TWI305674B - - Google Patents

Description

1305674 -MM 91123741_年月 η 倏正五, invention description (1) " FIELD OF THE INVENTION The present invention relates to a semiconductor process, and more particularly to an isolation structure and a method of forming the same to increase the active area Blemish current and improve insulation characteristics to reduce leakage current. Description of Related Art: The 'local enthalpy oxidation method (L〇c〇S) and shallow trench isolation zone processes are the two most commonly used techniques in various 7L isolation technologies, especially the latter, with small isolation regions and after completion It still maintains the advantages of flatness of the substrate, and is a semiconductor manufacturing technology that has recently received considerable attention. The -f 1 a to Id diagram depicts a cross-section that conventionally forms a shallow trench isolation structure. First, please refer to the figure 丨a, sequentially forming a pad 〇xide 1〇2 on a substrate 1 , surface, and a tantalum nitride layer blocking sound (4) lb diagram, The nitrogen cut layer 104 is coated with light - I ^ Β , 1 ^ and its pattern is defined by a lithography procedure to expose portions of the trench isolation regions to be formed. The benzene screen is sequentially engraved with the nitride layer 104' of the photoresist pattern layer 106 as a cover in the substrate 100 to form the Fuxi layer 0 port 4, the helium fossil layer 102 and the substrate 1〇〇 as Car+. λ plural An opening 108 for defining an active area of the component

Uctlve area) and isolation area. Next, please perform a thermal oxidation procedure, and =, after stripping the photoresist pattern layer 106, as a lining yttrium oxide I (not in contact with the surface growth of 08 - thin yttria vapor deposition method) (high d,, 's not followed, using high-density plasma chemical ruthenium nitride layer 104 on the Platinum CVD, HDPCVD), at 108. ΐ, 氧化 氧化 夕 layer (not shown), and filled Opening—~~ -1^__Chemical mechanical grinding (CMP) program to remove nitrogen H1! ι·.Τ丨WPU.”. _

$ 5 page 1305674

Correct the oxidized stone on the evening of the evening layer to form the surface tan. After taking it, please refer to the 1st d diagram to remove the tantalum nitride layer 104 and the oxygen=矽 layer 1 0 2 to complete the shallow trench. Slot isolation process. However, the CMP process used in the above shallow trench isolation process is difficult to control the polishing end point, which affects the process stability and increases the manufacturing cost. Further, during the etching to form the trench, the substrate is easily damaged to generate a leakage current. Further, the bottom surface area of the conventional shallow trench isolation structure is smaller than the upper surface area as shown in the first IdB1. - Aspect 'The area of the active area is limited by the surface area above the isolation structure and cannot be increased. Therefore, it is impossible to increase the drain current by increasing the diffusion area, so that the operation speed cannot be improved, and on the other hand, the isolation structure Since the bottom surface area is smaller than the upper surface area, the leakage path cannot be increased, so that the leakage current cannot be lowered and the Motomachi dependency is lowered. SUMMARY OF THE INVENTION In view of the above, it is an object of the present invention to provide an isolation structure and a vertical formation: a method of forming an isolation structure having an upper surface area smaller than a bottom surface area on a substrate to replace a shallow pomelo having a conventional upper surface area larger than a bottom surface area. _ off-structure (STI), thereby extending the component leakage path and increasing the insulation θ '! Another object of the present invention is to provide an isolation structure and a method for forming the same, which form an active region having a bottom surface area smaller than an upper surface area between the isolation structures by an epitaxial growth method, thereby increasing the active area area and increasing the area. Current.

Page 6 1305674

According to the above object, the present invention has a substrate, a semiconductor layer and two insulating layers as an active region. Among them, half surface area. Further, the two insulating layers are provided on both sides of the conductor layer as the two isolations are smaller than the bottom surface area thereof. Further in accordance with the above objects, the present method. First, a layer is formed on a substrate to form at least one tapered isolation region therein. Wherein the surface area above the bottom surface area of the opening is smaller than the bottom surface of the conductor layer as the active area. An isolation structure is provided that includes layers. The semiconductor layer is disposed on the substrate. The bottom surface area of the limb layer is smaller than the upper surface of the layer and adjacent to the half region. Wherein, the upper surface of the insulating layer provides an insulating layer for forming an isolation structure. Next, the rice is insulated and the openings are defined on both sides of the opening to be smaller than the upper surface area and isolated. Finally, a half-crystal growth method is formed in the opening, in which the semiconductor substrate is formed into a layer of a layer and formed by a temperature range of 0 C 0 ° C to 1 0 0 ° °. Further, the insulating layer is a ruthenium oxide layer or a tantalum nitride layer. Furthermore, the opening has a positive trapezoidal profile and the isolation region has an inverted trapezoidal profile. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT: A cross-sectional view of a shallow trench isolation structure in accordance with an embodiment of the present invention will be described below in conjunction with FIGS. 2a through 2d. First, please refer to Fig. 2a' to provide a substrate 20 〇, such as a ruthenium substrate, to form an insulating layer 2 〇 2 on the surface of the substrate 2000. In this embodiment, the thickness of the insulating layer 20 2 is in the range of 20 〇〇 to 300 Å (A), and it is preferably

1305674

ί :: The layer is composed. In 6, the method of forming the ruthenium oxide layer may be the use of tetraethyl phthalate (TEOS) in the thermal chemistry or chemical vapor deposition (chemical Vap〇r deP^S1 ΐ1〇η, CVD). A layer of ruthenium oxide formed. For example 'atmospheric, low pressure (i〇w

PreSSUre) or plasma enhanced chemical vapor deposition. Further, the method of forming a tantalum nitride layer can be deposited by using a low pressure chemical vapor deposition method using dichlorosilane (SidA) and ammonia gas (〇3) as raw materials. Next, please refer to FIG. 2b to apply a layer of photoresist layer (not shown) on the surface of the insulating layer 2 〇 2 . Thereafter, a plurality of openings 2 〇 6 ′ are formed in the photoresist layer by a conventional lithography process to define an isolation region. Next, please refer to the 2c figure, by using the photoresist pattern layer 2 0 4a having the opening 2 〇6 as the money mask, and simultaneously performing the isotropic and anisotropic etching 'red' such as the reactive ion I The insect engraving (reac seven ivei 〇ne schne, RIE) 'exposes the surface of the substrate 200 with the insulating layer 202 under the opening 206, and forms a plurality of tapered openings 2 〇8 in the insulating layer 220. In the present embodiment, the tapered opening 2 〇 8 formed in the insulating layer 2 〇 2 has a lower surface area smaller than its upper surface area. For example, the tapered opening 2 〇 8 has an inverted trapezoidal profile. As a result, the surface area of the remaining insulating layer 20 2 on both sides of the opening is smaller than the bottom surface area. For example, the remaining insulating layer 202 has a positive trapezoidal cross section. Wherein, the tapered openings 2 〇 8 are both sides as the isolation region 'the remaining insulating layer 20 2 constitutes the isolation structure 20 2a, and the opening '0 8 8 is used as the active region of the component in the subsequent process. . Finally, please refer to FIG. 2d, after removing the photoresist pattern layer 2 0 4 by appropriate etching solution or ashing treatment, 'forming a semiconductor layer 21 0 in the opening 2 〇 8 to 1305674 No. 91123741 曰 Amendment 5, invention description (5) As the active area of the component. In this embodiment, the semiconductor layer 210 may be a litho layer and may be subjected to epitaxial growth, such as solid phase epitaxy (SPE) or molecular beam crystallization ( The molecular beam epitaxy (MBE) and liquid phase epitaxy (LPE) are formed at a temperature ranging from 900 t: to 1000 t:, and a preferred formation temperature is about 9 7 ° C. Furthermore, the thickness of the semiconductor layer 210 is substantially the same as that of the isolation structure 2 〇 2 a . In this way, the isolation structure of the embodiment of the present invention is completed. Similarly, please refer to Fig. 2d, which shows a schematic cross-sectional view of the isolation structure 20a according to an embodiment of the present invention. It comprises a substrate 2 〇〇, a plurality of semiconductor layers 210 and a plurality of isolation structures 2 〇 2a. In this embodiment, the substrate 2 can be a germanium substrate; the semiconductor layer 210 is a germanium layer and can be formed by a crystal growth method at a temperature of about 190 C to 1 0 0 t: The insulating layer 2 〇 2 a may be a ruthenium oxide layer or a tantalum nitride layer, and has a thickness substantially the same as that of the semiconductor layer 21 且 and about 2,000 to 300 Å, which can be formed by chemical vapor deposition. The semiconductor layer 210 is disposed on the substrate 2 to serve as an active region. In the basin, the bottom surface area of the semiconductor layer 210 is smaller than the upper surface area thereof. For example, a semi-two layer 21 〇 has an inverted trapezoidal profile. Further, the isolation structure 2Q2a is disposed on the substrate 200 and adjacent to both sides of the semiconductor layer 21, respectively, as an isolation region. Conversely, the surface area above the isolation structure 202a is less than the soy. For example, the isolation structure 20 2 a has a positive trapezoidal cross section. ^ Compared with the shallow trench isolation process of the transmission and the system, the present invention does not need to utilize cMp 'HI, which does not have difficulty in controlling the polishing end point, and the process reliability is reduced, and the manufacturing cost can be reduced. Furthermore, the spacer structure of the present invention is formed on the substrate instead of forming a trench by etching the substrate.

Page 9 1305674 . _ Case No. 91123741_年月日日_i±i, _ V, invention description (6) formed by filling the trench with an insulating layer. Therefore, no damage is caused to the substrate and leakage current is generated. In addition, in the conventional shallow trench isolation structure, the area of the active region is limited by the surface area above the isolation structure and cannot be increased. However, in the isolation structure according to the present invention, the upper surface area of the active region is increased by the reduction of the upper surface area of the isolation structure, so that the diffusion area can be increased to increase the drain current. That is to increase the operating speed. Furthermore, since the surface area of the isolation structure of the present invention is smaller than the bottom surface area thereof, the leakage path can be effectively extended, resulting in a decrease in leakage current and an increase in reliability of the element. While the present invention has been described in its preferred embodiments, the present invention is not intended to limit the invention, and the invention may be modified and retouched without departing from the spirit and scope of the invention. The scope of protection is subject to the definition of the scope of the patent application attached.

</ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; A detailed description is as follows:

1a to 1d are diagrams showing a conventionally formed shallow trench isolation structure. Figs. 2a to 2d are schematic cross-sectional views showing the formation of shallow trench isolation structures in accordance with an embodiment of the present invention. [Description] 100, 20 0~ substrate; 1 0 2~ pad oxide layer; 1 0 4~ tantalum nitride layer; 106, 204a~ photoresist pattern layer; 1 0 8 , 2 0 6 , 2 0 8 ~ Opening; 11 0, 20 2a~ isolation structure; 2 0 2~ insulating layer; 21 0~ semiconductor layer.

Page 11

Claims (1)

1305674 _ Case No. 91123741_Yearly revision _6. Patent application scope 1. An isolation structure comprising: a substrate; a semiconductor layer disposed on the substrate as an active region, wherein a bottom surface area of the semiconductor layer is smaller than The upper surface area; and two insulating layers are disposed on the substrate and adjacent to the two sides of the semiconductor layer respectively as two isolation regions, wherein the surface area above the insulating layers is smaller than the bottom surface area thereof. 2. The isolation structure of claim 1, wherein the substrate is a broken substrate. 3. The isolation structure of claim 2, wherein the semiconductor layer is a layer of germanium. 4. The isolation structure of claim 3, wherein the stone layer is formed by a crystal growth method. 5. The isolation structure according to claim 4, wherein the temperature of the ruthenium layer is in the range of 900 ° C to 1 0 0 ° C. 6. The isolation structure of claim 1, wherein the insulating layer is a ruthenium oxide layer. 7. The isolation structure of claim 1, wherein the insulating layer is a nitride layer. 8. The isolation structure of claim 1, wherein the semiconductor layer has an inverted trapezoidal cross section and the insulating layers have a positive trapezoidal cross section. 9. The isolation structure of claim 1, wherein the thickness of the semiconductor layer is substantially the same as the thickness of the insulating layers and is at 2000~ Page 12 1305674 _ Case No. 91123741_Yearly 曰 Amendment _ Six, the scope of the patent application range of 300 angstroms. A method of forming an isolation structure, comprising the steps of: providing a substrate; forming an insulating layer on the substrate; etching the insulating layer to form at least one tapered opening in the insulating layer The side defines two isolation regions, wherein the bottom surface area of the opening is smaller than the upper surface area thereof, and the surface area above the isolation regions is smaller than the bottom surface area thereof; and a semiconductor layer is formed in the opening as the active region. II. A method of forming an isolation structure as described in claim 10, wherein the substrate is a stone substrate. A method of forming an isolation structure as described in claim 1 wherein the semiconductor layer is a layer of germanium. 1 3. A method of forming an isolation structure as described in claim 12, wherein the fragmentation is formed by a crystal growth method. 1 4. The method of forming an isolation structure according to claim 13 wherein the temperature of the ruthenium layer is in the range of 900 ° C to 1 0 0 ° C. A method of forming an isolation structure as described in claim 10, wherein the insulating layer is a layer of oxidized stone. 1 6. The method of forming an isolation structure according to claim 10, wherein the insulating layer is a nitride layer. 1 7. The method of forming an isolation structure of claim 10, wherein the opening has an inverted trapezoidal profile and the isolation regions have a positive trapezoidal profile. Page 13 1305674 . _ Case No. 91123741_年月曰 _ _ _ 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 The thickness of the isolation region is in the range of 2000 to 3000 angstroms. Page 14 1305674 Page 3