513775513775
發明領域： 本發明係有關於一種半導體製程技術，且特別有關於 一種在半導體基底上隔離元件的方法。 發明背景： 近年來，隨著半導體積體電路製造技術的發展，晶片 T所含元件的數量不斷增加，元件的尺寸也因積集度的提 二而不斷地縮小，生產線上使用的線路寬度已進入深次微 米甚或更細微尺寸的範圍。而無論元件尺寸如何縮小化， f晶片中各個元件之間仍必須有適當地絕緣或隔離，方可 得到良好的元件性質。這方面的技術一般稱為元件隔離技 術（device isolation technology)，其主要目的係在各 元件=間形成隔離物，並且在確保良好隔離效果的情況下 ’儘量縮小隔離物的區域，以空出更多的晶片面積來容納 更多的元件。 在各種元件隔離技術中，局部矽氧化方法（L〇c〇s)和 淺溝槽隔離區（shallow trench isolation ;STI)製程是 最常被採用的兩種技術，尤其後者具有隔離區域小和完成 後仍保持基底平坦性等優點，更是近來頗受重視的半導體 製造技術。一般的淺溝槽隔離製程，係先在基底上蝕刻出 溝槽，然後利用化學氣相沈積（CVD )程序，將氧化矽填入 基底的溝槽中，之後再以化學機械研磨程序（CMp)去除多 餘的介電層，以完成溝槽隔離製程。 ” —然而，隨著元件積集度的提昇，淺溝槽的尺寸也不斷 縮小的情況下，當氧化矽填入溝槽時便容易形成所謂孔洞FIELD OF THE INVENTION The present invention relates to a semiconductor process technology, and more particularly, to a method for isolating components on a semiconductor substrate. Background of the Invention: In recent years, with the development of semiconductor integrated circuit manufacturing technology, the number of components contained in wafer T has been increasing, and the size of components has been continuously reduced due to the increase in the degree of integration. Enter the range of deep sub-micron or even finer size. Regardless of how the component size is reduced, the various components in the f-chip must still be properly insulated or isolated to obtain good component properties. This technology is generally called device isolation technology, and its main purpose is to form spacers between components and to ensure a good isolation effect. More chip area to accommodate more components. Among various element isolation technologies, the local silicon oxidation method (LoCos) and shallow trench isolation (STI) process are the two most commonly used technologies, especially the latter has a small isolation area and complete Later, the advantages of maintaining the flatness of the substrate and the like are even more recent semiconductor manufacturing technologies. In the general shallow trench isolation process, a trench is etched on the substrate, and then a silicon oxide is filled into the trench of the substrate by a chemical vapor deposition (CVD) process, and then a chemical mechanical polishing process (CMp) is performed. The excess dielectric layer is removed to complete the trench isolation process. ”—However, with the increase of the component accumulation, the size of the shallow trenches is also shrinking. When silicon oxide fills the trenches, it is easy to form so-called holes.
513775 五、發明說明（2) (void)，或鑰匙孔（keyhole)的情況。形成孔洞的 是因為以傳統的化學氣相沈積法沈積氣化矽時，' ， 淺溝槽的頂端容易形成懸突物。如第1圖所示’ 4 @在 製程常遭遇的問題便是溝槽中會形成孔洞。 ^離 16〇填入溝槽丨4〇時，溝槽140在靠近頂端的部^分通备找 =窄，使得後續的氧化石夕無法完全填入 ？ 下孔洞200。孔洞的存在會使得污染物容易殘^此/ 造成污染，並使得淺溝槽隔離區最後％ /5 動區表面。除此之外，亦會增加接ί石夕表面低於主 槽見度可以避免孔洞的形成，然而， ； 溝 件密度。 ★此一來部降低了元 因此，為了使元件隔離的技術更臻於完善 楗出一種能夠解決孔洞問題，同時又能513775 V. Description of the invention (2) (void), or the case of a keyhole. The holes are formed because when the vaporized silicon is deposited by the conventional chemical vapor deposition method, the overhangs are easily formed at the tops of the shallow trenches. As shown in Figure 1, a problem often encountered in the process is the formation of holes in the trenches. ^ When the trench is filled at 16 o 4 o, the trench 140 is close to the top of the trench. ^ It is easy to find = narrow, so that the subsequent oxide stone cannot be completely filled? Under the hole 200. The existence of holes will make the pollutants more likely to remain / cause pollution, and make the shallow trench isolation area last 5% of the surface of the moving area. In addition, it will also increase the visibility of the surface of the stone below the main groove to avoid the formation of holes, however; the density of the grooves. ★ This reduces the element. Therefore, in order to make the technology of component isolation more perfect, we have come up with a solution that can solve the problem of holes.
件隔離技術。 允σ午四積集度的7C 發明概述： 有鑑於此，本發明的主要目 離製程以克服孔洞形成的問題，廿^ = k供一種新穎的隔 力。 ㈣問《亚兼顧高積集度的隔離能 程，ί·中隔以i ::二的：本發明提供-種新穎的隔離製Piece isolation technology. 7C Summary of the Allowable Noon-Fourth Product Integration: In view of this, the main purpose of the present invention is to separate the manufacturing process to overcome the problem of hole formation. 廿 ^ = k provides a novel barrier. Ask "The isolation energy process that takes into account the high accumulation degree, ·· separated by i :: two: the present invention provides a novel isolation system
層，鈇後將此^離^ M係在半導體基底上沈積一層隔離 層’、、、後將此隔離層定義成複數個平A 為隔離區。此方法有別於傳=十σ狀（託別3)，以作 isolation pr〇Cess) 將 離製程 避免孔洞的形成。依照本發物2溝槽中，：此可 ^另一項特徵，在定義出隔 五、發明說明（3) 離區之後，係設置_主$ 1 # A t i Μ ' 4· A + ^體層在任意兩個隔離區# _ :為+導體元件的主動區。易言 <，半導 卜間’以 在新生“半導體層上，而非原本的基底上。將會形成 依知本發明的方沾^ 认, 套，其主要步驟包括：形士 :;i導iiii;定義隔離層以形成至少兩隔離層 啼t 導層於基底上，且其厚度至少離平台 I為：：二：：：f體層進行平坦化直到露出：：上述隔 元;i主::在兩個隔離平台之間形成-半導體；隔= 依照本發明之另一， 離層於-半導體基底上要步驟包括：形成 義光阻層以形成一罩幕圖案 ：：：該隔離層上；定 的反向圖案，·以上述光：貝2預定形成主動區 =隔：層’藉此形成複數個隔罩L非等向性地餘 成了半導體層於基底i，且 声:丄去，光阻圖案；形 f，以及對半導體層進行平扫化二到二覆蓋住上述隔離平 止杜藉此在上述隔離平台：間η出上述隔離平台： 70件之主動區。 成個半導體區，作為 為讓本發明之上述和盆 顯易懂，下文特舉出較佳實：：的尤::；、和優點能更明 細說明如下·· 配合所附圖式，作詳 圖式之簡單說明 孔洞第1圖係顯示習知的溝槽隔離製程令，填溝所產生之 第8頁 0702-7058TWF ; 90Ρ86 ; Esmond.ptd 五、發明說明（4) 第2 6圖為一系列剖面圖 施例之元件隔離製程。 符號說明 用以說明本發明一較佳實 1 2〜氧化層； 1 6〜隔離層； 1 8〜光阻圖案； 20a-d〜主動區； 100〜半導體基底； 160〜介電材料； 10〜半導體基底； 1 4〜氮化層； IGa-c〜隔離平台 20〜半導體層； 〜MOS電晶體； 1 4 0〜隔離溝槽； 2 0 0〜孔洞。 實施例 請參閱第2至6圖，其顯示本發明 兀件隔離製程。第2圖顯示一半導 #乂仏貝施例/之 一層用來作為隔離元件的隔離/(i s 土 & .，其上覆盍有 ,^ ^ J 1网雕層 u s〇lation layer)16。 種絕緣㈣，並可為單層或由 數廣，丨電層堆豐而纟。在本實施例中，隔離層16是由一声 乳化層12與-層氮化層U所構成，其中氮化層14設於氧^匕 層1 2上，以在後續的研磨程序中作為研磨終止層。在其他 實施例中，隔離層1 6亦可使用本身能作為研磨終止層的單 一絕緣材料，例如，氮化矽、矽碳化物（si丨ic〇n 早 carbide)、鑽石等。氧化層12可熱氧化法形成，或以習知 的常壓或低壓化學氣相沈積法（Low Pressure CVD)沈積而 成。氮化層1 4通常則是以低壓化學氣相沈積法，利用二氯 石夕烧（SiCl2H2)與氨氣（關3)為反應氣體沈積而成。氧化展'This layer is used to deposit an isolation layer on the semiconductor substrate, and then this isolation layer is defined as a plurality of planes A as an isolation region. This method is different from pass = ten sigma (sub-part 3), which is used as isolation pr0Cess) to separate the process to avoid the formation of holes. According to the groove of this article, this: ^ Another feature, after defining the fifth, invention description (3) after leaving the zone, set _ 主 $ 1 # A ti Μ '4 · A + ^ body layer In any two isolation areas # _: is the active area of the + conductor element. Easy to say, the semi-conductor is used on the nascent "semiconductor layer, instead of the original substrate. A square electrode according to the present invention will be formed. Its main steps include: Iiiiiii; define an isolation layer to form at least two isolation layers; the conductive layer is on the substrate, and its thickness is at least from the platform I :: 2 ::: f body layer is flattened until exposed :: the above-mentioned spacer; i main: : Forming a -semiconductor between two isolation platforms; according to another aspect of the present invention, the steps of delaminating on a -semiconductor substrate include: forming a photoresist layer to form a mask pattern :: on the isolation layer; A predetermined reverse pattern, with the above-mentioned light: shell 2 is scheduled to form an active area = barrier: layer 'to form a plurality of barriers L anisotropically remaining semiconductor layers on the substrate i, and sound: Photoresist pattern; shape f, and flat sweeping of the semiconductor layer to cover the above-mentioned isolation plane, so as to form the above-mentioned isolation platform at the isolation platform: between n and 70 active regions. Form a semiconductor region, In order to make the above-mentioned sum of the present invention easier to understand, the following comparison Jiashi :: you ::;, and the advantages can be explained in more detail as follows: • In conjunction with the drawings, a brief description of the holes is shown. Figure 1 shows the conventional trench isolation process order and trench filling site. Produced page 8 0702-7058TWF; 90P86; Esmond.ptd V. Description of the invention (4) Figure 26 shows a series of cross-sectional views of the component isolation process of the embodiment. The symbol description is used to illustrate a preferred embodiment of the present invention. 1 2 ~ Oxide layer; 16 ~ isolation layer; 18 ~ photoresist pattern; 20a-d ~ active area; 100 ~ semiconductor substrate; 160 ~ dielectric material; 10 ~ semiconductor substrate; 1 4 ~ nitride layer; IGa-c ~ Isolation platform 20 ~ Semiconductor layer; ~ MOS transistor; 1 40 ~ Isolation trench; 2 00 ~ Hole. For examples, please refer to Figs. 2 to 6, which show the isolation process of the element of the present invention. Fig. 2 shows The half-conductor # 乂 仏 贝 例 / one layer is used as the isolation of the isolation element / (is soil &., Which is overlaid with, ^ ^ J 1 网 雕 层 us〇lation layer) 16. Kind of insulation, It can be a single layer or a large number of electrical layers. In this embodiment, the isolation layer 16 is an acoustic emulsion layer 12 And a nitride layer U, wherein the nitride layer 14 is disposed on the oxygen layer 12 to serve as a polishing stop layer in the subsequent polishing process. In other embodiments, the isolation layer 16 can also be used A single insulating material that can itself be used as a polishing stop layer, for example, silicon nitride, silicon carbide (carbide), diamond, etc. The oxide layer 12 can be formed by a thermal oxidation method, or by conventional atmospheric pressure or Low pressure chemical vapor deposition (Low Pressure CVD) deposition. The nitride layer 14 is usually a low pressure chemical vapor deposition method, using dichlorite sintering (SiCl2H2) and ammonia (off 3) as the reaction gas Deposited. Oxidation Exhibition '
0702-7058TWF ； 90P86 ； Esmond.ptd 第9頁 513775 五、發明說明（5) 1 入2的厚度較佳大於2_人，氮化川的厚度較佳大於圆 第3 =示係將基底上的隔離層} 6定義成複數個隔離 千口（1S〇lat1〇n mesas)16a、16b、16c。首先， 基底10上覆蓋一層可用來作為蝕刻罩幕的材料，例如光 η ”傳統的微影技術將此光阻層定義成一罩幕圖 案8 ’其貫貝上為預定形成的主動區的反向圖案（reverse active area mask)。然後，以光阻圖案“為蝕刻罩 LI氮='1氧化層12，便可得到如圖中所示的隔 ^千口 a_、16b、16C。此蝕刻程序可使用反應性離子蝕 J、化學電漿姓刻、或其他任何非等向性的 (anisotropic)蝕刻技術。 請參閱第4圖，去除光阻圖案18之後，沈積一声 體層20覆蓋在基底10上，且其厚度至少將隔離平台曰…、 16b、16c完全覆蓋住。此半導體層2〇例如是一層蟲晶矽 層，其可利用矽烷氣體在7〇〇〜U5〇t：的溫度範圍下形 半導體層20亦可能是一層複晶石夕層，以低壓化學氣 法，利用矽烷氣體在5 75~65〇艺的溫度範圍下沈積而、 此外，由於半導體層後續將作為元件的主動區，因此 視需要而定，將p型離子（如硼）型離子（如磷或 在半導體層2 0中。 > 雜 、，第5圖所不係將半導體層2 0加以平坦化直到露出隔離 平台16a、16b、16c的表面。半導體層2〇的平坦化可採 回蝕刻或化學機械研磨（Chemical_Mechanical ρ〇ι “Η叫 第10頁 0702-7058TWF i 90P86 i Esmond.ptd 513775 五、發明說明（6) ------------ ^鞋序。較佳者，係使用化學機械研磨法並以氮化層 二研磨時的終止層。如此一來，半導體層所殘留下來 1 Ϊ ί成為由數個隔離平台16a、16b、16C所交替分離 Λ/區20a、20b、20c、2〇d。因此，半導體區2〇a、 c 便成為主動區，其上 半導體 ， :::=、—便成為隔， 20a之9^ ’便可依照習知的半導體製程，在主動區 電曰體V 20d上製作所需要的任意元件，例如廳 製】,：邏輯元件等。第6圖係用以舉例說明當MOS 電日日體製作在主動區20b、20C上的情形。 κ:!!別注意的是’由於上述的隔離區16a、l6b、16c 疋厶由一隔離層丨β蝕刻而成， 槽而得，因此可以避免傳統溝槽= 電材料填入溝 良而形成孔洞的問㉟。此外，❹ :丁 目為填溝不 層/氧化層作為隔離層】6，但本發明例中是以氣化 發明可使用任何適當的介電材 範圍不限於此，本 雖然本發明已以較佳實施例揭 2 限定本發明，任何熟習此技藝者， 、，：、、;、其並非用以 和範圍内，當可作些許之更動與潤不脫離本發明之精神 範圍當視後附之申請專利範圍^ .因此本發明之保護 |疋為準。 0702-7058TWF ； 90Ρ86 ； Esmond.ptd $ 11頁0702-7058TWF; 90P86; Esmond.ptd Page 9 513775 V. Description of the invention (5) 1 The thickness of 2 is preferably larger than 2_person, and the thickness of nitrided river is preferably larger than the circle. Isolation layer} 6 is defined as a plurality of isolation ports (1Solat10n mesas) 16a, 16b, 16c. First, the substrate 10 is covered with a layer of material that can be used as an etching mask. For example, the traditional photolithography technology defines this photoresist layer as a mask pattern 8 '. The reverse of the predetermined active area is formed on the substrate. Pattern (reverse active area mask). Then, using the photoresist pattern "for the etch mask LI nitrogen = '1 oxide layer 12," as shown in the figure can be obtained a thousand, a, 16b, 16C. This etching procedure can use reactive ion etching J, chemical plasma etching, or any other anisotropic etching technique. Referring to FIG. 4, after removing the photoresist pattern 18, an acoustic layer 20 is deposited to cover the substrate 10, and the thickness of the acoustic layer 20 completely covers at least the isolation platforms…, 16b, 16c. This semiconductor layer 20 is, for example, a worm crystal silicon layer, which can use silane gas at a temperature range of 700 to U50 t: The semiconductor layer 20 may also be a polycrystalline stone layer. , Using silane gas deposition in the temperature range of 5 75 ~ 650, and in addition, since the semiconductor layer will be used as the active area of the device in the future, as needed, p-type ions (such as boron) Or in the semiconductor layer 20. > The semiconductor layer 20 is not planarized until the surface of the isolation platforms 16a, 16b, 16c is exposed in FIG. 5. The planarization of the semiconductor layer 20 can be etched back. Or chemical mechanical grinding (Chemical_Mechanical ρ〇ι "Howling page 10 0702-7058TWF i 90P86 i Esmond.ptd 513775 V. Description of the invention (6) ------------ ^ Shoe order. Better That is, the stop layer when using the chemical mechanical polishing method and polishing with the nitride layer 2. In this way, the semiconductor layer remains 1 ί becomes alternately separated by a plurality of isolation platforms 16a, 16b, 16C Λ / zone 20a 20b, 20c, 20d. Therefore, the semiconductor regions 20a, c become The active area, on which the semiconductor, ::: =,-becomes a partition, 9 ^ 'of 20a can be used to produce any required components on the active area V 20d according to the conventional semiconductor process, such as the hall system] ,: Logic elements, etc. Figure 6 is used to illustrate the situation when the MOS electric solar body is made on the active areas 20b and 20C. Κ: !!疋 厶 is formed by a β etched from an isolation layer and obtained from a trench, so that the problem of traditional trenches = electrical materials filling the trenches and forming holes can be avoided. In addition, ❹: the trench filling layer / oxide layer is used as Isolation layer] 6, but in the example of the present invention, any suitable dielectric material can be used in the gasification invention. The scope is not limited to this. Although the present invention has been described in the preferred embodiment 2 to limit the invention, anyone skilled in this art, ,,: ,, ;; It is not intended to be used within the scope. When some changes and modifications can be made without departing from the spirit of the present invention, the scope of the appended patents shall be regarded as ^. Therefore, the protection of the present invention shall prevail. 0702-7058TWF; 90P86; Esmond.ptd $ 11 pages