1299897 九、發明說明： 【發明所屬之技術領域】 本發明係提供一種應用於積體電路 衣i尾路板制 造方法，尤指一種可降低成本之積體電路封裝製程。x 【先前技術】1299897 IX. Description of the Invention: [Technical Field] The present invention provides a method for manufacturing an integrated circuit board, particularly an integrated circuit packaging process capable of reducing cost. x [prior art]
按，傳統印刷電路板之製造 負片製程； 其中傳統正片之製造流程，括： 方法，包括有正 片製裎與 如第三圖所示，其 步驟包Press, the manufacturing process of the traditional printed circuit board; the manufacturing process of the traditional positive film, including: the method, including the positive film and the step shown in the third figure, the step package
A 其上、下層鋼面導通； X 2 :線路製作：運用液態油墨或感光型油墨，透尚 底片與光源曝光原理形成線路，#以化學方式去除非線： 表面油墨，使該表面露出銅層部份； 、 X 3 :線路蝕刻：將露出之銅層運用化學腐蝕分 理，使銅完全去除，而留下油墨保護之線路； ” X 4 ·線路表面處理：將留 竹㈢卜之綠路表面油墨去除後， 將路出之銅面依雲灰辦：卜於人接^^ 攸而求鍍上付合積體電路封裝（c〇b)製程之 金屬層。 藉由上迷印刷電路板之製程後，可進行積 (COB)的製程，昔本 合止认 先，θ先於上述之積體電路封裝（COB)製 程之：屬曰杈導線，再進行模壓封膠’藉以完成封裝製程。 然而，由於印刷電路板在線路蝕刻之步驟，將不要之 銅層蝕刻掉唆’因Λ，在線路表面處理將出之銅面依需求 5 1299897 上爲人^ 付5積體電路封裝（C0B)製程之金屬層後，需將先前串 於打線焊點（bonding pad)之導線一併去除如此之製程 將又到拉導線佔據佈線面積之限制。 另由於不要之銅層蝕刻掉後，會形成正反表面積 同之鋼夺而 回’而面積小之銅層吸收電流速度較快，面積較 之鋼層吸收電流速度較慢，會使兩面積不同之銅層之 成鍍層厚许π μ 乂 予度不均，造成在後段模壓封膠製程時，因板厚言 低不斗》 卞而造成溢膠之情形。 另夕卜 ’傳統之負片之製造流程，如第四圖所示，如篦甘 步驟包括： 如弟其 γ 1 ^ •化學貫孔：於銅電路板上做化學貫孔（ρτΗ) 具上、T S 災 卜層銅面導通； 底片!2、:線路製作：*用液態油墨或感光型油墨，透過 面油：光源曝光原理形成線路，#以化學方式去除線路表 使5亥線路表面露出銅層部份； 於線路=·線路保護：將露出銅層之線路表面以電解方式， Υ、面直接鍍上錫金屬保護層，以保護線路之完整性； 分解原理線路蝕刻：將非線路銅層表面之油墨運用化學 學蝕刻原使之％全去除乾淨而留下非線路銅層；再以化 層去r二將非線路銅面完全去除，最後再將保護錫金屬 无除而留下線路銅層； 將露出、良路表面處理··將留下之線路表面油墨去除後， 金屬層。_面依需求鍍上符合積體電路封裝(COB)製程之 6 1299897 上述印刷電路板傳統之負片製程，較正1製程需要多 一道線路保護之步驟，且在鑛上錫後，亦需要-董剝锡之 步驟，因此步驟較為繁複，且製造成本亦較高。 緣此，本發明人針對上述習知印刷電路板所存在 題點，藉由多年從事相關領域之研究與製造開[經詳 設計與審慎評估後，終於創 ° 於劁&出種可改進上述缺點，且 更具理想實用性之應用於藉栌雪欠 ^用於積體電路封裝之電路板製造方 法。 【發明内容】 欲解決之技㈣題點：習知積體電路封裝⑽ 統製造方法，包括有正片製程與負片製程： 其中正片製程步驟包括有化學貫孔、線路製作、線雜 名虫刻及線路表面處理·妙& ㈣理H由於線路㈣後，會形成床 表面積不相同之銅表面， 主 u此絰過（COB)表面鍍層製程後 易形成鍍層之厚度不均規务 子厪不均現象，且在積體電路封裳（⑶…的# 壓封膠製程時，容易因高 ）的才1 门他不十而造成杈壓溢膠；再 僅留下一部份需要之綠» 而要之線路，在積體電路封裝 線的製程設計時，會使佑綠々工. )而要拉与 曰便佈線之面積受到限制。 另外，負片製造步驟包括 v匕括.化學貝孔、線路製作、潑 路保4、線路蝕刻及線路表 需要多-道線…之: 由於負片^ 剥錫之步驟，因此製造成本較高。 而要^ 解決問題之技術特點： 電 不&明係梃供一種應用於積旁 路封農之電路板製造方法，其步驟包括： 1299897A The upper and lower steel surfaces are turned on; X 2 : Line production: using liquid ink or photosensitive ink, through the film and light source exposure principle to form a line, # chemically remove the non-line: surface ink, the surface is exposed to the copper layer Part; X 3 : Line etching: the exposed copper layer is chemically etched to completely remove the copper, leaving the ink protection line; ” X 4 · Line surface treatment: will leave the bamboo (three) Buzhi Green Road After the surface ink is removed, the copper surface of the road will be ridden by the cloud: the copper layer is coated with the metal layer of the integrated circuit package (c〇b) process. After the process, the COB process can be performed. The θ is prior to the above-mentioned process. The θ is prior to the above-mentioned integrated circuit package (COB) process: it is a wire, and then the molding is sealed to complete the packaging process. However, due to the step of etching the printed circuit board, the unnecessary copper layer is etched away. Because of the flaw, the copper surface will be treated on the surface of the line. According to the demand 5 1299897, the 5 integrated circuit package (C0B) After the metal layer of the process, the previous The removal of such a process from the wire of the bonding pad will limit the wiring area of the wire. In addition, since the copper layer is not etched, the positive and negative surface area will be formed. The copper layer with a small area absorbs the current faster, and the area absorbs the current slower than the steel layer, which causes the thickness of the copper layer of the two different areas to be π μ 乂 uneven, resulting in the later stage molding and sealing process. At the time, because of the thick words of the board, it is caused by the smashing of the sputum. In addition, the manufacturing process of the traditional negative film, as shown in the fourth figure, such as the 篦甘 step includes: 弟其其γ 1 ^ • Chemistry Through hole: chemical through hole on the copper circuit board (ρτΗ), TS trace copper surface conduction; negative film! 2, line production: * use liquid ink or photosensitive ink, through the face oil: light source exposure principle Forming the line, #chemically remove the line meter to expose the copper layer part of the surface of the 5 Hai line; in the line = · line protection: the surface of the line that exposes the copper layer is electrolyzed, and the surface of the copper layer is directly plated with a tin metal protective layer. Protect the line Integrity; Decomposition principle Line etching: chemically etch the ink on the surface of the non-line copper layer to remove all the non-line copper layer; then remove the non-line copper surface completely by the layer Finally, the protective tin metal is removed and the copper layer of the circuit is left; the exposed surface is treated, the surface of the circuit is removed, and the metal layer is removed. The surface is coated with the integrated circuit package (COB). Process 6 699897 The traditional negative film process of the above printed circuit board requires more steps of line protection than the 1 process, and after the tin is applied to the tin, the step of removing the tin is required, so the steps are complicated and the manufacturing cost is also Therefore, the present inventors have made research and manufacture for the above-mentioned conventional printed circuit boards by performing research and manufacturing in related fields for many years [after detailed design and careful evaluation, finally created a 劁 劁 & The circuit board manufacturing method for the integrated circuit package can be improved by the above-mentioned disadvantages, and is more ideally applicable. [Description of the Invention] Techniques to be Solved (4) Title: The conventional integrated circuit package (10) system manufacturing method includes a positive film process and a negative film process: wherein the positive film process steps include chemical through holes, line fabrication, line miscellaneous insects and Line surface treatment · wonderful & (4) rational H due to the line (four), will form a copper surface with a different surface area of the bed, the main u this (COB) surface coating process is easy to form a coating thickness unevenness irregularities Phenomenon, and in the integrated circuit seals ((3) ... #压封胶process, easy to be high), he does not cause the pressure to overflow the glue; only leave a part of the required green» The required line, in the process design of the integrated circuit packaging line, will make the green work.) The area of the wiring to be pulled and squatted is limited. In addition, the negative film manufacturing steps include v. In addition, chemical beading, line fabrication, splash protection 4, line etching, and wiring meters require multi-channels: due to the negative film ^ stripping step, the manufacturing cost is higher. And ^ to solve the technical characteristics of the problem: Electric does not & Ming system for a method of manufacturing circuit board manufacturing method, including: 1299897
步驟1、化與I 使其上、下心貝孔：於銅電路板上做化學貫孔(PTH)， r層銅面導通； 步驟2、線路製… 、 過底片與光源曝来=·運用液態油墨或感光型油墨，透 表面油墨，使該形成線路’再以化學方式去除線路 Μ、、、复路表面露出鋼層部份； 步驟3、線故主 後，所露出夕^ 、面處理：將留下之線路表面油墨去除 製程之金屬層；面依需求而鍍上符合積體電路封裝(⑽) 學二=:、1=刻：將非線路之銅層表面油墨運用化 化學蚀刻分解二…除’巾留下非線路銅層’再以 解原理將非線路銅層完全去除，只 體電路封裝α〇Β)製程之金屬表面； … 化二Π、、線路側面銅包覆：將線路側面露出之銅層以 子命飞接鍍上金屬保護層，以避免露鋼線路氧化； ^驟6、線路表面清潔··清潔積體電路封裝之表面。 藉此本發明由於線路表面處理之步驟已鍍上符合 體電路封裝（_製程之金屬層，可避免佈線時之面積多募 而產生南低電流效應，且不需將所有積體電路封裝（[⑽） 線路之接觸墊（PAD)串接導通，減少線路表面處理（步驟 3)時需增加拉導線之設計與佔用印刷電路板表面積空間， 可提高印刷電路板佈線面積。 對照先前技術之功效··提供一種應用於積體電路封震之 電路板製造方法，由於本發明係在線路蝕刻前已鍍上符人 積體電路封裝（COB)製程之金屬層，可避免佈線時 J心囬積多 8 1299897 暴而產生兩低電流效應，且不需將所有積體電路封穿（⑶b ) •線路之接觸墊（PAD)串接導通，改良習知線路鋼層\鍍層 厚度不均容易高低不平而造成晶片封裴時模壓溢膠，及佈 線之面積受到限制之缺點。 【實施方式】 •接下來會列舉一較佳實施例，並配合圖示及圖號，對 ^明其他的目的及效能做進一步的說明，期能使貴審查 :對本發明有更詳細的瞭解，並使熟悉 以實施，以下所沭去描士 只议術者月匕據 制本發明丄Γ 釋較佳實施例，而非在於限 為…凡有以本發明之發明精神為基礎，而 ’、、'，明之發明任何形式的變更或屬 圖保護之範疇。 ㈢屬於本發明意 本發明係提供一插虛田Μ 造方法。 Μ ν積體電路封裝之電路板製 首先，請參閱第一圄 牛_ , / 圖所不，其步驟包括： 步驟1 (S1)、化學I · (ΡΤΗ)，使其上、 予貝孔：於銅電路板上做化學貫孔 八 s鋼面導通； 步驟2(S2)、線路製 透過底片與光源曝光原 用液態油墨或感光型油墨， 層為A，油墨為B)，再以線路（如第二之一圖所示，銅 該線路表面露出銅層部=化學方式去除線路表面油墨，使 墨為B ‘，留下之油黑以，（如第二之二圖所示，去除之油 層A)。 /由墨β‘去除後可露出底下之銅 步驟3 (S3)、線路表 · 处理·將留下之線路表面油墨 9 1299897 去除後，所露出 (COB)製程之八M面依需求而鍍上符合積體電路封裝 墨B‘之地方铲 ^第一之三圖所示，在原本去除油 C);其中該積V:合積體電路封議B)製程之金屬層 另外，炫 路封裝（C0B)製程係以電解原理完成之。 表面鍍層元：：路表面處理之流程中’符纟_製程金屬Step 1, and I make the upper and lower core holes: make chemical through holes (PTH) on the copper circuit board, r layer copper surface conduction; Step 2, line system..., over the film and light source exposure = · use liquid Ink or photosensitive ink, through the surface ink, so that the formation of the line 'chemically remove the line Μ,, the road surface to expose the steel layer part; Step 3, the line after the main, exposed 夕 ^, surface treatment: The metal layer of the circuit surface ink removal process will be left; the surface is plated according to the requirements and conforms to the integrated circuit package ((10)). 2::1=1: The non-line copper layer surface ink is chemically etched and decomposed. ...except that 'the towel leaves the non-line copper layer' and then remove the non-line copper layer completely by the solution principle, only the body circuit encapsulates the metal surface of the process; The exposed copper layer on the side is plated with a metal protective layer to avoid oxidation of the exposed steel line; ^Step 6. Clean the surface of the line · Clean the surface of the integrated circuit package. Therefore, since the step of the surface treatment of the circuit has been plated with the metal circuit package (the metal layer of the process), the south-low current effect can be avoided by avoiding the area of the wiring, and it is not necessary to package all the integrated circuits ([ (10)) The contact pads (PAD) of the line are connected in series to reduce the surface treatment (step 3). The design of the drawn wires and the space occupied by the printed circuit board are required to increase the wiring area of the printed circuit board. A method for manufacturing a circuit board for use in a sealed circuit of an integrated circuit is provided. Since the present invention is coated with a metal layer of a human body integrated circuit package (COB) process before the line is etched, the J core can be prevented from being accumulated during wiring. 8 1299897 violently produces two low current effects, and does not need to seal all integrated circuits ((3)b) • The contact pads (PAD) of the line are connected in series, improving the conventional line steel layer\plating thickness unevenness is easy and uneven There is a disadvantage that the area of the wiring is limited when the wafer is sealed, and the area of the wiring is limited. [Embodiment] Next, a preferred embodiment will be listed, together with the figure and the figure number, Further explanations of other purposes and performances will enable you to review: to have a more detailed understanding of the present invention, and to familiarize yourself with the implementation, the following is a discussion of the present invention. The preferred embodiments are not limited to the scope of the invention, and any form of alteration or genus protection of the invention is based on the spirit of the invention. Provide a method of inserting the virtual field. 电路 积 积 电路 电路 电路 电路 电路 电路 电路 电路 电路 电路 电路 电路 电路 电路 电路 电路 电路 电路 电路 电路 电路 电路 电路 电路 电路 电路 电路 电路 电路 电路 电路 电路 电路 电路 电路 电路 电路 电路 电路 电路 电路 电路 电路 电路 电路, to make it up, to Bebei: to make chemical through-hole eight s steel surface conduction on the copper circuit board; Step 2 (S2), the line system through the negative film and the light source to expose the original liquid ink or photosensitive ink, the layer is A, The ink is B), and then the line (as shown in the second figure, the copper surface of the line exposes the copper layer part = chemically removes the line surface ink, so that the ink is B', leaving the oil black, (such as As shown in the second two figure, the oil layer A) is removed. / After being removed by the ink β' The exposed bottom copper step 3 (S3), the wiring meter, the processing, and the remaining line surface ink 9 1299897 are removed, and the exposed (COB) process is coated with the integrated circuit package ink B according to the requirements. 'The place shovel ^ shown in the first three figures, the original oil C); where the product V: the integrated circuit circuit B) the metal layer of the process, in addition, the circuit package (C0B) process is based on the principle of electrolysis Finished. Surface Plating Element:: Process in the Surface Treatment Process
素或兩種元素以二、、銀、始、、錫或其他貴重金屬元 勢裎金屬 合成之合金元素所組成；其中符合COB :耸屬表面鍍層之貴重金屬元素係由姑、纪、姻、錄、 專：金屬固體元素所組成之群組。 #◊路表面處理之流程中，符合COB製程金屬表面 級增I貝重金屬元辛— .你丄 I之一種以上元素合成之合金元素所組 由金、銀、麵、鎳、錫或銘、把、銦、録、叙之群 方矢所組成，你1 4 ·》日 Λ •錫銦、錫銀、錫鉍、鎳銀、鎳金、鎳錫、 鉑鎳等金屬容液。 4 線路蝕刻··將非線路之銅層表面油墨運 子刀解原理，使之完全去除乾淨（如第二之四圖所示， 將原本@下之油墨B”去除），而留^下非線路銅I，再以化 Γ虫刻分解原理將非線路鋼層完么除m符合積體 路封裝⑽B)製程之金屬表面(如第二之五圖所示 之油墨B底下之非線路銅層A‘去除，使線路鋼層 A留下）。 鋼步驟5 (S5)、線路側面鋼面包覆：將線路側面露出之 ^ 乂化干/奋液直接鍍上金屬保護層，以避免露銅線路而 (如第一之六圖所不，將銅層.A，，之線路側面D包覆化 10 録、矣必 該線路 係由金 1299897 學溶液另外’該線路側面銅面包覆之流程中 面金屬保護層’係由金、銀、始、錄、锡、或 屬元素’或兩種元素以上合成之合金元素戶"且 :驟5之線路側面銅面包覆之流程中，該線路 4層之貝重金屬元素係由始、把、銦 體元素所組成。 又該線路側面銅面包覆之流程中 達層之二種元素以上合成之合金元素 錄、錫、或銘、把、銦、娣、銀之群族所組： 銦、錫銀、錫鉍、錄銀、鎳金、鎳錫、麵鎳筹 步驟6(S6)、線路表面清潔：清潔積 面。 藉由上述之步驟，如第二之七圖所示，可 封裝(COB)製程之金屬表面固設一半導體晶片1 電路封裝（COB)製程之金屬表面上拉導線f ,再 _封裝（COB)製程之金屬上進行模壓封膠製程◦。 由於本發明之步驟3線路表面處理之步驟 7體電路封裝（c〇B)製程之金屬層，可避免因佈 夕春而產生尚低電流效應，並防止發生積體電s 金屬鍍層厚度差異過大之現象。 、 卜本I明之步驟4的線路钮刻步驟， 先鍍上積體電路封裝（COB)之金屬表面，不需將 路封裝（COB)線路之接觸墊（pAD )串接導通， 電路封裝（COB)之金屬表面直接完成（c〇B)表面 ，該線路側 其他貴重金 成；其中該 側面金屬保 、專金屬固 側面金屬保 、銀、鉑、 ，例如：錫 金屬容液。 路封裝之表 於積體電路 ^ ’並於積體 於積體電路 已鍍上符合 線時之面積 各封裝（COB) 由於本發明 所有積體電 而能於積體 處理步驟不 1299897 需增加拉導線設計，亦可提高佈線面積。 又由於本發明之步驟4線路蝕刻步驟 分解原理將非線路銅層完全去除，並二：以…刻 裝卿製程之金屬表面，因此，積體電下:二積體電路封 貝版电路封裝（COB)之狳 路側面會露出銅&，而纟易造成銅氧化，俗稱銅綠，因此、， 必須於線路側面銅包覆。 由上所述，由於本發明線路表面處理之步驟已錢上符 肇合積體電路封裝（C0B)製程之金屬層，可避免佈線時之面積 多募而產生高低電流效應，且不需將所有積體電路封裝 (COB)線路之接觸墊（pAD)串接導通，而能於積體電路封 裂（COB)之金屬表面直接完成（c〇B)表面處理步驟，並避免 模壓封膠時產生溢膠之情形，可防止不良率之產品產生， 達到降低成本之目的。 歸納上述所說，本發明同時具有上述幕多效能與實用 饧值’並可有效提升整體的經濟效益，因此本發明確實為 鲁 創意極佳的發明，且在相同技術領域中未見相同或近似 之產品公開使用，應已符合發明專利之要件，乃依法提出 申請，並請賜予本發明專利。 【圖式簡單說明】 第一圖係本發明方法之流程圖。 第二之一圖係本發明利用油墨曝光之結構示意圖。 第二之二圖係本發明去除油墨為之結構示意圖。 第二之三圖係本發明鍍上符合積體電路封裝（C0B)製程之 金屬層C之結構示意圖。 12 1299897 第二之四圖係本發明去除後油墨之結構示意圖。 弟二之五圖去除非線路銅層之油墨結構示意圖。 第二之六圖係本發明銅層線路側面包覆化學溶液之結構示 意圖。 第二之七圖係本發明固設一半導體晶片、打線（Bonding) * 及模壓封膠製程之結構示意圖。 第三圖係傳統正片製程之流程圖。 第四圖係傳統負片製程之流程圖。 •【主要元件符號說明】 51 :化學貫孔 52 :線路製作 S 3 :線路表面處理 S 4 :線路蝕刻 S 5 :線路側面銅包覆 S 6 :線路表面清潔 A :銅層 φ B :油墨 B ‘ ：去除之油墨 B” ：留下之油墨 C:鍍上符合積體電路封裝（COB)製程之金屬層 A ‘ ：非線路銅層 A ” ：線路銅層 D :線路側面 E :半導體晶片 F ··打線（Β ο n d i n g ) 13 1299897 G :模壓封膠製程 X 1 :化 學 貫 孔 X 2 :線 路 製 作 X 3 :線 路 刻 X 4 :線 路 表 面 處理 Y 1 :化 學 貫 孔 Y 2 :線 路 製 作 Y 3 :線 路 保 護 Y 4 :線 路 蝕 刻 Y 5 :線 路 表 面 處理 14Or two elements consisting of two, silver, tin, tin or other precious metal elements of the alloying elements of the metal synthesis; which meets the COB: the precious metal elements of the surface coating are from Gu, Ji, and Record, special: group of metal solid elements. #◊路surface treatment process, in line with the COB process, the surface level of the metal is increased by I. The elemental alloy element is composed of gold, silver, noodles, nickel, tin or Ming. Indium, recorded, and the group of the group of the group, you 1 4 · "Sunday" • tin indium, tin silver, tin antimony, nickel silver, nickel gold, nickel tin, platinum nickel and other metal liquid. 4 Line etching · · The non-line copper layer surface ink carrier knife solution principle, so that it is completely removed (as shown in the second figure, remove the original @下墨B), and leave the next The copper I of the line, and then the non-line steel layer is finished by the decomposition principle of the mites, and the metal surface of the process is matched with the circuit of the integrated circuit package (10) B) (such as the non-line copper layer under the ink B shown in the fifth figure) A' is removed to leave the steel layer A.) Steel step 5 (S5), side steel surface cladding: directly expose the side of the line to the metal layer to avoid the exposed copper The line (as shown in the first six figure, the copper layer. A, the line side D of the line is covered with 10 records, the line must be the gold 1299897 solution solution and the side of the line side copper surface coating process The middle metal protective layer 'is an alloy element composed of gold, silver, beginning, recording, tin, or a genus element or two elements or more; and: in the process of copper surface coating on the side of the line 5, The shell metal element of the 4th layer of the line consists of the element of the beginning, the end, and the indium body. In the process, two elements of the layer are synthesized above, and the alloy elements are recorded, tin, or group of indium, tin, indium, antimony, and silver: indium, tin silver, tin antimony, silver, nickel, nickel tin Surface Nickel Step 6 (S6), Line Surface Cleaning: Clean the surface. With the above steps, as shown in the second figure, the metal surface of the packageable (COB) process is fixed with a semiconductor wafer 1 circuit package (COB) process metal surface pull-up wire f, re-package (COB) process metal on the mold sealing process ◦. Because of the step 3 of the invention line surface treatment step 7 body circuit package (c〇B) process The metal layer can avoid the low current effect caused by the Buxichun, and prevent the phenomenon that the thickness difference of the metal plating layer of the integrated electricity s is too large. The step of the step of the step 4 of the Buben I Ming is first plated with the integrated body. The metal surface of the circuit package (COB) does not need to be connected in series with the contact pad (pAD) of the circuit package (COB) line. The metal surface of the circuit package (COB) directly completes the surface (c〇B), which is other valuable on the line side. Jincheng; the side metal protection, special metal Side metal, silver, platinum, for example: tin metal liquid. The road package is shown in the integrated circuit ^ 'and the integrated circuit in the integrated circuit has been lined with the area of each package (COB) due to the invention All the integrated body can be processed in the integrated process is not 1299897. It is necessary to increase the design of the drawn wire and increase the wiring area. Moreover, the non-line copper layer is completely removed due to the decomposition principle of the step 4 etching step of the present invention, and two: to... Engraving the metal surface of the Qing process, therefore, under the integrated electricity: the side of the circuit of the two integrated circuit circuit pack (COB) will expose copper & It must be copper coated on the side of the line. As described above, since the step of the surface treatment of the circuit of the present invention has already been applied to the metal layer of the integrated circuit package (C0B) process, the area of the wiring can be prevented from being multi-raised, and high and low current effects are generated, and all the integrated bodies are not required. The contact pad (pAD) of the circuit package (COB) line is connected in series, and can directly complete the (c〇B) surface treatment step on the metal surface of the integrated circuit (COB), and avoid the overflow of the glue when the molding is sealed. In this case, the product of the non-performing rate can be prevented from being produced, and the purpose of reducing the cost can be achieved. In summary, the present invention has the above-mentioned multi-efficiency and practical depreciation, and can effectively improve the overall economic benefit, so the present invention is indeed an excellent invention of Lu, and the same or similar in the same technical field is not seen. The public use of the product shall meet the requirements of the invention patent, and the application shall be made according to law, and the patent of the invention shall be given. BRIEF DESCRIPTION OF THE DRAWINGS The first figure is a flow chart of the method of the present invention. The second diagram is a schematic diagram of the structure of the present invention using ink exposure. The second figure is a schematic diagram of the structure of the ink removal of the present invention. The second figure is a schematic view showing the structure of the metal layer C conforming to the integrated circuit package (C0B) process of the present invention. 12 1299897 The fourth figure is a schematic view of the structure of the ink after removal of the present invention. The second figure of the second is to remove the ink structure diagram of the non-line copper layer. The sixth figure is a schematic view of the structure of the side of the copper layer wiring of the present invention coated with a chemical solution. The second seventh diagram is a schematic structural view of the present invention for fixing a semiconductor wafer, bonding, and molding and sealing process. The third picture is a flow chart of the traditional positive film process. The fourth picture is a flow chart of the traditional negative film process. • [Main component symbol description] 51: Chemical via 52: Line fabrication S 3 : Line surface treatment S 4 : Line etching S 5 : Line side copper cladding S 6 : Line surface cleaning A : Copper layer φ B : Ink B ' :Removed Ink B" :Leaves Ink C: Plated with metal layer A ' in accordance with Integrated Circuit Package (COB) process: Non-line copper layer A ”: Line copper layer D: Line side E: Semiconductor wafer F ··Threading (Β ο nding ) 13 1299897 G : Molding and sealing process X 1 : Chemical through hole X 2 : Line making X 3 : Line engraving X 4 : Line surface treatment Y 1 : Chemical through hole Y 2 : Line making Y 3: line protection Y 4 : line etching Y 5 : line surface treatment 14