Γ352409 九、發明說明： 【發明所屬之技術領域】 幾何圖案之結構 本發明係有關於-種四方扁平無引腳之半導體封裝結構特別是 有關於-種在四方扁平無引腳之半導體封裝結構中的金屬基座上形成 【先前技術】 在現代的半導體職製程中，均是將一個已經完成前段製程(_ EndProcess)之晶圓（wafe〇先進行薄化處理（加肋__)，將 晶片的厚度研磨至2〜20 mil之間；然後，再塗佈（咖㈣）或網印 (printing)-層高分子（⑽卿）材料於晶⑽㈣此高分子材料 可以是-種樹脂(Epoxy);接著’將—個可以移除的膠帶㈣貼附 於半固化狀的高分子㈣上；_，進行晶K_(sawingp_s)， 使晶圓成為i顆的晶片（die);最後，就可將—顆顆的晶片與基板連 接。 在眾多的半導體«型態中，四方扁平無㈣（_舰 Non Lead，QFN)之封裳結構是將引腳峨於封裝體中，故鱼外部電 路板連接時’較錄貼於電路板上且可財較小騎合厚度，因此㈣ _裝結構符合當下對電子零組件需「輕、薄、短、小」的要求，特 別疋用在可攜型（p她ble _)之電子產品上，此種具有封「輕、 薄、短、小」的封裝結構可財效的節省空間。 首先，請參考第u圖，係一中典型的QFN封裝結構，此qfn 封裝結構是將“ n與導線架中的晶片承座15固接，而晶片承座15 的四週配置有複數細丨腳12，此複數個㈣腳12的高度高於晶片承 座15使得兩者間形成一高度差，並且複數個内引腳12藉由複數條金 屬導線13與晶片主動面上的複數個金屬接點連接。在此封裝結構中， 複數個内引腳12之前端度易峡’同時在進行金屬導線的打線製程 (wlrebonding)時’很容易被壓彎故降低了封裝結構的可靠度。 另外一種典型的_封裝結構，是由美國專利號第5942794所揭 I其主要是以導線架為主體，將導線架四端的支撑勒Μ向 上考曲’使其可以膽日片u，使得晶片u得以升高可以便於封裝 體Η密_ U及㈣腳12，但此封裝結構會增加封裝體之厚度， 且因其内引腳12係平貼於封裝_麵，耻f要較長的金屬導線η 來連接晶m細丨腳12，除了增加電子信峨的歸卜，還會使用 金屬導線13因跨弧太大變雜軟，故在進行注模（祕⑻時，可能 使得金屬魏13細峨__產_，__内的金 屬導線13短路’故同樣會降低封裝結構的可靠度。 而另外一種不制導線㈣_騎結構則已揭露於美國專矛 第6372539齡。此專齡要是綱基板上以掏（職她）试 製程來_ “承座__ 18，额軸―_ Μ _ 片11與金屬導線13。由於_封裝結構报多都使用在小型或可攜型 之電子產品，故電子產品所產生賴效齡影·品的絲，因此散 熱是很重㈣課題。此種QFN _裝結構可⑽善以導絲為主體的Γ 352409 IX. Description of the invention: [Technical field of the invention] Structure of the geometric pattern The present invention relates to a quad flat no-lead semiconductor package structure, particularly in a quad flat no-lead semiconductor package structure Formed on the metal pedestal [Prior Art] In the modern semiconductor manufacturing process, a wafer that has completed the front-end process (_EndProcess) (wafe 进行 first thinned (ribbed __), the wafer The thickness is ground to between 2 and 20 mils; then, the coating (Caf (4)) or the printing-layer polymer (10) is applied to the crystal (10) (4). The polymer material may be an Epoxy resin. Then, 'attach a removable tape (4) to the semi-cured polymer (4); _, carry out the crystal K_(sawingp_s), make the wafer a i-die; finally, - The individual wafers are connected to the substrate. Among the many semiconductor types, the square-shaped flat (4) (_Non Lead, QFN) is a pin-up structure that encloses the pins in the package, so the fish external circuit board is connected. When it is 'recorded on the board and can be The smaller the size of the ride, so (4) _ the structure is in line with the current requirements for "light, thin, short, small" electronic components, especially for the portable (p her ble _) electronic products, this The package structure with "light, thin, short, and small" can save space. First, please refer to the figure u, which is a typical QFN package structure. This qfn package structure will be "n and lead frame". The wafer holder 15 is fixed, and the wafer holder 15 is disposed with a plurality of fine legs 12, and the height of the plurality of (four) legs 12 is higher than the wafer holder 15 so that a height difference is formed between the two, and a plurality of The inner lead 12 is connected to a plurality of metal contacts on the active surface of the wafer by a plurality of metal wires 13. In the package structure, a plurality of inner leads 12 are at the front end of the easy-toothed chim (wlrebonding) is very easy to be bent, which reduces the reliability of the package structure. Another typical _ package structure is disclosed in U.S. Patent No. 5,942,794, which is mainly based on a lead frame, and the lead frame is four. The end of the support The film u can be raised, so that the package u can be raised to facilitate the package Η _ U and (4) the foot 12, but the package structure will increase the thickness of the package, and because the inner pin 12 is flat on the package _ surface , shame f to a longer metal wire η to connect the crystal m fine foot 12, in addition to increasing the electronic letter of the intent, but also use the metal wire 13 because the cross-arc is too large and soft, so the injection molding (secret (8), it may cause the short-circuit of the metal wire 13 in the metal ________, so it will also reduce the reliability of the package structure. The other type of non-wire (4) _ riding structure has been exposed in the United States Spear is 6372539 years old. This special age should be on the platform of the 掏 (professional) trial process _ "bearing __ 18, front axle _ _ _ _ film 11 and metal wire 13. Since most of the _ package structure reports are used in small or portable electronic products, the electronic products produce silk that is effective in age and shadow, so heat dissipation is a serious problem. This kind of QFN _ mounting structure can be (10) good with guide wire as the main body
QfN封裝結構之缺點，卻 面上，故其完全平貼於外部電路板上1 承座17剌腳群18在同—平 冤路板上，因此散熱性不佳。 【發明内容】 味露面_-種在晶月 之散熱吟啦嶋構 據此，本發明之一主要目的在提供 結構，以有效解決㈣封裝結構散熱性不佳的曰^放熱面積㈣封裝 法，主要目的錢供—射增加憾面積_封裝方 法以有政解決QFN封褒結構散熱性不佳的問題。 封裝方 構，提^種可增加散熱面積卿封裝結 塾氧化。’曰“之金屬焊塾，可防止被触刻後的金屬焊 構中本=财—主要目的在提供—種可增加散熱面積QFN的封裝姓 使用_細刪繼娜㈣社，故不需 使用曰曰片承座’故可減小QFN封裝結構的厚度。 紗ΓΐΓ目的，本發明首先提供一種^扁平無引腳之半導體封 、L^ ^ —魅動面上配置有碰個金屬接點以及在背關配置有 、、何圖案凹痕的晶片，然後以複數條金屬導線，用以將晶片上的 文個金屬接點與複數個金屬焊塾之第—面連接；最後，再以一個封膠 、i覆日日片、金屬導線及複數個金屬焊墊之第—面，並曝露晶片背面 之近似幾何圖案及複數個金屬焊墊之第二面。 本發明接著提供-種四方扁平無引腳之半導體封裝結構，包括—個 主動面上配置有複數個金屬接點的晶片；然後以複數條金屬導線，用以 1352409 將晶片上的複數個金屬接點與複數個金屬焊墊之第—面連接；然後，再 以一個封膠體’包覆晶片、金屬導線及複數個金屬焊墊之第一面，並曝 露晶片之背面及複數個金屬焊墊之第二面；最後，再以—個電鍍層，將 其固接於晶片背面及複數個金屬焊墊之第二面，其中晶片背面上的電鍍 層為近似幾何圖案。 本發明接著提供一種四方扁平無引腳之半導體封裝之方法，係提供 · 一金屬基板，其具有一第一面及相對於該第一面之一第二面；形成一圖 . 案（pattern)於金屬基板之第一面及第二面上，以定義出一金屬基座區 及複數個金屬焊墊；接著，蝕刻金屬基板，以形成金屬基座區及複數個 金屬焊墊；將一個主動面上配置複數個金屬接點之半導體晶片貼付於金痛| 屬基座區；形成複數條金屬導線，用以將晶片上的複數個金屬接點與複 數個金屬焊墊連接；然後，以注膜方式（molding)形成封膠體，以覆 * 蓋晶片、金屬導線、金屬基座之第一面及複數個金屬焊墊之第一面，並 曝露金屬基座之第二面及複數個金屬焊墊之第二面；接著，蝕刻曝露之 _ 金屬基座之第二面及複數個金屬焊塾之第二面，以使金屬基座被移除並 使複數個金屬焊塾隔開；再形成一個幾何圖案於封膠體之晶片之背面 上；最後，蝕刻封膠體並將幾何圖案形成於晶片之背面上。 【實施方式】 鲁 本發明在此麟觸純為-種QFN雜結構及对，以使qfn 封裝結構具有較佳的散熱效果。為了能徹底地瞭解本發明，將在下列 的描述中提出詳錢步驟及其域。顯舰，本發_施行並未限定 QFN封裝之結構及方式之技藝者所熟習的特殊細節。另一方面，眾所 周知的晶片形成方式以及晶片薄化等後段製程之詳細步驟並未描述於 細節中，崎免造成本發日科必要之限L，對於本發明的較佳 實施例，則會詳細描述如下，然而除了這些詳細描述之外本發明還The shortcomings of the QfN package structure are on the surface, so that it is completely flat on the external circuit board. 1 The socket 17 is on the same-flat board, so the heat dissipation is not good. SUMMARY OF THE INVENTION The appearance of one of the present invention is to provide a structure for effectively solving the problem of (4) heat dissipation area (four) packaging method in which the heat dissipation of the package structure is not good, The main purpose of the money supply - shooting increased regret area _ packaging method to solve the problem of poor heat dissipation of QFN sealing structure. The packaging structure can be improved to increase the heat dissipation area of the package. '曰' metal welding 塾, can prevent the metal welding structure after being inscribed, the main purpose is to provide a kind of package name that can increase the heat dissipation area QFN _ 细删继娜(四)社, therefore no need to use The cymbal bearing seat can reduce the thickness of the QFN package structure. For the purpose of the yarn defect, the present invention first provides a flat, leadless semiconductor package, and a metal contact on the sleek surface. A wafer having a pattern of pits and a pattern is disposed at the back, and then a plurality of metal wires are used to connect the metal contacts on the wafer to the first surface of the plurality of metal pads; finally, a seal is used The first surface of the metal, the metal wire and the plurality of metal pads are exposed, and the approximate geometric pattern on the back side of the wafer and the second side of the plurality of metal pads are exposed. The present invention further provides a kind of square flat no reference. The semiconductor package structure of the foot includes a wafer on which a plurality of metal contacts are disposed on the active surface; and then a plurality of metal wires are used for the 1352409 to connect the plurality of metal contacts on the wafer with the plurality of metal pads. Face connection; And covering the first side of the wafer, the metal wire and the plurality of metal pads with a sealant, and exposing the back side of the chip and the second side of the plurality of metal pads; finally, using a plating layer, The method is fixed on the back surface of the wafer and the second surface of the plurality of metal pads, wherein the plating layer on the back surface of the wafer is an approximate geometric pattern. The present invention further provides a method for quad flat no-lead semiconductor package, providing a metal a substrate having a first surface and a second surface opposite to the first surface; forming a pattern on the first side and the second side of the metal substrate to define a metal pedestal region And a plurality of metal pads; then, etching the metal substrate to form a metal pedestal region and a plurality of metal pads; and attaching a semiconductor wafer with a plurality of metal contacts on the active surface to the gold pain | Forming a plurality of metal wires for connecting a plurality of metal contacts on the wafer with a plurality of metal pads; and then forming a sealant by a filming method to cover the wafers, the metal wires, The first side of the pedestal and the first side of the plurality of metal pads, and exposing the second side of the metal pedestal and the second side of the plurality of metal pads; and then etching the second _ metal pedestal a second surface of the plurality of metal soldering holes to remove the metal base and to separate the plurality of metal soldering holes; forming a geometric pattern on the back surface of the sealing body of the sealing body; finally, etching the sealing body and The geometric pattern is formed on the back surface of the wafer. [Embodiment] The present invention is purely a QFN hybrid structure and pair, so that the qfn package structure has a better heat dissipation effect. In order to thoroughly understand the present invention. The detailed steps and their fields will be set forth in the following description. The display does not define the specific details familiar to those skilled in the art and construction of QFN packages. On the other hand, well known methods of wafer formation and The detailed steps of the wafer thinning process and the like are not described in the details. The preferred embodiment of the present invention will be described in detail below, but in addition to these detailed descriptions, The invention is also described
S 8 β、廣泛地贿在其他的實細巾且本剌的細*受蚊，其以 之後的專利範圍為準。 〆首先°月參考帛2Α圖至第21圖’其為本發明之-具體實施例之 詳，-田製k過程。請參考第Μ圖，係為一平整之金屬基板_，此金屬 土板100之材料可以是鋼、減兩者之合金。接著將—個適當的圖案 貼付於金屬基板100之上表面及下表面上（未顯示棚中），然後進行 個餘刻程序，絲被圖案祕的金屬基板1GG移除，也就是將定義 為金屬基舰102 _份，將其在金屬基板⑽之上表面及下表面上 均移除部份之金屬；在本實施例中，似—個近似半侧㈤Μ⑻ 之方式進行，將沒有被圖案遮蔽的金屬基座區1()2移除—部份，也就 是並未完全_穿透’形成兩端較厚而中央㈣之結構，其中兩端較 厚定義為複數個金屬焊無1G4,中央較祕収義為金屬基座區 102，如第2B圖所示。接著，可以選擇性地在金屬焊墊區ι〇4上先進 打一次的電鍍製程，將，金屬材料沉積於每一個金屬焊墊區丨〇4之上， 以形成-金屬層106,而此金屬層1〇6之金屬材料係自下列族群中選 出’包括金、銀、銅、錫、叙、|巴或其合金；在形成本金屬層1〇6後， 可以使得後續在進行金屬導線焊接時，較容易形成焊接點，如第2c圖 所示。再接著，將-個半導體晶片經由—黏著層（未顯示於圖中） 固接於金屬基板100之金屬基座區102上，此黏著層之目的在接合半 導體晶片200與金屬基座1〇2 ’因此，只要是具有此一功能之黏著材料， 均為本發明之貫施態樣，例如：膠膜（die attached )或是半固化取 (即B-Stage膠），如第2D圖所示。然後，進行一打線製程（“π bonding)，以複數條金屬導線108來將半導體晶片2〇〇上的複數個金屬 接點（未顯示於圖中）與金屬基板100之複數個金屬焊塾區1⑽電性 連接；如前所述，金屬導線108可直接焊接於複數個金屬焊墊區1〇4 上，也可以是焊接於金屬焊墊區104之金屬層1〇6上，如證门一 牙/is圖所示。 1352409 冉接者，隨即進行. ㈣ding)將-高分子材料;卿⑽）’以注模方式 片2〇〇、金屬導後H脂材料所形成之封膠層300來將晶 片200金屬導線108、金屬基座1〇2之第 之第一面覆蓋並固化成一體’如第2F圖所示。•塾1〇4 來=此ΪΓΓ ’她上敎過輯M半输3片的單元 娜=在揭示本發明之特徵，而實際之製造過程是將- 整月的金屬基板1〇〇以一圖索推仏紅 茶進仃银刻，來形成複數個金屬基座區102 金屬焊塾請’因此半導體晶請也是依序貼付於金屬焊 塾區104上，故在完成封膠製程後，是在整片的金屬基板刚上形成 複數個封雜300。因此，挪成_體—面憾是平整的金 屬層。 接著’將上述之整片完成娜製賴金屬基板丨⑻進行另—次的 钱刻程序’以將封膠體300的另一面的金屬層移除，由於先前的半蝕 刻製程已移除-部份的金屬*形成較薄的金屬基舰1()2與較厚的複 數個金屬焊墊區104,因此當封膠體3〇〇的另一面（第二面）的金屬層 進行侧後，自然會將較薄的金屬基座區1〇2的部份完純刻穿^ (etching through)，也就是將金屬基座區1〇2移除，而較厚的複數個金 屬焊墊區1〇4則會在封膠體3〇〇上保持部份的金屬，由於較薄的金屬# 基座區102已被移除，使得金屬基座區1〇2與複數個金屬焊墊區ι〇4 凡全分離，同時複數個金屬焊墊區1〇4之間也形成各自獨立的焊墊， 請參考第2G目。很明顯地，當第二次的侧完成後，金屬基座區ι〇2 已被移除，而複數個金屬焊墊區104之第二面也未被封膠體3〇〇所覆 蓋，也就是直接將晶片200的黏著層與複數個金屬焊墊區丨〇4之第二 面的金屬層裸露或曝露。接著將晶片200的背面201上的黏著層移除 (未顯示於圖中），將晶月200的背面201直接裸露。最後，再將—個 具有近似幾何圖案401的隔離層400貼付於曝露的晶片2〇〇的背面2〇1S 8 β, extensively bribe in other fine scarves and Benedictine's fine insects, which are subject to the subsequent patents. 〆 First, reference is made to Fig. 21 to Fig. 21, which is a detailed description of the specific embodiment of the present invention. Please refer to the figure for a flat metal substrate. The material of the metal earth plate 100 may be steel or alloy of the two. Then, an appropriate pattern is attached to the upper surface and the lower surface of the metal substrate 100 (not shown in the shed), and then a residual process is performed, and the wire is removed by the pattern metal substrate 1GG, which is defined as metal. The base ship 102 _ parts, which removes part of the metal on the upper surface and the lower surface of the metal substrate (10); in this embodiment, it is like an approximate half-side (5) Μ (8), which will not be shielded by the pattern. The metal pedestal area 1 () 2 is removed - part, that is, it is not completely _ penetrated to form a thicker and central (four) structure at both ends, wherein the thicker ends are defined as a plurality of metal welds without 1G4, the central comparison The secret is the metal base area 102, as shown in Figure 2B. Then, an electroplating process can be selectively performed on the metal pad region ι 4 to deposit a metal material on each of the metal pad regions 4 to form a metal layer 106, and the metal The metal material of layer 1〇6 is selected from the following groups: 'including gold, silver, copper, tin, ruthenium, yttrium or its alloy; after forming the metal layer 1〇6, it can be used for subsequent metal wire bonding It is easier to form a solder joint as shown in Figure 2c. Then, a semiconductor wafer is fixed to the metal pedestal region 102 of the metal substrate 100 via an adhesive layer (not shown) for bonding the semiconductor wafer 200 and the metal pedestal 1 〇 2 ' Therefore, as long as it is an adhesive material having this function, it is a consistent aspect of the present invention, for example, a die attached or a semi-cured (ie, B-Stage adhesive), as shown in FIG. 2D. . Then, a plurality of metal wires 108 are used to bond a plurality of metal contacts (not shown in the figure) on the semiconductor wafer 2 to the plurality of metal pads of the metal substrate 100. 1 (10) Electrical connection; as described above, the metal wire 108 may be directly soldered to the plurality of metal pad regions 1〇4, or may be soldered to the metal layer 1〇6 of the metal pad region 104, such as a gate Tooth / is shown in Fig. 1352409 冉 接 , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , The first surface of the wafer 200 metal wire 108 and the metal base 1〇2 is covered and solidified into one body as shown in FIG. 2F. • 塾1〇4 = ΪΓΓ 她 她 她 她 她 她 她 她 她 她 她The three-piece unit Na = reveals the features of the present invention, and the actual manufacturing process is to form a plurality of metal pedestal regions 102 by pushing the black metal into the enamel silver in a month. Metal soldering please 'Therefore, the semiconductor crystal is also attached to the metal soldering area 104 in sequence, so it is completed. After the glue process, a plurality of seals 300 are formed on the entire metal substrate. Therefore, the metal body layer is a flat metal layer. Then, the whole piece is finished with a metal substrate (8). Performing another cost-cutting procedure to remove the metal layer on the other side of the encapsulant 300, since the previous half-etch process has been removed - part of the metal* forms a thinner metal-based ship 1() 2 with Thicker plurality of metal pad regions 104, so when the metal layer of the other side (second side) of the sealant 3〇〇 is side, the portion of the thin metal base region 1〇2 is naturally finished. The etching through is to remove the metal pedestal area 1〇2, and the thicker plurality of metal pad areas 1〇4 will retain part of the metal on the sealing body 3〇〇. Since the thinner metal # pedestal area 102 has been removed, the metal pedestal area 1 〇 2 is completely separated from the plurality of metal pad areas ι 〇 4 , and a plurality of metal pad areas 1 〇 4 are also To form separate pads, please refer to item 2G. Obviously, when the second side is completed, the metal base area ι〇2 has been In addition, the second side of the plurality of metal pad regions 104 is not covered by the encapsulant 3〇〇, that is, the metal directly contacting the adhesive layer of the wafer 200 and the second surface of the plurality of metal pad regions 4 The layer is exposed or exposed. The adhesive layer on the back side 201 of the wafer 200 is then removed (not shown), and the back side 201 of the crystal moon 200 is directly exposed. Finally, an isolation layer having an approximate geometric pattern 401 is used. 400 attached to the back of the exposed wafer 2〇〇2〇1
S 10 1352409 上’如第2H圖所示。然後，再進行一次蝕刻製程，將近似幾何圖案 6〇〇侧於晶片2〇0的背面2〇1上，如第Ή圖所示。此近似幾何圖案 可以是平行絲、同d平行L職是其佩麻不規狀 圖案等。很明顯地，此被蝕刻後的凹痕圖案可以增加與空氣的接觸面 積，故當此職結構置於-可攜型之魏（NB)時，可藉此來增加卿 封裝結構讀熱©積’以有效麟卿封裝結構散雛不佳的問題。 此外，本實施例係將增加散熱面積的幾何圖案直接配置在晶片的背面 上，故不需使用晶片承座（即金屬基座區1〇2)，故可減小封裝結 構的厚度^ 在上述形成本發明之實施例的過程中，為了使第二次的蝕刻過程 能夠確實將金屬基座區102移除，同時將複數個金屬焊墊區1〇4之間 完全被银刻穿透，因此會多蝕刻一段時間，藉由過蚀刻（〇veretchi%) 來確保完全被蝕刻穿透。故為了能使複數個金屬烊墊區1〇4之間能保 持平整的共平面’故也可以選擇性地在進行一次電鍍的製程，以將一 金屬電鍍層500形成在複數個金屬焊墊區1〇4之第二面上，如第^圖 所示。如此，除了可以將蝕刻後的金屬焊墊區1〇4保持平整的共平面， 也能防止被钱刻後曝露的複數個金屬焊墊區104發生氧化的情形此 外，金屬電鍍層500也具有一定之厚度，故當此QFN封裴結構與外部 電路板接合時’可以使得晶片200的背面201不與外部電路板接觸°， 使得整個晶片2〇〇的背面201及其背面201上的近似幾何圖案6〇〇與 外部電路板有一間距，故可進一步的增加散熱的效果。當然，也可= 選擇在晶片200的背面201的近似幾何圖案600上，藉由此電鍍製程 也同時電鍍上一金屬電鍍層500，在此本發明並不加以限制。 第2J圖所示為一理想化之示意圖，在實施的製程中，因為選擇使 用溼蝕刻（wetetching)製程，因此在蝕刻後，會有非等向性的敍列所 形成之下切（under-cut)痕跡，如第2K圖所示。然而，因金屬基板 11 1352409 並非很厚，因此下切痕跡在巨觀之下並不明顯，特別是在幾何圖案的 蝕刻深度不是很大時，下切痕跡更不明顯。同時此下切痕跡為溼蝕刻 製程必然有的現象，而且也非本發明之特徵所在，故在此並未詳細說 明。 接下來，請參考第3圖，係本發明之另一具體實施例之示意圖。 本貫施例在將一金屬基板100的上表面及下表面進行不同圖案的蝕 刻，以定義出較薄的金屬基座區102與較厚的複數個金屬焊墊區1〇4 ; 以及可以選擇性地在金屬焊塾區104之第一面上先進行一次的電鑛製 程，將一金屬材料沉積於每一個金屬焊墊區104之第一面之上，以形 成-金屬層106,然後將-個半導體晶片勘經由—黏著層固接於金屬馨 基板100之金屬基座區102之第一面上，接著，⑽數條金屬導線1〇8 來將半導體晶片200上的複數個金屬接點與金屬基板1〇〇之複數個金 屬焊墊區104電性連接，以上過程均與第2圖相同。 再接著，沿著複數個金屬焊墊KH之侧邊以注模方式（m〇lding) 將一高分子材料或一樹脂材料所形成之封膠層3〇〇來將晶片2〇〇、金屬 導線108、金屬基座1〇2之第一面及複數個金屬焊塾1〇4之第一面覆蓋 並固化成-體’如第3A圖所示。接著’將上述之整片完成封膠製程的 孟屬基板1GG進行另-次的侧程序，將較薄的金屬基舰移除，鲁 而車乂厚的複數個金屬焊塾區1〇4則會在封膠體3〇〇上保持部份的金 屬’由於較薄的金屬基座區1〇2已被移除，使得金屬基座區1〇2斑複 數個金屬焊龍1()4完全分離，同時複數個金屬焊籠1()4之間秘 成各自獨立的焊墊，請參考第3B圖。很明顯地，當第二次祕刻完成 後’ ^屬基舰102被完全移除，而使晶片2〇〇的背面2〇1上的黏著 層曝露出來，同複數個金屬焊塾區1〇4之第二面⑴5及第三面⑴7 並未破封膠體所覆蓋’也就是複數個金屬焊墊區104之第二面105 及第三面107也是直接裸露或曝露出金屬層，並且金屬焊塾區ι〇4之S 10 1352409 is as shown in Figure 2H. Then, an etching process is performed again, and the approximate geometric pattern 6 is placed on the back surface 2〇1 of the wafer 2〇0 as shown in the second figure. This approximate geometric pattern can be a parallel wire, the same d parallel L is a non-regular pattern. Obviously, the etched dimple pattern can increase the contact area with air, so when the structure is placed in the portable type (NB), the reading package heat reading product can be increased. 'The problem of poor nesting in the effective Linqing package structure. In addition, in this embodiment, the geometric pattern of increasing the heat dissipation area is directly disposed on the back surface of the wafer, so that the wafer holder (ie, the metal base region 1〇2) is not required, so the thickness of the package structure can be reduced. In the process of forming an embodiment of the present invention, in order to enable the second etching process to surely remove the metal pedestal region 102, and at the same time, the plurality of metal pad regions 1 〇 4 are completely penetrated by silver, It will be etched for a while and ensured to be completely etched by over-etching (〇veretchi%). Therefore, in order to maintain a flat coplanarity between the plurality of metal pad regions 1 〇 4, it is also possible to selectively perform a plating process to form a metal plating layer 500 in a plurality of metal pad regions. On the second side of the 1〇4, as shown in the figure ^. In this way, in addition to maintaining the flat coplanarity of the etched metal pad region 1〇4, it is also possible to prevent oxidation of the plurality of metal pad regions 104 exposed by the money, and the metal plating layer 500 also has a certain degree. The thickness, so that when the QFN sealing structure is bonded to the external circuit board, the back surface 201 of the wafer 200 can be made not to be in contact with the external circuit board, so that the approximate geometric pattern on the back surface 201 of the entire wafer 2 and its back surface 201 6〇〇 has a distance from the external circuit board, so it can further increase the heat dissipation effect. Of course, it is also possible to select on the approximate geometric pattern 600 of the back surface 201 of the wafer 200, by which the metal plating layer 500 is simultaneously plated, and the invention is not limited thereto. Figure 2J shows an idealized schematic. In the implementation process, because the wet etching process is chosen, after etching, there will be an anisotropic sequence undercut (under-cut). ) traces, as shown in Figure 2K. However, since the metal substrate 11 1352409 is not very thick, the undercut trace is not noticeable under the macroscopic view, especially when the etching depth of the geometric pattern is not large, the undercut trace is less noticeable. At the same time, this undercut is a phenomenon that is inevitable in the wet etching process, and is not a feature of the present invention, and thus is not described in detail herein. Next, please refer to Fig. 3, which is a schematic view of another embodiment of the present invention. The present embodiment etches different patterns of the upper surface and the lower surface of a metal substrate 100 to define a thinner metal pedestal region 102 and a thicker plurality of metal pad regions 1 〇 4; Optionally performing an electric ore process on the first side of the metal pad region 104, depositing a metal material on the first side of each of the metal pad regions 104 to form a metal layer 106, and then a semiconductor wafer is bonded to the first side of the metal pedestal region 102 of the sinica substrate 100 via an adhesive layer, and then (10) a plurality of metal wires 1 〇 8 to bond a plurality of metal contacts on the semiconductor wafer 200 The plurality of metal pad regions 104 of the metal substrate 1 are electrically connected to each other, and the above processes are the same as those in FIG. 2 . Then, along the side of the plurality of metal pads KH, a polymer material or a sealing layer formed of a resin material is formed by injection molding to bond the wafer 2 and the metal wires. 108. The first side of the metal base 1〇2 and the first side of the plurality of metal solder joints 1〇4 cover and solidify into a body as shown in FIG. 3A. Then, 'the above-mentioned whole piece of the GUM substrate 1GG which completes the sealing process is subjected to another side procedure, and the thin metal base ship is removed, and the plurality of metal welding areas of the thick and thick steel are 1〇4. Will retain part of the metal on the sealant 3' because the thin metal base area 1〇2 has been removed, so that the metal base area 1〇2 spot multiple metal soldering dragon 1 () 4 completely separated At the same time, a plurality of metal welding cages 1 () 4 are secreted into separate pads, please refer to Figure 3B. Obviously, when the second secret is completed, the ^^ base ship 102 is completely removed, and the adhesive layer on the back side 2〇1 of the wafer 2〇〇 is exposed, and the same number of metal soldering areas are 1〇 The second side (1) 5 and the third side (1) 7 of 4 are not covered by the sealant', that is, the second side 105 and the third side 107 of the plurality of metal pad regions 104 are also directly exposed or exposed to the metal layer, and the metal welding 〇 area 之4
S 12 丄352409 第一面105及第三φ 107是連接在一起。接著將晶片2〇〇的背面加 上的黏著層移除（未顯示於圖中），以使晶片2〇〇的背面2〇1直接裸露。 然後，再將-個具有近似幾何圖案4〇1的隔離層4〇〇貼付於已曝露之 晶片200的背面20卜如第3C圖所示。然後，再進行—次钱刻製程， 將近似幾何圖案600蝕刻於晶片2〇〇的背面2〇1上，如第3〇圖所示。 此近似幾何圖案可以是平行直線、同心圓、平行之彎曲曲線或是其他 規則及不酬之圖輯。很鶴地，此祕職的凹痕難可以増加 與空氣的_面積，可藉縣增加QFN織賴之散熱面積，以^效 解決QFN封裝結構散熱性不佳的問題。 在上述形成本發明之實施例的過程中，為了使第二次的钱刻過程 能夠確實將金屬基座區102移除，同時將複數個金屬焊塾區1〇4之間 完全被触刻穿透，因此會多姓刻一段時間，藉由過蝴來確保完全被 蝕刻穿透。故為了能使複數個金屬焊塾區1〇4之間能保持平整的共平 面故也可以選擇性地在進行_次電鍍的製程，以將一金屬電鐘層⑽ 形成在複數個金鱗塾區104之第二面1〇5上，如第3E圖所示。如此， 除了可以·顺的金屬焊_ 1G4健平整的共平面，也能防止被 银刻後曝露的複數個金屬焊_ m發生氧化的情形；此外，金屬電 鑛層500也具有-定之厚度，故當此_封裝結構與外部電路板接合 時可以使得金屬基座區1〇2不與外部電路板接觸，使得整個金屬基 座區102及其上的近似幾何圖案_與外部電路板有一間距，故可進 -步的增加雜的效果當然’也可以選擇在金屬基舰脱的近似 幾何圖案600上，藉由此電鐘製程也電錢上—金屬電鍍層則，在此本 發明並不加以限制。 請繼續參考第4A圖及第4B圖，係本發明之另-具體實施例之簡 化之製程不意圖。本實施例係在完成前述之第Μ圖至第2G圖的步驟 後’並不再使用_製程來將近似幾何騎银刻在晶片綱的背面加 13 1352409 上，而是以一層具有近似幾何圖案4〇1及金屬焊墊層圖案4〇2之隔離 層400直接貼付在晶片2〇〇的背面2〇1與複數個金屬焊墊區ι〇4之曝 露面上’如第4A圖所示 '然後直接進行電鍍製程，將電鍍層5〇〇形成 於複數個金屬焊塾區104之上，並且在晶片2〇〇的背面2〇1上形成電 鐘之近似幾何圖案600，如第4B圖所示。此近似幾何圖案可以是平行 直線、同心圓、平行之f曲曲線或是其他規則及不規則之圖案等。很 明顯地，由電鍍餘卿成之凸起的幾制樣可以增加與空氣的 接觸面積，故可藉此來增加QFN封裝結構之散熱面積，以有效解決 QFN封裝結構散熱性不佳的問題。 同理’也可以將本實施例係在完成前述之第3B _步驟後，也是_ 直接以-層具有近似幾何圖案及金屬焊墊層圖案4Q2之隔離層· 直接貼付在晶片200的背面2()1與複數個金屬焊塾區1〇4之曝露面上； 然後直接進行電鑛製程，將電鍍層5⑻形成於複數個金屬焊塾區⑴4 並且在b曰片200的背面2〇1上形成電鑛之近似幾何圖案6⑻的 凹痕^如第5圖所示。此近似幾何圖案可以是平行直線、同心圓、平 行之f曲曲線或是其他規則及不規則之圖案等。很_地 程所形成之凸起_何„職可以增加與空氣的接觸面積，故可藉 此來i曰加QFN封裝結構之散熱面積，以有效解決qfn封裝結構散埶鲁 性不佳的問題。 * 八很明顯的，本發明的特徵相較於先前技術，係將先前技術中的寬 屬^微j、化’並且在微金屬微帶的位置作不同的配置。顯然地， 2上面實施例中的描述，本發明可能有許多的修正與差異。因此需 其附加的權利要求項之範圍内加以理解，除了上述詳細的描述 ㈣Ϊ發明還可以廣泛地在其他的實施例巾施行。上述僅為本發明之 例而已’並非用以限定本發明之中請專利範圍；凡其它未脫 發明所揭示之精神下所完成的等效改變或修飾，均應包含在下述S 12 丄 352409 The first side 105 and the third φ 107 are connected together. The adhesive layer on the back side of the wafer 2 is then removed (not shown) so that the back side 2〇1 of the wafer 2 is directly exposed. Then, a spacer layer 4 having an approximate geometric pattern 4?1 is attached to the back surface 20 of the exposed wafer 200 as shown in Fig. 3C. Then, the etching process is performed again, and the approximate geometric pattern 600 is etched on the back surface 2〇1 of the wafer 2〇〇 as shown in FIG. This approximate geometric pattern can be a parallel straight line, a concentric circle, a parallel curved curve, or a series of other rules and no pay. Very crane land, the dent of this secret job can be added to the air _ area, can increase the heat dissipation area of QFN woven by the county, to solve the problem of poor heat dissipation of QFN package structure. In the above-described process of forming an embodiment of the present invention, in order to enable the second engraving process to surely remove the metal pedestal region 102, at the same time, a plurality of metal ferrule regions 1 〇 4 are completely touched through. Throughout, so many people will be engraved for a while, by means of butterflies to ensure that they are completely etched through. Therefore, in order to maintain a flat coplanarity between the plurality of metal soldering regions 1 〇 4, it is also possible to selectively perform a plating process to form a metal electric clock layer (10) in a plurality of gold scales. The second side of the area 104 is 1 〇 5 as shown in Fig. 3E. In this way, in addition to the smoothing of the coplanar surface of the metal welding _ 1G4, it is also possible to prevent the oxidation of the plurality of metal welding _ m exposed by the silver etching; in addition, the metal electric ore layer 500 also has a certain thickness. Therefore, when the package structure is bonded to the external circuit board, the metal base region 1〇2 can be prevented from contacting the external circuit board, so that the entire metal base region 102 and the approximate geometric pattern thereon have a distance from the external circuit board. Therefore, it is possible to add a hybrid effect to the step-by-step. It can also be selected on the approximate geometric pattern 600 of the metal-based ship, whereby the electric clock process is also used for the metal-plated layer, and the present invention does not limit. Continuing to refer to Figures 4A and 4B, a simplified process of another embodiment of the present invention is not intended. In this embodiment, after the steps of the foregoing figures to 2G are completed, 'there is no longer used _ process to engrave the approximate geometry of the silver on the back side of the wafer, plus 13 1352409, but with an approximate geometric pattern of one layer. 4隔离1 and the metal pad pattern 4〇2 isolation layer 400 is directly attached to the back surface 2〇1 of the wafer 2〇〇 and the exposed surface of the plurality of metal pad regions ι〇4 as shown in FIG. 4A. Then, the electroplating process is directly performed, and the plating layer 5 is formed on the plurality of metal pad regions 104, and an approximate geometric pattern 600 of the electric clock is formed on the back surface 2〇1 of the wafer 2〇〇, as shown in FIG. 4B. Show. The approximate geometric pattern can be a parallel straight line, a concentric circle, a parallel f curve, or other regular and irregular patterns. Obviously, the number of protrusions formed by electroplating Yuqing can increase the contact area with air, so that the heat dissipation area of the QFN package structure can be increased to effectively solve the problem of poor heat dissipation of the QFN package structure. Similarly, the present embodiment can also be directly attached to the back surface 2 of the wafer 200 after the completion of the foregoing 3B_step, and also directly to the isolation layer having the approximate geometric pattern and the metal pad pattern 4Q2. 1) and a plurality of metal soldering areas on the exposed surface of 1〇4; then directly performing an electric ore process, forming a plating layer 5 (8) in a plurality of metal soldering regions (1) 4 and forming on the back surface 2〇1 of the b-plate 200 The indentation of the approximate geometric pattern 6 (8) of the electric ore ^ is shown in Fig. 5. The approximate geometric pattern can be a parallel straight line, a concentric circle, a parallel f curve, or other regular and irregular patterns. The bulge formed by the _ ground process can increase the contact area with the air, so it can be used to increase the heat dissipation area of the QFN package structure to effectively solve the problem of poor dispersion of the qfn package structure. * It is obvious that the features of the present invention are different from the prior art in that the width of the prior art is different, and the position of the micro-metal microstrip is differently configured. Obviously, the above is implemented. The invention may be modified and varied in many ways, and it is intended to be understood within the scope of the appended claims. In addition to the above detailed description (4), the invention may be widely practiced in other embodiments. The present invention is not intended to limit the scope of the invention, and any equivalent changes or modifications made in the spirit of the invention will be included in the following.
S 14 1352409 申請專利範圍内。 【圖式簡單說明】 第1A〜職係先前技術之QFN封楚結構之示意圖； 第2A〜2K_本發明之_封裝結構讀造触示意圖； 第 3A〜_綱㈣; QFN封敦結構之製造過程示意圖;S 14 1352409 is within the scope of the patent application. [Simplified Schematic] FIG. 1A is a schematic diagram of the structure of the QFN seal of the prior art; 2A~2K_ The schematic diagram of the package structure of the present invention; 3A~_class (4); Manufacturing of the QFN seal structure Process schematic
第5圖係本發明之另-QFN封裝結構之製造過程示意圖 【主要元件符號說明】 1〇 QFN封裝結構（先前技術） 11 晶片 12 内引腳 13 金屬導線 !4 封膠體Fig. 5 is a schematic view showing the manufacturing process of the other-QFN package structure of the present invention. [Main component symbol description] 1〇 QFN package structure (prior art) 11 Wafer 12 Inner pin 13 Metal wire !4 Sealant
第4A〜4B圖係本發明之再一 以及 15 晶片承座 16 凸起之承座 17 金屬基座 18 焊塾· 100 金屬基板 102 金屬基座區 104 焊墊區 105 焊墊區之第二面 !〇6 金屬層 15 1352409 107 焊墊區之第三面 108 金屬導線 200 晶片 201 晶片背面 300 封膠體 400 隔離層 401 幾何圖案 402 金屬焊墊層圖案 500 電鍍層 600 凹痕之幾何圖案4A to 4B are still another embodiment of the present invention and 15 wafer holder 16 raised seat 17 metal base 18 solder 塾 100 metal substrate 102 metal pedestal area 104 pad area 105 second side of the pad area !〇6 Metal Layer 15 1352409 107 Third Side of Pad Area 108 Metal Wire 200 Wafer 201 Wafer Back 300 Sealant 400 Isolation Layer 401 Geometry Pattern 402 Metal Pad Pattern 500 Plating Layer 600 Geometric Pattern of Dent