1297940 16260twf.d〇c/r 九、發明說明： 【發明所、屬之技術領域】 3右^^明疋有關於一種線路基板及其製作方法，且特別 =二―種藉由圖案化複合導電層外側之金屬層，以形 「土土土板中之線路層的線路基板及其製作方法。 L无W技術】 近年來，隨著電子技術的曰新月異，高科技電子產業 的相繼問世，播提审 便侍更人性化、功能更佳的電子產品不斷地 出^ 1並朝向輕、薄、短、小的趨勢設計。目前在半 ^ =衣衣私中，線路基板（circuitsubstrate)是經常使用 的構衣元件之一，其主要包括壓合法（lamination)及增層 法（buildup)二大類型之基板。其中，線路基板主要由多 層圖案化線路層（Patterned circuit layer)及多層圖案化介 電層（patterned dielectric layer)交替疊合而成，由於線路 基板具有佈線細密、組裝緊湊及性能良好等優點，使得線 路基板已經成為晶片尺寸封裝（Chip Scale Package，CSP) 與覆晶封裝（flip chip package)之主流。 又而a，線路基板之圖案化線路層例如由銅箱層 (copper foil iayer)經過微影蝕刻所定義而成，而介電層 係配置於兩相鄰之圖案化線路層之間，用以隔離兩相鄰之 圖案化線路層。其中，不同的圖案化線路層之間係可透過 一導電通孔（Plating Through Hole，PTH)或一導電孔 (conductive via)，而彼此電性連接。圖案化介電層之材 質可為玻璃環氧基樹脂（FR-4、FR-5)、雙順丁婦二酸酿 1297940 16260twf.doc/r 亞胺（Bismaleimide-Triazine，BT) ^ ， ㈣）等…卜，線路基減包含 ’此焊罩祕⑽最外層的_倾^;之r r 暴=部分的圖案化線路層，以作為線 凡件電性連接的媒介。 汉/、/、他罨千 圖1繪示為習知之一種線路基板-立 照圖卜以四層線路層之基板為例，習 120.13〇. 140 电層150、160、170相互堆疊而成，每— :m是位於兩相鄰之圖案化線路層ιι〇曰、 二：:=广計上，最内層的圖案化線路層 疋作為線路基板100之電源平面卩 ，平以 ;:二端f接地端。此外，最外層的圖案化線路層二 爾號導線，當 ^目=面與接地平面之一導電通孔180，來達到訊號傳遞 在習知技術中’雖然線路基板100具有四層圖案化線 層。、m、Μ0 ’但僅有最外層之二圖案化線路 _ 可作為訊號傳輸之佈設（layout)空間，而内 :之一圖案化線路層12〇、no的大部分面積則作 線面ί佈設空間。亦即’當線路基板100之 層的層數為四層、六層或八層以上時，但實際上作為 1297940 16260twf.doc/r 訊號傳輸之層數則相對少於或等於二 餘層數則提供訊號傳輪之參考電虔戶^二層或六層，其 對地此:會使縣路基二==薄無法減少，相 由於銥路基板中用以電性 ”複’^於基板上形 二^，再經過鑽孔、電I.等處=層(: 孔之製作，如此一來，不僅合拎 I此π成V電通 通孔所需的時間，也合提古二 2 、、’基板上之導電 【發明内容】 正们線路基板的製作成本。 其4 t明的目的就是在提供—種線路基板，藉由將後路 =兩側之表層線路嵌入於介電層中，以降低= 方法H的目的就是在提供—猶路基板的製作 作成本Γ有奴為間化之製程，並有助於降低線路基板之製 、+，==明的再—目的是提供一種線路基板的製作方 .，、此製作方法製作而成之線路基板具有較為平整的 义面、’以防止後續形成之抗氧化層及焊罩層的剝離。 為達^述或其他目的，本發明提出一種線路基板，其 宜合層、一第一表層線路層、一第二表層線路層 以夕數個導電塊。其中，疊合層具有相對應之一第一表 面以及一裳-主 w、一、—人币一表面，且疊合層中包括多數個介電層以及至 、 '复B線路層。此複合線路層是配置於上述介電層之1297940 16260twf.d〇c/r IX. Description of the invention: [Inventions, genus of the technical field] 3 Right ^^ Ming 疋 has a circuit substrate and its manufacturing method, and in particular = two kinds of patterned composite conductive The metal layer on the outer side of the layer is shaped as the circuit board of the circuit layer in the earth-soil board and its manufacturing method. L-free W technology In recent years, with the rapid development of electronic technology, the high-tech electronics industry has been successively launched. The electronic product with better humanity and better function is continuously designed and oriented towards light, thin, short and small trends. Currently, in the half-clothing, the circuit substrate is often One of the constituent components used mainly includes two types of substrates, lamination and buildup, wherein the circuit substrate is mainly composed of a plurality of patterned circuit layers and a plurality of patterned patterns. The patterned dielectric layers are alternately stacked. Due to the advantages of fine wiring, compact assembly, and good performance of the circuit substrate, the circuit substrate has become a chip size package (Chip). Scale Package, CSP) and the flip chip package. Moreover, a, the patterned circuit layer of the circuit substrate is defined by, for example, a copper foil layer (copper foil iayer), and dielectric The layer is disposed between two adjacent patterned circuit layers for isolating two adjacent patterned circuit layers, wherein different patterned circuit layers are permeable to a through hole (Plating Through Hole, PTH) Or a conductive via, electrically connected to each other. The material of the patterned dielectric layer can be glass epoxy resin (FR-4, FR-5), dicisbutanol acid 1297940 16260twf. Doc/r imine (Bismaleimide-Triazine, BT) ^, (4)), etc., the line base subtraction contains the 'outer layer of the solder mask (10) _ 倾 ^; rr violent = part of the patterned circuit layer, as The medium of the electrical connection of the wire is one of the circuit boards of the Chinese/, /, and it is shown in Figure 1. The substrate of the four-layer circuit layer is taken as an example. The 120.13〇. 140 electrical layer 150 , 160, 170 are stacked on each other, each - : m is located in two adjacent patterned circuit layers ιι曰, 2::= In the broadest sense, the innermost patterned circuit layer 疋 is used as the power plane of the circuit substrate 100, flat;; the two-terminal f ground terminal. In addition, the outermost patterned circuit layer Er Er wire, When one of the faces = the ground plane, one of the conductive vias 180 is used to achieve signal transmission in the prior art 'although the circuit substrate 100 has four patterned line layers. , m, Μ 0 'but only the outermost two patterned lines _ can be used as the layout space for signal transmission, and the inner: one of the patterned circuit layers 12 〇, no part of the area is made for line ί space. That is, when the number of layers of the circuit substrate 100 is four, six or eight layers, the number of layers transmitted as the 1297940 16260 twf.doc/r signal is relatively less than or equal to two layers. Provide reference to the signal transmission wheel to the second or sixth floor, which is grounded to the ground: the county road base 2 == thin can not be reduced, because the circuit board is used to electrically "re-form" on the substrate 2^, then through the hole, electric I. etc. = layer (: the production of the hole, so that not only the time required for the π into the V through hole, also mention the ancient two 2,, ' Conduction on the substrate [Summary of the invention] The manufacturing cost of the circuit substrate is the same. The purpose of the 4 t is to provide a circuit substrate by embedding the back surface = surface lines on both sides in the dielectric layer to reduce = The purpose of Method H is to provide a process for the production of the substrate, and to reduce the manufacturing process of the circuit substrate, and to improve the circuit substrate. The production side, the circuit board made by the production method has a relatively flat surface, 'preventing Stripping of the subsequently formed oxidation resistant layer and the solder mask layer. For the purpose of other or other purposes, the present invention provides a circuit substrate having a suitable layer, a first surface layer, and a second surface layer. a conductive block, wherein the laminated layer has a corresponding one of the first surface and a skirt-main w, a - a coin-surface, and the laminated layer includes a plurality of dielectric layers and a 'complex B circuit layer The composite circuit layer is disposed on the dielectric layer
lzy/^4U 16260twf.d〇c/r J 共包括兩圖案化綠政展；^ 之間的一中間金屬層。、、第一^配置於該些圖案化線路層 面。第二表層線路^配置於'層線路層是配置於第-表 在本發明之一較佳實施例中 ：!罩層，此第1罩層是配置^線，板更包括一第一 路，至少部分的第—表層線 路層上，並暴 一弟-抗氧化層，配置於第—此外，線路基板更包括 -表:線路層上。而第一抗氧以之至少部分第 在本發明之一較佳實 q匕括鎳/金層。 焊罩層，此第二焊罩声： 三線路基板更包括一第二 露出至少部分的第二^線路:第二表層線路層上，並暴 -第二抗氧化層，配置ς第二外’線路基板更包括 在本發明:亡二化層包括-鎳/金層。 其中第一複合導電声包括一由鮝供一弟一锼合導電層， 屬層兩側之兩外層:屬層。接:金置於中間金 後’於第-複合導電層二 1297940 16260twf.doc/r 介電層暴露出第-圖案化線路層，以形成—上層疊合基 板。接下來，提供一第二複合導電層，其中第二複合導電 層包括一中間金屬層以及配置於中間金屬層兩側之兩外層 至屬層。再來，圖案化第二複合導電層一外側之外層金屬 層，以形成一第二圖案化線路層。之後，於第二複合導電 層之外側形成-第二介電層，且第二介電層暴露出第二圖 案化線路層，以形成—下層疊合基板。接下來，提供一核 〜基板，其中核心基板包括一核心介電層以及配置於核心 介電f _多數_心導魏。最後，基板配置於 上層j合基板與下層疊合基板之間，並使第一圖案化線路 層與第二圖案化線路層朝向核心基板，而壓合上層疊合基 板、核心基板與下層疊合基板，以藉由核心導電塊導通第 一圖案化線路層與第二圖案化線路層。 在本發明之一較佳實施例中，其中第一複合導電層之 中間金屬層的材質包括鎳，而第—複合導電層之外層金屬 層的材質包括銅。同樣地，第二複合導電層之中間二屬層 的材質包括鎳，而第二複合導電層之外層金屬 & 括銅。 刊貝匕 在本發明之一較佳實施例中，其中於壓合上層最人美 板、核心基板與下層疊合基板之後，線路基板的製作;ς 更包括下列步驟··首移除第一複合導電層另—側之夕 層金屬層與中間金屬層，以暴露出第1案化線路層盘第 一介電層’並轉除第二複合導電層另—側之外層金屬声 與中間金屬層’以暴露出第二圖案化線路層與第二介^ 1297940 16260twf.doc/r 層。之後，在第一介電層與第— 一谭罩層，並且在第二介電層^案^線路層上形成-第 -第二焊罩層，其中第一焊罩；：一圖案化線路層上形成 線路層。最後少部分的第二圖案化 案化線路層上形成—第—抗氧化層分的第-圖 :露之至少部分的第二圖案化線路層上形成二 在本發明之一較佳實施例中， 與第二抗氧化層的方法包括分別在第抗氧化層 少部分的第一圖案化線路層以及第所暴露之至 部分的第二«化魏層上魏層所暴露之至少 板in明之—較佳實施例中，其中在塵合上居晶人其 板、核心基板與下層疊合基板之後 合基 更包括下列步驟：首先，移除第1合13,作方法 層金屬層，並轉除第二複合導電層另之外 ΐ二;後，在第一複合導電層之中間金屬層以及 W層之中間金屬層上分別形成圖案化 &後合 =fc=抗氧化層。之後，以第-抗氧化；層ί 减層為罩幕，圖案化第一複合導電層之中 抗 -複合導電層之中間金屬層。最後，在第—介電^第 圖案化線路層上形成―第一焊罩層，並且 ^第- 第二圖案化線路層上形成一第二焊罩層，t電層與 是覆蓋第一圖案化線路層，並暴露出第-抗氧化^罩層 層Lzy/^4U 16260twf.d〇c/r J A total of two patterned green metal exhibitions; an intermediate metal layer between ^. The first ^ is disposed on the patterned circuit layers. The second surface layer is disposed in the 'layer circuit layer is disposed in the first table. In a preferred embodiment of the present invention: the cover layer, the first cover layer is a configuration line, and the board further includes a first road. At least part of the first-surface circuit layer, and a violent-anti-oxidation layer, is disposed in the first--in addition, the circuit substrate further includes a watch: a circuit layer. The first antioxidant is, at least in part, preferred in the present invention to include a nickel/gold layer. The solder mask layer, the second solder mask sound: the three-circuit substrate further comprises a second exposed at least part of the second circuit: the second surface layer of the circuit layer, and the second-anti-oxidation layer is disposed on the second outer layer The circuit substrate is further included in the present invention: the deuterated layer includes a nickel/gold layer. The first composite conductive sound comprises a conductive layer provided by a pair of scorpions, and two outer layers on both sides of the genus layer: a genus layer. After the gold is placed in the intermediate gold, the first patterned conductive layer is exposed on the first composite conductive layer 212997940 16260twf.doc/r dielectric layer to form an upper laminated substrate. Next, a second composite conductive layer is provided, wherein the second composite conductive layer comprises an intermediate metal layer and two outer layer to genus layers disposed on both sides of the intermediate metal layer. Further, the second composite conductive layer is patterned with an outer outer metal layer to form a second patterned wiring layer. Thereafter, a second dielectric layer is formed on the outer side of the second composite conductive layer, and the second dielectric layer exposes the second patterned wiring layer to form a lower laminated substrate. Next, a core-substrate is provided, wherein the core substrate comprises a core dielectric layer and is disposed on the core dielectric f_majority_core. Finally, the substrate is disposed between the upper j-substrate and the lower laminated substrate, and the first patterned circuit layer and the second patterned circuit layer are oriented toward the core substrate, and the laminated substrate, the core substrate, and the lower layer are laminated. The substrate is configured to conduct the first patterned circuit layer and the second patterned circuit layer by the core conductive block. In a preferred embodiment of the invention, the material of the intermediate metal layer of the first composite conductive layer comprises nickel, and the material of the outer metal layer of the first composite conductive layer comprises copper. Similarly, the material of the middle two-layer layer of the second composite conductive layer includes nickel, and the outer metal of the second composite conductive layer & In a preferred embodiment of the present invention, after the uppermost slab, the core substrate and the lower laminated substrate are laminated, the circuit substrate is fabricated; ς further includes the following steps: The composite conductive layer is further disposed on the side of the metal layer and the intermediate metal layer to expose the first dielectric layer of the first patterned circuit layer and removes the metal acoustic and intermediate metal of the second composite conductive layer Layer 'to expose the second patterned circuit layer and the second dielectric layer 1297940 16260 twf.doc/r. Thereafter, a first-second solder mask layer is formed on the first dielectric layer and the first dielectric layer, and on the second dielectric layer, wherein the first solder mask; a patterned circuit A circuit layer is formed on the layer. Finally, a second portion of the second patterned circuit layer is formed on the first layer of the first anti-oxidation layer, and at least a portion of the second patterned circuit layer is formed on the second patterned substrate layer. In a preferred embodiment of the present invention And the method of the second anti-oxidation layer comprises: respectively, a first portion of the first patterned circuit layer of the first oxidation resistant layer and at least a portion of the second exposed layer of the Wei layer exposed to the second layer of the Wei layer - In a preferred embodiment, wherein the substrate is bonded to the substrate, the core substrate and the lower laminated substrate after dusting, the base further comprises the following steps: first, removing the first layer 13 as a method layer metal layer and removing the substrate The second composite conductive layer is further formed; afterwards, a patterning & ==cc=antioxidation layer is formed on the intermediate metal layer of the first composite conductive layer and the intermediate metal layer of the W layer, respectively. Thereafter, the intermediate metal layer of the anti-composite conductive layer in the first composite conductive layer is patterned by using the first anti-oxidation layer layer as a mask. Finally, a first solder mask layer is formed on the first dielectric layer, and a second solder mask layer is formed on the second and second patterned circuit layers, and the t-layer and the first pattern are covered. The circuit layer and expose the first anti-oxidation layer
1297940 16260twf.doc/r -焊罩層是覆蓋第二圖 在本發明之一較佳實施例中，其中形成第一抗h 與弟^一抗乳化層的方法包括分別在第一禮合導電展_ 層 金屬層以及第二複合導電層之中間金屬層上電二中間 化之一金層或鎳/金層。 又^成圖案 在本發明之一較佳實施例中，其中在壓合上層最八 板、介層基板與下層疊合基板之前，更包括；列士$5基 提供一第三複合導電層，其中第三複合導電層包一中(a) 金屬層以及配置於中間金屬層兩側之兩外層"金屬層 案化第三複合導電層一外侧之外層金屬層，以形成一第， 圖案化線路層（c)於第三複合導電層之外側形成一第 電層，且第三介電層暴露出第三圖案化線路層，以形^二 中間叠合基板⑷將第三圖案化線路層朝向核心基板;^而壓 合中間疊合基板於核心基板之其中一側上(e)圖案化第三 複合導電層另-側之外層金屬層，以形成—第四圖案化^ ，層⑴於第三複合導電層之另一側形成一第四介電層，1 第四介電層是暴露出第四圖案化線路層（g)提供一層間基 ，於中間疊合基板與上層疊合基板或巾間疊合基板與下層 疊合基板之間，並且在屢合上層疊合基板、核^基板與; 層疊合基板時，—併壓合中間疊合基板與層間基板，其中 層間基板包括一層間介電層以及配置於層間介電層内的多 ，個層間導電塊。當欲製作出具有更多線路狀線路基板 打可重複執行上述步驟(甸至(g)至少一次，即可使線路基 1297940 16260twf.doc/r 板中具有更多的線路層。 絲上所述，本發明之線路基板是利用由三 合而成的導電塊取代傳統中空的導電; 小線路二尺寸的限制’因此’將有助於縮 衣而言，本發明之線路基板的製 率將有助於降低線路基板一 ^ Μ八t匕外’本發明之線路基板主要是將複合導電層中的外 =屬層進行圖案化製程，以形成圖案化：=卜 再將介電材料填入於圖案化線路層中，以形二1 板。藉由多個疊合基板、核心基板盥 " =有上rr之線路基板，^ ==成的線路基板具有較佳之平整度，如此 層由線路===;形 :=路!其位於線路基板表*之-侧 值。口匕’ *電流流經表層線路時’將有助於降低其阻抗 易懂為讓下ttl之上靜其他目的、特徵和優點能更明顯 明^下了謂舉齡實補，並配合所關心作詳細說 12 1297940 16260twf.doc/r 【實施方式】 圖2繪不為本發明之線路基板的結構剖面圖。請炎考 圖2所示，此線路基板200係屬於具有雙層線路層之基板， 其主要包括疊合層210、第一表層線路層220、第二表層線 路層230以及多個導電塊240。以下，將搭配圖示詳細說 明線路基板200中之元件及其相對應之關係。1297940 16260twf.doc/r - The solder mask layer is covered by the second figure. In a preferred embodiment of the present invention, the method of forming the first anti-h and the anti-emulsification layer includes the first conductive conductive exhibition respectively. The layer metal layer and the intermediate metal layer of the second composite conductive layer are electrically charged to form a gold layer or a nickel/gold layer. In a preferred embodiment of the present invention, wherein the uppermost layer, the interlayer substrate and the lower laminated substrate are laminated, the first layer of the upper layer of the upper layer and the lower layer of the substrate are further provided; The third composite conductive layer comprises a (a) metal layer and two outer layers disposed on both sides of the intermediate metal layer, a metal layer, a third composite conductive layer, and an outer outer metal layer to form a first patterned circuit. The layer (c) forms an electric layer on the outer side of the third composite conductive layer, and the third dielectric layer exposes the third patterned circuit layer, and the third patterned circuit layer is oriented toward the intermediate laminated substrate (4) a core substrate; and pressing the intermediate laminated substrate on one side of the core substrate (e) patterning the other composite metal layer of the third composite conductive layer to form a fourth patterning layer, the layer (1) The other side of the three composite conductive layer forms a fourth dielectric layer, and the fourth dielectric layer exposes the fourth patterned circuit layer (g) to provide a layer of interlayer, and the intermediate laminated substrate and the upper laminated substrate or Between the stacked substrate and the lower laminated substrate, and in the overlap Laminating the substrate, the core substrate, and the laminated substrate, and pressing the intermediate laminated substrate and the interlayer substrate, wherein the interlayer substrate comprises an interlayer dielectric layer and a plurality of interlayer conductive blocks disposed in the interlayer dielectric layer . When you want to make a circuit with more line-like circuit, you can repeat the above steps (Dian to (g) at least once to make the circuit base 1297940 16260twf.doc/r board have more circuit layers. The circuit substrate of the present invention replaces the conventional hollow conductive with a conductive block formed by triple bonding; the limitation of the small size of the two wires 'so that' will contribute to the shrinking, and the manufacturing rate of the circuit substrate of the present invention will have Helping to reduce the circuit substrate. The circuit substrate of the present invention mainly performs patterning process on the outer layer of the composite conductive layer to form a pattern: then the dielectric material is filled in In the patterned circuit layer, the two boards are formed by a plurality of laminated substrates and a core substrate, and the circuit substrate having the upper rr has a better flatness, and the layer is formed by the line. ===; Shape: = Road! It is located in the line substrate table * side value. Port 匕 ' * current flowing through the surface line 'will help to reduce its impedance is easy to understand to let ttl above other purposes, The features and advantages can be more clearly understood. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 2 is a cross-sectional view showing the structure of a circuit board which is not the present invention. As shown in FIG. 2, the circuit board 200 is a circuit board having a double layer. The substrate mainly includes a laminated layer 210, a first surface layer circuit layer 220, a second surface layer circuit layer 230, and a plurality of conductive blocks 240. Hereinafter, components in the circuit substrate 200 and their corresponding relationships will be described in detail with reference to the drawings. .
豐合層210具有相對應的第一表面si及第二表面 S2,且其包括多個介電層212以及至少一複合線路層214。 此複合線路層214是配置於介電層212之間。複合線路層 214包括二圖案化線路層214a、214b及配置於圖案化線^ 層214a、214b之間的中間金屬層214c。在本發明之一實 施例中，圖案化線路層214a、214b可例如是由銅金屬所二 成’而夾置於二者間的中間金屬層2丨4 c可例如係由鎳金屬 所構成。此第一表層線路層220是配置於疊合層210之第 :表面s卜且核人於第—表面S1内，使第_表層線路 層220之+外側表面與疊合層21〇之第一表面§ι共平面。 同樣地，第=表層線路層230是配置於疊合層210之第二 f 且疋队入於第二表面内，使第二表層線路声 面是與叠合層21〇之第二表面S2共平面路【 Ϊ 20::線Ϊ層220與第二表層線路層230是作為線路基 路層230之材料弟—表層、線路層22G與第二表層線 層犯内，用以3制。此外，導電塊240是配置於介電 與第二表層線路合線路層214、第一表層線路層220 曰230。如此一來，第一表層線路層22〇 13 1297940 16260twf.doc/r 即可透過導電塊24〇及複合線路層叫 層230電性連接。 中 田人更，^而电塊24。係由三層實心的金屬材料 ^而成’因此’將有助於提高整個線路基板之可靠 =吏】者可依據不同的使用需求，於線路基板200中 之=田*配置所需的導電塊，本發明對於導電塊· 之數目、形狀及其材質不作任何的限制。 =繼續參考圖2所示，本發明可進—步地於第一表声 2路層220及弟二表層線路層23()上分別配置 層（solder mask)250及一筮- p干罩 僅暴露出部份的第—表層 層260亦僅暴蕗出部份的第二 早 路基板200與其他電子元丰曰^ " 30，以作為線 接的媒介。 牛如曰曰片、被動元件之間電性連 氧化二。選擇性_ 是配置於第-焊罩層25f抗氧化層270 上，而此第二抗氧化層斤，的广表層線路層220之 暴露的第二表層線路層23(^配==焊=260所 220及第二表層線路居=以防止弟—表層線路層 形。在此實施财，第L产接_ L產生氧化的情 例如是由一鎳/金層所化層270及第二抗氧化層· 求，僅於基板200其中使用者可依據不同的使用需 氧化層亦可。 貞,之表面上依序形成焊罩層及抗 1297940 16260twf.doc/r 圖3A〜3H繪示為本發明之具有雙層線路層之線路基 板的製作流程剖面圖，以下將搭配圖示說明本發明之線二 基板的製作方法。 首先’請參照圖3A所示，提供一第一複合導電声 310，此第一複合導電層310包括一中間金屬層316及配置 於中間金屬層316兩側之二外層金屬層312、314。在此實 施例中，外層金屬層312、314與夾置於二者間之中間金^ 層316係由不同的金屬材料所組成，如此一來，在後續圖 案化製程中，此中間金屬層316即可作為钮刻阻障層。: 本實施例中，外層金屬層312、314例如係由銅金^所構 成，而夾置於二者間的中間金屬層316例如係由鎳金屬所 構成。 接著，請參照圖3B所示，圖案化第一複合導電層31〇 一側之外層金屬層312，以形成第一圖案化線路層3l2a。 在此貝施例中，可利用微影I虫刻技術進行外層金屬層 之圖案化製程。 之後，睛參考圖3C所示，於第一複合導電層310之 外側形成一第一介電層318，此第一介電層318暴露出圖 3B中所形成之第一圖案化線路層312a，以形成一上層疊 合基板310’。此第一介電層318之製作方式，可先將一 B-stage膠填入第一圖案化線路層312a，之後，將其固化 (curing)後即可形成第一介電層318。 ’、 接下來，請參照圖3D所示，提供一第二複合導電層 320’此第二複合導電層32〇包括一中間金屬層326及配置 15 I29794Q·. doc/006The abundance layer 210 has a corresponding first surface si and a second surface S2, and includes a plurality of dielectric layers 212 and at least one composite wiring layer 214. The composite circuit layer 214 is disposed between the dielectric layers 212. The composite wiring layer 214 includes two patterned wiring layers 214a, 214b and an intermediate metal layer 214c disposed between the patterned wiring layers 214a, 214b. In one embodiment of the invention, the patterned wiring layers 214a, 214b may, for example, be formed of copper metal and sandwiched between the intermediate metal layers 2, 4c, for example, may be comprised of nickel metal. The first surface layer 220 is disposed on the first surface of the laminated layer 210 and the core is in the first surface S1, so that the + outer surface of the first surface layer 220 and the first layer of the first layer The surface §ι is coplanar. Similarly, the second surface layer 230 is disposed on the second f of the laminated layer 210 and the squad is inserted into the second surface such that the second surface acoustic surface is the same as the second surface S2 of the laminated layer 21 The plane road [20:: the line layer 220 and the second layer line layer 230 are used as the material of the line base layer 230 - the surface layer, the circuit layer 22G and the second surface layer layer are used for the system. Further, the conductive block 240 is disposed on the dielectric and second surface wiring layer 214 and the first surface wiring layer 220 曰230. In this way, the first surface layer 22 12 13 1297940 16260 twf.doc/r can be electrically connected through the conductive block 24 and the composite circuit layer. Zhongtian people are more, ^ and the electric block 24. It is made up of three layers of solid metal materials. Therefore, it will help to improve the reliability of the entire circuit board. 者 The required conductive blocks can be configured in the circuit substrate 200 according to different usage requirements. The present invention does not impose any limitation on the number, shape, and material of the conductive blocks. Continuing to refer to FIG. 2, the present invention can further configure a layer of a solder mask 250 and a 筮-p dry cover on the first surface acoustic layer 2 layer 220 and the second surface layer 23 (). The exposed portion of the first surface layer 260 also smashes only part of the second early substrate 200 and other electronic elements, as a medium for wire bonding. Niu Ruqi and passive components are electrically oxidized. Selective_ is disposed on the anti-oxidation layer 270 of the first solder mask layer 25f, and the second surface layer 220 of the wide surface layer 220 of the second anti-oxidation layer is exposed (^===================== The 220 and the second surface line are in order to prevent the formation of the surface layer of the surface layer. In this case, the oxidation of the Lth layer L is, for example, a layer of nickel/gold layer 270 and a second oxidation resistance. The layer is only required for the substrate 200 to be oxidized by the user according to different uses. 贞, the surface of the surface is sequentially formed with a solder mask layer and anti-1297940 16260 twf.doc / r Figures 3A to 3H are shown as A cross-sectional view of a circuit board having a two-layer circuit layer, and a method of fabricating the second substrate of the present invention will be described below with reference to the drawings. First, please refer to FIG. 3A to provide a first composite conductive sound 310. The first composite conductive layer 310 includes an intermediate metal layer 316 and two outer metal layers 312, 314 disposed on opposite sides of the intermediate metal layer 316. In this embodiment, the outer metal layers 312, 314 are interposed therebetween. The intermediate gold layer 316 is composed of different metal materials, so that In the continuous patterning process, the intermediate metal layer 316 can be used as a button barrier layer. In this embodiment, the outer metal layers 312 and 314 are formed, for example, of copper and gold, and sandwiched between the two. The metal layer 316 is made of, for example, nickel metal. Next, referring to FIG. 3B, the first composite conductive layer 31 is patterned on one side of the outer metal layer 312 to form a first patterned wiring layer 313a. In the embodiment, the patterning process of the outer metal layer can be performed by using the lithography I. In the third embodiment, a first dielectric layer 318 is formed on the outer side of the first composite conductive layer 310. A dielectric layer 318 exposes the first patterned wiring layer 312a formed in FIG. 3B to form an upper laminated substrate 310'. The first dielectric layer 318 can be fabricated by first using a B-stage adhesive. The first patterned wiring layer 312a is filled in, and then cured, the first dielectric layer 318 is formed. ', Next, please refer to FIG. 3D, a second composite conductive layer 320' is provided. The second composite conductive layer 32 includes an intermediate metal layer 326 and a configuration 15 I29 794Q·. doc/006
修(更)正替換頁 96-11-29 於中間金屬層326兩侧之二外層金屬層322、324。同理， 外層金屬層322、324與失置於二者間之中間金屬層326 係由不同的金屬材料所組成，如此—來，在後續圖案化製 程中，此中間金屬1326即可作為钱刻阻障層。在本實施 例中，外層金屬層322、324例如係由銅金屬所構成，而夾 置於二者間的中間金屬層326例如係由錄金屬所構成。 接著，睛荼照圖3E所示，圖案化第二複合導電層32〇 一側之外層金屬層322，以形成第二圖案化線路層322a。 在此實施例中，可利用微影蝕刻技術進行外層金屬層322 之圖案化製程。 之後，請參考圖3F所示，於第二複合導電層32〇之 外侧形成一第二介電層328，此第二介電層328暴露出上 述第二圖案化線路層322a，以形成一下層疊合基板320,。 接下來，請參考圖3G所示，提供一核心基板33〇， 其中’此核心基板330包括一核心介電層332以及配置於 核心介電層332内的多個核心導電塊334。此導電塊334 係由三層實心的金屬材料疊合而成，且各導電塊334之位 置需對應於上層疊合基板310’之第一圖案化線路層312a 與下層疊合基板320’之第二圖案化線路層322a而設置。 此核心基板330之製作方法可參考中華民國專利第 1250555號之專利說明書所述，在此不再多作贅述。 最後，請參考圖3H圖所示，將核心基板330配置於 上層疊合基板310,與下層疊合基板320’之間，並使其第一 圖案化線路層312a與第二圖案化線路層322a朝向核心基 5 16 I29794Q 1626D1 'twfl.doc/006 〇/" T ^'— ^ 和”月7日修⑽正替換頁 96-11-29 ，330，而壓合上層疊合基板31〇，、核心基板33〇與下声 豐合基板32G’，以藉由核心基板33〇内之數個核心導電^ 334導通第-圖案化線路層312a與第二圖案化線路層 322a。如此一來，即可完成線路基板3⑻之基本製程。曰 而在完成上述線路基板3〇〇之製作流程後，更可利用 下列兩種方式於線路基板3〇〇兩侧的表面形成焊罩層及抗 氧化層，以保護線路基板300中的圖案化線路免於受損及 受潮。 、 第一種方式是預先在線路基板的外圍保留所需之電鍍 線，之後，再利用電鍍的方式於圖案化線路上形成抗氧^ 層。圖4A〜4C繪示為在線路基板上預先保留下電鍍線，以 於線路基板之表面上依序形成焊罩層及抗氧化層之製作流 程剖面圖。首先，請參照圖4A所示，移除掉第一複合^ 電層31〇另一側之外層金屬層叫與中間金屬層训，以 暴，出第一圖案化線路層312a與第一介電層318;並移除 掉第一複合導電層320另一侧之外層金屬層324與中間金 屬層326,以暴露出第二圖案化線路層322a與第一介電層 之後，請參考圖4B所示，在第一介電層318與第一 圖案化線路層312a上形成一第一焊罩層34〇，並且^第二 介電層328與第二圖案化線路層322a上形成一第二焊罩層 350。其中，第一焊罩層34〇暴露出至少部分的第一圖案化 線路層312a，而第二焊罩層35〇暴露出至少部分的第二圖 案化線路層322a，以作為線路基板3〇〇與其他電子元件如 17 129794¾ iOtwfl .doc/006 ?W((月工, 日修(更)正替換頁 96-11-29 晶片、被動元件之間電性連接的媒介。 最後’請參考圖4C所示，在第-焊罩層34〇所暴露 之至少部分的第-圖案化線路層312a上形成-第一 化層360，並且在第二烊罩@ 35〇所暴露之至少部分的 二圖案化線路層355a上形成—第二抗氧化層，，以防止 第-圖案化線路層312a及第二圖案化線路層迎因接觸 到空氣而產生氧化的情形。在本實施射，此第—抗氧化 層360與第二抗氧化㉟37〇之形成方式，可例如在第—焊 罩層340所暴露之第―圖案化線路層迎以及第二焊罩 35匕所暴？之第二圖案化線路3瓜上電鍍一鎳/金層，以‘ 成第-抗氧化層360與第二抗氧化層37〇。使用者可依據 不同的使用需求’僅於線路基板3〇〇其中一侧之表面上依 序形成焊罩層及抗氧化層亦可。 而另外種於線路基板兩側之表面上形成銲罩層及抗 氧化層的方式，則是不需在線路基板周圍保留電錢^，同 樣可以在表層線路上形成抗氧化層。圖5A〜5D_示為另一 種在圖3H中所示之線路基板兩侧分別形成銲罩犀2 化層之製作流程剖面圖。 9 首先’請參考圖5A所示，移除掉第一複合導電層31〇 另-侧之外層金屬層3M’並且移除掉第二複合導電^細 =二卜層金屬層324。在此步驟中，可利用心的方 式移除掉弟一複合導電層310及第二複合導電層32〇。 之後，請參考圖5B所示，於第一複合導^ 中間金屬層训以及第二複合導電層32。之電中:，= 1297940 16260twfl .d〇c/〇〇6 曰修(€)正替換頁 96-11-29 326上上分別形成圖案化的第—抗氧化層綱， -抗氧化層37G’。在此實施例中，圖案化的^叶、卜= 圖案化的第二抗氧化層37G，之形成方式，“由二 間金屬層326上電鑛形成圖案化 層，與第二複合導電層320之中“屬層 取後，请麥考圖5D所示，在第一介電層318與二 圖案化線路層312a上形成—第—焊罩層卿，並^ 二介電層328與第二圖案化線路層322a上形成_ f1235〇，、,°fr第—焊罩層34G，覆蓋住第—圖案化Ϊ路層 —亚暴路出第一抗氧化層36〇,，而第二焊罩層35〇， 盍弟一圖案化線路層322a，並暴露出第二抗氧化層37〇,， 如此一來，即可完成線路基板兩側之銲罩層及抗^化層 製作。 曰 然而，除了上述具有雙層線路層之線路基板的製作之 外，本發明亦可應用於具有多層線路層之線路基板的製 作。圖6A〜6H繪示為具有多層線路層之線路基板的製作淹 程剖面圖。具有多層線路層之線路基板的製作方法，是在 ，3H中所示之上層疊合基板31〇，、核心基板33〇與下層 疊合基板_320’壓合之前，先進行下列步驟··首先，請參考 圖6A所示，提供一第三複合導電層38〇，其中，第三複合 導電層380包括一中間金屬層386以及配置於中間金屬層 386兩側之兩外層金屬層382、384。之後，請參考圖6b 19 1297940 16260twf.doc/r 所不’圖案化第二複合導電層—相之外層金屬層 382，以形成一第三圖案化線路層犯乃。 接著，請參考圖6C所示，於第三複合導電層38〇之 外側形成-第三介電層388，且第三介電層388暴露出第 三圖案化線路層382a，以形成一中間疊合基板通，。之 後，請參考® 6D所示，將第三圖案化線路層382a朝向核 ^基板330，而將中間豐合基板3⑽，疊合於核心基板％〇 之其中一側上。接下來，請參考圖6E所示，圖案化第三 複合導電層380另一側之外層金屬層384，以形成一第四 圖案化線路層384a。 之後，請參考圖6F所示，於第三複合導電層38〇之 另一側形成一第四介電層389，此第四介電層389是暴露 出第四圖案化線路層384a。最後，請參考圖6G所示，提 供一層間基板390於中間疊合基板38〇，與上層疊合基板 310’或中間疊合基板380，與下層疊合基板32〇，之間，並且 在壓合上層疊合基板310,、核心基板33〇與下層疊合基板 320’時，一併壓合中間疊合基板380,與層間基板390，即 可完成如圖6H中所示之具有多層線路層的線路基板4〇〇 的製作流程。其中，層間基板390包括一層間介電層392 以及配置於層間介電層392内的多個層間導電塊394，其 結構與圖3G中所示之核心基板33〇相同 ，所以，在此不 再重述。當使用者欲製作出具有更多線路層之線路基板 時’只需重覆執行圖6A〜6G中所示之步驟，即可製作出具 有更多線路層的線路基板。此外，在完成圖6G中所示之 20 1297940 16260twf.doc/r 線路基板400的製作後，可選擇性地利用圖4a〜4 5A〜5D中所示之步驟，於線路基板铜之 所= 焊罩層及抗氧化層。 喊&的 綜上所述，本發明之線路基板是利用由三層 合而成的導電塊取代傳統中空的導電通孔，以作為不= 雜連接的管道。由於本發明在基板上並不像傳 、，克，琶通孔-樣有最小尺寸的限制，因此，將有助=縮 小f路基板的面積及其厚度，使應用此線路基板之產品朝 向溥型化的方向發展；且相較於傳絲板上的導電通=之 製作流程而言’本發明之線路基板的製作流程較為精簡， 如此一來，將有助於降低線路基板之製作成本，並可提高Repair (more) positive replacement page 96-11-29 on both sides of the intermediate metal layer 326 of the outer metal layers 322, 324. Similarly, the outer metal layers 322, 324 and the intermediate metal layer 326 between the two are composed of different metal materials, so that in the subsequent patterning process, the intermediate metal 1326 can be used as a money engraving. Barrier layer. In the present embodiment, the outer metal layers 322, 324 are made of, for example, copper metal, and the intermediate metal layer 326 interposed therebetween is composed of, for example, a metal. Next, as shown in Fig. 3E, the outer metal layer 322 on the side of the second composite conductive layer 32 is patterned to form a second patterned wiring layer 322a. In this embodiment, the patterning process of the outer metal layer 322 can be performed using a photolithographic etching technique. Then, as shown in FIG. 3F, a second dielectric layer 328 is formed on the outer side of the second composite conductive layer 32, and the second dielectric layer 328 exposes the second patterned circuit layer 322a to form a lower layer. The substrate 320 is combined. Next, referring to FIG. 3G, a core substrate 33 is provided, wherein the core substrate 330 includes a core dielectric layer 332 and a plurality of core conductive blocks 334 disposed in the core dielectric layer 332. The conductive block 334 is formed by laminating three layers of solid metal material, and the positions of the conductive blocks 334 are corresponding to the first patterned circuit layer 312a and the lower laminated substrate 320' of the upper laminated substrate 310'. The second wiring layer 322a is provided. For the manufacturing method of the core substrate 330, reference may be made to the patent specification of the Patent No. 1250555 of the Republic of China, and no further description is made herein. Finally, referring to FIG. 3H, the core substrate 330 is disposed between the upper laminated substrate 310 and the lower laminated substrate 320', and the first patterned wiring layer 312a and the second patterned wiring layer 322a are disposed. Towards the core base 5 16 I29794Q 1626D1 'twfl.doc/006 〇/" T ^'- ^ and "May 7th repair (10) is replacing pages 96-11-29, 330, and the laminated substrate 31 is laminated, The core substrate 33A and the lower sound balance substrate 32G' are used to turn on the first patterned circuit layer 312a and the second patterned circuit layer 322a by a plurality of core conductive electrodes 334 in the core substrate 33. The basic process of the circuit substrate 3 (8) can be completed. After completing the manufacturing process of the circuit substrate 3, the solder mask layer and the anti-oxidation layer can be formed on the surfaces of the two sides of the circuit substrate 3 by the following two methods. In order to protect the patterned circuit in the circuit substrate 300 from damage and moisture. The first way is to reserve the required plating line on the periphery of the circuit substrate in advance, and then form the pattern on the patterned circuit by electroplating. Anti-oxidation layer. Figures 4A to 4C are shown in the line The plating line is preliminarily retained on the board to form a cross-sectional view of the manufacturing process of the solder mask layer and the anti-oxidation layer on the surface of the circuit substrate. First, referring to FIG. 4A, the first composite electric layer 31 is removed. The outer metal layer on the other side is called an intermediate metal layer to blast out the first patterned circuit layer 312a and the first dielectric layer 318; and the outer metal layer on the other side of the first composite conductive layer 320 is removed. After the layer 324 and the intermediate metal layer 326 are exposed to expose the second patterned wiring layer 322a and the first dielectric layer, please refer to FIG. 4B to form on the first dielectric layer 318 and the first patterned wiring layer 312a. a first solder mask layer 34, and a second solder mask layer 350 is formed on the second dielectric layer 328 and the second patterned wiring layer 322a. The first solder mask layer 34 exposes at least a portion of the first solder mask layer A patterned wiring layer 312a is formed, and the second solder mask layer 35 is exposed to at least a portion of the second patterned wiring layer 322a to serve as the wiring substrate 3 and other electronic components such as 17 1297943⁄4 iOtwfl .doc/006 ?W ( (monthly, daily repair (more) is replacing page 96-11-29 wafer, passive components between the electrical connection Finally, please refer to FIG. 4C, forming a first layer 360 on at least a portion of the first patterned circuit layer 312a exposed by the first solder mask layer 34, and at the second mask @35 A second anti-oxidation layer is formed on at least a portion of the two patterned circuit layers 355a exposed to prevent the first patterned circuit layer 312a and the second patterned circuit layer from oxidizing due to contact with air. In the present embodiment, the first anti-oxidation layer 360 and the second anti-oxidation layer 3537 can be formed, for example, in the first-patterned circuit layer exposed by the first solder mask layer 340 and the second solder mask 35 Storm? The second patterned line 3 is plated with a nickel/gold layer to form a first anti-oxidation layer 360 and a second anti-oxidation layer 37. The user can form the solder mask layer and the anti-oxidation layer only on the surface of one side of the circuit substrate 3 according to different usage requirements. In addition, the manner in which the solder mask layer and the anti-oxidation layer are formed on the surfaces on both sides of the circuit substrate is such that it is not necessary to reserve electricity around the circuit substrate, and an oxidation resistant layer can be formed on the surface layer. 5A to 5D are cross-sectional views showing another manufacturing process of forming a solder mask rhinoceros layer on both sides of the circuit substrate shown in Fig. 3H. 9 First, please refer to FIG. 5A, the first composite conductive layer 31 〇 the other-side outer metal layer 3M' is removed and the second composite conductive layer 2 bis-layer metal layer 324 is removed. In this step, the core-composite conductive layer 310 and the second composite conductive layer 32A can be removed by means of a heart. Thereafter, referring to FIG. 5B, the first composite conductive metal layer and the second composite conductive layer 32 are formed. In the electricity:, = 1297940 16260twfl .d〇c / 〇〇 6 曰 repair (€) is replacing page 96-11-29 326 respectively to form a patterned first anti-oxidation layer, - anti-oxidation layer 37G' . In this embodiment, the patterned pattern, the patterned second oxidation resistant layer 37G is formed in such a manner that "the patterned metal layer is formed by the two metal layers 326, and the second composite conductive layer 320 is formed. After the genus layer is taken, please refer to the first dielectric layer 318 and the second patterned circuit layer 312a, as shown in FIG. 5D, the first solder mask layer, and the second dielectric layer 328 and the second layer. Forming the circuit layer 322a to form _f1235〇,, °fr first-welding layer 34G, covering the first-patterned circuit layer-substorm road out of the first anti-oxidation layer 36〇, and the second welding cap The layer 35A, the younger one patterned the circuit layer 322a, and exposes the second anti-oxidation layer 37〇, so that the solder mask layer and the anti-chemical layer on both sides of the circuit substrate can be completed. However, in addition to the above-described fabrication of a wiring substrate having a double-layer wiring layer, the present invention is also applicable to the fabrication of a wiring substrate having a multilayer wiring layer. 6A to 6H are cross-sectional views showing the fabrication of a circuit substrate having a plurality of wiring layers. The circuit board having the multilayer wiring layer is formed by laminating the substrate 31A as shown in 3H, and before the core substrate 33〇 and the lower laminated substrate _320' are pressed together, the following steps are performed first. Referring to FIG. 6A, a third composite conductive layer 38 is provided. The third composite conductive layer 380 includes an intermediate metal layer 386 and two outer metal layers 382, 384 disposed on opposite sides of the intermediate metal layer 386. Thereafter, please refer to FIG. 6b 19 1297940 16260 twf.doc/r to pattern the second composite conductive layer-phase outer metal layer 382 to form a third patterned circuit layer. Next, referring to FIG. 6C, a third dielectric layer 388 is formed on the outer side of the third composite conductive layer 38, and the third dielectric layer 388 exposes the third patterned circuit layer 382a to form a middle stack. The substrate is connected. Thereafter, as shown in Fig. 6D, the third patterned wiring layer 382a is directed toward the core substrate 330, and the intermediate rich substrate 3 (10) is superposed on one side of the core substrate %〇. Next, referring to FIG. 6E, the outer metal layer 384 on the other side of the third composite conductive layer 380 is patterned to form a fourth patterned wiring layer 384a. Then, referring to FIG. 6F, a fourth dielectric layer 389 is formed on the other side of the third composite conductive layer 38, and the fourth dielectric layer 389 exposes the fourth patterned circuit layer 384a. Finally, referring to FIG. 6G, an inter-layer substrate 390 is provided on the intermediate laminated substrate 38, with the upper laminated substrate 310' or the intermediate laminated substrate 380, and the lower laminated substrate 32'', and pressed When the laminated substrate 310, the core substrate 33A and the lower laminated substrate 320' are closed, the intermediate laminated substrate 380 is pressed together, and the interlayer substrate 390 is completed to have a multilayer wiring layer as shown in FIG. 6H. The production process of the circuit substrate 4〇〇. The interlayer substrate 390 includes an interlayer dielectric layer 392 and a plurality of interlayer conductive blocks 394 disposed in the interlayer dielectric layer 392. The structure is the same as that of the core substrate 33A shown in FIG. 3G, so Retelling. When the user wants to make a circuit substrate having more wiring layers, it is only necessary to repeatedly perform the steps shown in Figs. 6A to 6G to fabricate a wiring substrate having more wiring layers. In addition, after the fabrication of the 20 1297940 16260 twf.doc/r circuit substrate 400 shown in FIG. 6G is completed, the steps shown in FIGS. 4a to 4 5A to 5D can be selectively used to solder the copper on the circuit substrate. Cover layer and anti-oxidation layer. Shout & In summary, the circuit substrate of the present invention replaces a conventional hollow conductive via with a three-layer conductive block as a non-heterojunction. Since the present invention does not have a minimum size limitation on the substrate, it will help to reduce the area of the f-channel substrate and its thickness, so that the product to which the circuit substrate is applied is oriented. The direction of the development is progressed; and the manufacturing process of the circuit substrate of the present invention is relatively simple compared to the manufacturing process of the conductive wire on the wire plate, which will help to reduce the manufacturing cost of the circuit substrate. And can improve
其生產效率。 N 此外，本發明之線路基板主要是將複合導電層中的外 層金屬層進行目案化製程，以形成圖案化線路層，之後， 再將^電材料填入於圖案化線路層中，以形成一疊合基 板。/藉由多個疊合基板、核心基板與層間基板之疊合，即 ^成/、有夕層線路層之線路基板。因此，利用本發明所 之方法製作而成的線路基板具有較佳之平整度^如此 末即了防止線路基板兩側後續形成之抗氧化層及焊罩 層由線路基板上祕的情形。再者，由於本發明之圖案化 2表層線路層其位於線路基板表面之一側具有較大的表面 知，因此，當電流流經表層線路時，將有助於降低其阻抗 值。 雖然本發明已以較佳實施例揭露如上，然其並非用以 21 1297940 16260twf.d〇c/r 明，任何熟習此技藝者’在不脫離本發明之件、由 範圍當^見後附之申請專利範園所界定者為準匕本毛明之保護 【圖式簡單說明】 習知之—種線路基板的剖面示意圖。 f官不為本發明之線路基板的結構剖面圖。 M〜3H料縣糾之射雙麟⑽之纽其 板的製作流程剖面圖。 ㈢之線路基 圖4A 4C緣示為在線路基板 雷 側分^形成種在圖3H中所示之線路基板兩 二面圖。 流程剖面圖。‘、、、有夕層树層之祕基板的製作 【主要元件符號說明】 100 ·線路基板 110 :圖案化線路層 120 :圖案化線路層 130 :圖案化線路層 140 :圖案化線路層 150 :介電層 160 :介電層 170 :介電層 22 1297940 16260twf.doc/r . 180 :導電通孔 200 :線路基板 210 :疊合層 212 :介電層 214 :複合線路層 214a :圖案化線路層 214b :圖案化線路層 $ 214c :中間金屬層 220 :第一表層線路層 230 :第二表層線路層 240 :導電塊 250 :第一焊罩層 260 :第二焊罩層 270 ··第一抗氧化層 280 :第二抗氧化層 300 :線路基板 • 310 :第一複合導電層 310’ ：上層疊合基板 312 :外層金屬層 312a :第一圖案化線路層 314 :外層金屬層 316 :中間金屬層 . 318 :第一介電層 320 :第二複合導電層 23 1297940 16260twf.doc/r . 320’ ：下層疊合基板 322 :外層金屬層 322a :第二圖案化線路層 324 :外層金屬層 326 :中間金屬層 328 :第二介電層 330 :核心基板 $ 332 :核心介電層 334 :核心導電塊 340 :第一焊罩層 340’ ：第一焊罩層 350 :第二焊罩層 350’ ：第二焊罩層 360 :第一抗氧化層 360’ ··第一抗氧化層 370 :第二抗氧化層 ❿ 370’ ：第二抗氧化層 380 :第二複合導電層 380’ ：中間疊合基板 382 :外層金屬層 382a :第三圖案化線路層 384 :外層金屬層 . 384a :第四圖案化線路層 386 :中間金屬層 24 1297940 16260twf.doc/r 388 ··第三介電層 389 :第四介電層 390 :層間基板 392 :層間介電層 394 :層間導電塊 400 ··線路基板 51 :第一表面 52 ··第二表面Its production efficiency. In addition, the circuit substrate of the present invention mainly performs the meshing process of the outer metal layer in the composite conductive layer to form a patterned circuit layer, and then fills the electroconductive material into the patterned circuit layer to form A stack of substrates. / By a plurality of stacked substrates, a core substrate and an interlayer substrate, that is, a circuit substrate having an integrated circuit layer. Therefore, the circuit substrate produced by the method of the present invention has a preferable flatness. Thus, the anti-oxidation layer and the solder mask layer which are subsequently formed on both sides of the circuit substrate are prevented from being secreted on the circuit substrate. Furthermore, since the patterned 2 surface wiring layer of the present invention has a large surface on one side of the surface of the wiring substrate, when the current flows through the surface wiring, it contributes to lowering the impedance value. Although the present invention has been disclosed above in the preferred embodiments, it is not intended to be used by those skilled in the art, and is not limited to the scope of the present invention. The definition of the patent application park is the protection of the standard Mao Ming [simplified description of the drawing]. f is not a structural sectional view of the circuit substrate of the present invention. M~3H is the cross-section of the production process of the board of the county. (3) Line Base Figure 4A shows the relationship between the 4C and the circuit substrate shown in Figure 3H. Process profile. [,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, Dielectric layer 160: Dielectric layer 170: Dielectric layer 22 1297940 16260twf.doc/r. 180: Conductive via 200: Circuit substrate 210: Laminated layer 212: Dielectric layer 214: Composite wiring layer 214a: Patterned wiring Layer 214b: patterned circuit layer $214c: intermediate metal layer 220: first surface layer circuit layer 230: second surface layer circuit layer 240: conductive block 250: first solder mask layer 260: second solder mask layer 270 · first Antioxidant layer 280: second oxidation resistant layer 300: wiring substrate • 310: first composite conductive layer 310': upper laminated substrate 312: outer metal layer 312a: first patterned wiring layer 314: outer metal layer 316: middle Metal layer. 318: first dielectric layer 320: second composite conductive layer 23 1297940 16260twf.doc/r. 320': lower laminated substrate 322: outer metal layer 322a: second patterned circuit layer 324: outer metal layer 326: intermediate metal layer 328: second dielectric layer 330: core base $332: core dielectric layer 334: core conductive block 340: first solder mask layer 340': first solder mask layer 350: second solder mask layer 350': second solder mask layer 360: first anti-oxidation layer 360 First anti-oxidation layer 370: second anti-oxidation layer 370 370': second oxidation-resistant layer 380: second composite conductive layer 380': intermediate laminated substrate 382: outer metal layer 382a: third patterned circuit Layer 384: outer metal layer. 384a: fourth patterned circuit layer 386: intermediate metal layer 24 1297940 16260twf.doc/r 388 · third dielectric layer 389: fourth dielectric layer 390: interlayer substrate 392: interlayer Electrical layer 394: interlayer conductive block 400 · circuit substrate 51: first surface 52 · second surface