TWI267969B - Circuit substrate, method of fabricating the same and chip package structure using the same - Google Patents

Abstract

A circuit substrate including a core layer and a stacked layer disposed thereon is provided. The stacked layer includes a first dielectric layer, a circuit layer, a solder mask layer and at least one first bump. The first dielectric layer is disposed on the core layer. The circuit layer is disposed on the core layer and lodged in the first dielectric layer, and the core layer includes a first conductive layer connected to the core layer and a second conductive layer disposed on the first conductive layer. The solder mask layer is disposed on the first dielectric layer. The first bump is disposed on the first dielectric layer and lodged in the solder mask layer. The first bump is electrically connected to the circuit layer, and exposed from the solder mask layer. The circuit substrate is electrically connected to other devices through the first bump, to improve the convenience in use.

Description

[Technical Field] The present invention relates to a circuit board and a method of fabricating the same, and more particularly to a circuit board having a bump on its surface and a method of fabricating the same. [Prior Art]

Flip Chip Bonding Technology (FC) is a packaging technology for connecting a die to a carrier, which is mainly used to form a plurality of wafer pads by means of an area array. (diepad) is disposed on the active surface of the wafer

And forming a bump on the wafer pad, and then flipping the wafer (fUp), and then through the bumps, the wafer pads on the surface of the wafer are electrically and structurally connected to the load crying The contact is such that the wafer can be electrically connected to the carrier via the bumps and then electrically connected to the outside via the internal wiring. Since the flip chip bonding technology (FC) can be applied to the chip package structure of the high pin count (figh wish Count), and has many advantages such as reducing the chip package area and shortening the signal transmission path pinch, etc., the flip chip bonding technology has been Widely used in high-end wafer packaging. FIG. 1 is a cross-sectional view showing a conventional flip chip package structure. Referring to FIG. 1, the flip chip package structure 1 〇〇 mainly includes a b-chip m-substrate 120 and a plurality of bumps 130. Wherein the 'wafer 11 is located above the US plate 120' and has a plurality of wafer pads 112 on the active surface s facing the substrate 120; the plurality of ball bottom metal layers 114 are respectively disposed on the wafer pad 112; The cap layer 116 is disposed on the active surface s 6 126796 of the wafer 11 from 778 twfd 〇 c / g, and exposes a portion of the bottom metal layer 114. A plurality of pads 122 are disposed on the surface of the substrate 120. The wafer pad 112 on the wafer cassette (1) is electrically and structurally connected to the wafer pad 13 through the bumps 13

The pads 122 are used to transmit the signal between the substrate 12 and the wafer 11A. In addition, a primer layer (1111, 11) 140 is generally formed between the wafer 110 and the substrate 〇2〇 to buffer the thermal stress generated between the wafer 11 and the substrate 120 by the underlying layer 14 It is prevented that the bumps 13A and the wafer 110' or the junction of the bumps 130 and the substrate 12 are broken. Furthermore, the bump process for forming the bumps 130 includes the following steps: First, a photoresist layer is formed on the wafer, and a plurality of openings are formed on the photoresist layer by using a lithography process, and the openings are formed. Used to determine the location of the bump formation. Next, a solder paste is filled in the opening of the photoresist layer by printing or plating to form a plurality of conductive pillars. After that, the photoresist layer is removed. The conductive columns are reflowed to form a spherical bump. However, the conventional flip chip packaging process has the following disadvantages: (1) The bump process for forming the bumps is quite complicated, and therefore, not only the manufacturing time of the entire flip chip package structure but also the manufacturing cost thereof is increased. (2) In a conventional flip chip package structure, an underfill dispensing process is used to fill the underfill between the wafer and the substrate. In this way, not only is there an additional process required, but since the underfill process has already faced a bottleneck, the poor underfill process will create voids in the make layer, resulting in delamination between the wafer and the substrate. The phenomenon. SUMMARY OF THE INVENTION An object of the present invention is to provide a circuit substrate having at least one bump on its surface as a bump in a flip chip package structure. It is still another object of the present invention to provide a method of fabricating a circuit substrate by integrating the fabrication of the bumps into the fabrication process of the substrate to simplify the fabrication of the flip chip package structure. Another object of the present invention is to provide a chip package structure in which a wafer is bonded to the above-mentioned circuit substrate by a flip chip bonding technique or a wire bonding technique to simplify the process of the chip package structure. To achieve the above or other objects, the present invention provides a circuit substrate mainly comprising a core layer and a laminated layer disposed on the core layer. The core layer has at least one conductive structure extending through the core layer; the laminated layer includes a first dielectric layer, a circuit layer, a solder mask layer and at least one first bump. The first dielectric layer is disposed on the core layer; the circuit layer is disposed on the core layer and located in the first dielectric layer, wherein the circuit layer comprises a first conductor layer connected to the core layer and a first conductor a second conductor layer on the layer; the solder mask layer is disposed on the first dielectric layer; the first bump is disposed on the first dielectric layer and located in the solder mask layer, wherein the first bump system and the line The layers are electrically connected and the solder mask layer exposes the top surface of the first bump. In an embodiment of the invention, the core layer includes a second dielectric layer and at least one conductive block. The second dielectric layer has a corresponding one of the first surface and a second surface. The conductive block is disposed in the second dielectric layer and includes a second bump, a third bump, and a metal layer. Further, the metal layer is disposed between the second bump and the third bump. 8 I2679^8twfdoc/g You: In one embodiment, including copper, (4) gold material package _ bumps are made of three-bump material in a second conductor layer of an embodiment of the present invention; The material of the first layer is copper; in one embodiment of the invention, the material of 2 comprises copper. The layer, which is disposed on the solder mask layer, is exposed to 2 substrates and further includes - an oxidation resistant layer comprising a nickel/gold layer. 77 on a bump. This antioxidant layer is the surface of the solder mask layer in one embodiment of the invention. In addition, the first bump may be convex or recessed on the surface. The surface of a bump can also be cut into the solder mask layer. Further, the present invention proposes the following steps. Firstly, a method for fabricating a circuit substrate is provided, comprising: a plurality of metal layers 4 combined with the composite conductive layer being at least a metal layer, and having a shape S number; a bump, a bump layer formed between the bumps, and a bump . After that, on the first side. Next, patterning the composite dry conductor layer thickness exposes the top wiring layer of the first bump. Thereafter, a dielectric layer is formed on the side of the solder mask layer to form a laminated layer, a first top surface between the wiring layers. Next, a core is provided; the second electrical layer exposes the circuit layer through the core layer. The last day has at least a conductive structure through the layer (10) and the core (10) = shirt layer and core - such that the line metal composite conductive layer comprises between the - first outer layer and the second outer gold layer; Located in the first-outer metal layer 1 to the genus layer. Whereas at least the metal layer of the patterned composite conductive layer 9 1267969^-8 is patterned, the patterned composite conductive layer is further characterized by an external waste & genus layer, and a genus layer and an intermediate metal layer. - Bu (4)' is the patterning of the second outer layer of gold, and is further on the block where the cladding layer and the core layer are joined. The method for fabricating the substrate in the first embodiment of the present invention further comprises forming a sacrificial layer::=Τ, the film is exposed to the top surface of the first bump. On the cover layer, sacrificing the soul iif in the embodiment, after the bonding layer is bonded to the core and the layer, the germanium further includes removing the sacrificial film so that the first bump protrudes from the solder mask layer. In the embodiment of the present invention, after the laminated layer is bonded to the core layer, the method of fabricating a circuit substrate further includes removing a portion of the first bump and a bump to be recessed in the solder mask layer. In order to achieve the above or other objects, the present invention further proposes a wafer, , , . The structure includes a wafer and the above-described wiring substrate. The wafer system is disposed on the substrate, and is electrically connected to the line through a flip chip bonding technique, a wire bonding technique, or the like. Since the structure of the wire board is the same as that of the upper circuit board, it will not be repeated here. In summary, the present invention (the circuit substrate is a process towel for integrating the fabrication of the bumps on the circuit substrate), so that the surface of the substrate is a bump, so as to effectively simplify the process of the flip chip package structure. And increase the convenience of the use of the line.

The above and other objects, features and advantages of the present invention will become more apparent from the < Embodiments Fig. 2 is a cross-sectional view showing the structure of a wiring board of the present invention. Please refer to FIG. 2'. The circuit substrate 200 belongs to a circuit substrate having a single-layer circuit layer, and mainly includes a core layer 210 and a laminated layer 220. Hereinafter, the components in the circuit substrate 2A and their corresponding components will not be described in detail. The core layer 210 has at least one conductive structure extending through the core layer 210. In this embodiment, the conductive structure is a conductive block 214. The stack 220 is disposed on the core layer 21, and includes a first dielectric layer milk pan, a circuit layer 224, a solder mask layer 226, and at least one first bump (10). A dielectric layer 222 is configured. Above the core layer 21〇. The circuit layer 224 is also disposed on the core layer 21 and embedded in the first dielectric layer 222 to serve as the signal conductor of the circuit substrate 2 . The circuit layer 224 includes a body layer 224a and a second conductor, wherein the first conductor layer 22 is connected to the layer 210 and the second conductor layer is located in the embodiment of the present invention. The first conductor layer is added to the dielectric layer 222, and: eight (four) cores; = 228 is disposed in the first screen 994 dry from the dry cover layer 226. The first bump 228 is i-faced and the solder mask layer 226 is exposed to expose the top surface of the first bump. Thus, the first bump 228 can be used as the circuit substrate 1267. twf.doc/g 200 and other electronic components such as crystal dielectric. In this Wei-plus ^, ===7 / connected media here, the material can be copper. Surface. However, the first bump 228 is tangent to the welding The stencil of the cover layer 226. The one brother 228 may also protrude or be recessed on the surface of the solder mask rhinoceros 226, which is not limited in the present invention. The cover layer 226 is formed by the second dielectric layer 2 The conductive block 214 is composed of a second surface to the first surface su and a second surface = 12 having a corresponding - electric layer trace and the conductive block 214 is: the electric ? 214 is summarized in the fourth The conductive block 2; ^ is composed of /MM. Further, for example: copper, brocade, copper, and the like:]: the metal material of the core is superposed and the second bump 214a, the metal layer 2l4bD; Used to form 'will help to improve the entire circuit substrate 2 ^ ^ ^ 214C ' such a conductive block 214 required by the user according to different usage requirements, core 2, The present invention does not impose any restrictions on the positional configuration and the material of the present invention. For the number and shape of the conductive blocks 214, the circuit substrate 200 may also be provided with a layer 230. The oxidation resistant layer 230 is disposed, and has an anti-emulsification- Above the bumps 228 to prevent the first oxidation of the first cap layer 226. In this embodiment, the film is composed of a nickel/gold layer. The deuterated layer 230 is composed of, for example, Again, in addition to the ancient mouth 200 shown in Figure 2, this wealth can be placed on the upper and lower sides of the circuit board of the nuclear evil ^ riding layer 12

I26796Q?8twf.d〇c/g - The laminated layer 22A, as shown in Fig. 3, is made into a circuit substrate 200' having a double-layer wiring layer. In this embodiment, the first bumps 228 in the crystalline layer 220 above the core layer 2i are protruded from the surface of the solder mask layer 226, and the first of the stacked layers 220 below the core layer 210. The bumps 228 are flushed to the surface of the solder mask layer 226. However, the user can make the first convex in the overlapping layer 22〇 on both sides of the core layer 21 according to different needs.

The block 228 is convex, recessed, or tanged to the surface of the solder mask layer 226, and the present invention is not limited in any way. X Figures 4A to 4G are cross-sectional views showing the fabrication of a single-layer wiring board of the present invention, and the following is a method of performing the sputtering of the substrate. First, please refer to FIG. 4A, a composite conductive layer 310 is provided by laminating a plurality of metals. The composite conductive layer includes a first-outer metal layer 3 lt ^ 及 and a sandwich In the middle of the metal layer between the two. The material of the genus layer 31Ga, the intermediate metal layer 31% and the second outer layer i ^ C may be copper, nickel and copper, respectively. The composite conductive layer 31 五 五 five layers are patterned to form a plurality of first bumps 312 as shown by the outer side 5 Π 4B. In this embodiment, the image is formed by lithography and rice-rooting, to form a plurality of layers 310a between the first bumps 312/^12. ^, after referring to _4C, the second solder mask layer t320' is exposed and the solder mask layer 320 is patterned to the composite conductive layer 310 = lower f, as shown in FIG. 4D, the tantalum layer 31 is another An outer side 'to form a wiring layer 13 12 6796 ^ 778 twf.doc / g 330. In this embodiment, the second outer layer 330 is made in the middle of the metal. In addition, after the circuit layer 33 is formed to form the circuit layer, the pattern shown in FIG. 4E is matched with the bump 312. The circuit layer 330 is formed on the solder mask layer 320. Bit

=:=Through the wire "conducting block 214, the bonding layer 300 and the core layer 210 of the two sides in FIG. 4E, the internal man-in-one, and the core layer 210 are pressed: The top surface is connected to the core layer 210, so that the circuit board 400 of the present invention is completed. In the steps shown in FIG. 4F, the core of FIG. 2 is taken as an example for illustration. However, the present invention may also employ a suitable core layer of the bean to be bonded to the laminated layer. The present invention does not impose any limitation on the type of the core layer.

Further, referring to FIG. 4G, after the fabrication of the basic circuit substrate 4 is completed, the oxidation resist layer 230 may be formed on the first bumps 312 exposed by the solder mask layer 320. The oxidation resistant layer 230 is disposed over the first bumps 228 exposed by the solder mask layer 226 to prevent oxidation of the first bumps 228 due to contact with air. The spear J is formed on the circuit substrate 4 by the above steps, and the first bumps 312 are aligned with the solder mask layer 32. However, the user can also cause the formed first bump 312 to protrude from the solder mask layer 320 by the following steps. Fig. 5Α~5Ε 14 I267969778twf.d〇c/g A production flow substrate cross-sectional view. First, in the same steps as shown in the sin, the one side of the composite conductive layer 31 is shaped like a bump 312. Thereafter, please refer to FIG. 5A, the solder mask layer 32G' of the first bump 312. The layer 320 has a height slightly lower than the degree of return of the A12 and exposes the top surface of the first bump M2. Next, 3^11, FIG. 5B, on the solder mask layer 320, a cover is formed on the first bump. For the convenience of the subsequent process, the surface of the sacrificial film 36() can be ground by machine or grinding to keep it flat and the user can adjust the degree of the sacrificial film 360 2 according to different usage requirements, so that the sacrifice is made. The film covers the first bump 312, or the top surface of the convex one is exposed by the sacrificial thin moon. In this implementation, the sacrificial diaphragm 360 exposes the top surface of the first bump 312. Thereafter, referring to FIG. 5C, the other outer side of the composite conductive layer 31 is patterned to form a wiring layer 330. Next, please refer to the item 5D, and a first dielectric layer 340 located between the wiring layers 3, for example, is formed on the cap layer 320 to form a stacked layer 300. Then, referring to FIG. 5E, the laminated layer 300 shown in FIG. 5D is bonded to a core layer 21, and the sacrificial film 360 is removed, so that the fabricated circuit substrate 4 can be fabricated. The first protrusion 312 protrudes from the solder mask layer 32. Similarly, an anti-oxidation layer (not shown) may be selectively disposed on the first bump 312 of the circuit substrate 4A to prevent oxidation of the first bump 312 due to contact with air. situation. In the above process, only the circuit substrate having a single circuit layer is taken as an example. However, the user may also sandwich a core layer between the two laminated layers 15 12679697781 ^ d〇c/g to form A circuit substrate having a double layer circuit layer. In addition, the present invention also alternately stacks the layer of the layer and the layer of the layer to form a circuit substrate having a plurality of circuit layers. The present invention does not use the number of layers of the stacked layer and the core layer in the circuit substrate. Any restrictions. Figure 6 is a cross-sectional view of a circuit substrate which is not another embodiment of the present invention. Referring to Fig. 6, the circuit substrate 4 is composed of two laminated layers 300', 300'' and a core layer 21 sandwiched therebetween. The laminated layer 300 above the core layer 210 has a first bump 312 protruding from the solder cap layer 320. The first layer 312' of the laminated layer 300 under the core layer 210 is recessed in the solder mask layer 32. In this embodiment, a portion of the first bump 312 may be removed by etching to recess it in the solder mask layer 320''. The first bump 312' is recessed in the solder mask layer 32, and the design of the first bump 312' will be facilitated to be subsequently formed on the first bump 312. A cross-sectional view of the substrate in its actual application. Referring to FIG. 7, the circuit substrate 4 of the present invention is adapted to be disposed in a carrier state 500 to electrically connect to the carrier 5 via the solder balls formed on the first bumps 312. A wafer 600 is disposed on the line of the US Cup, and the circuit substrate is electrically connected directly through the first bump == sheet 600. In addition, in the substrate 6A and the circuit substrate 4, a bonding material may be filled in the bonding place to ensure the electrical connection between the chip 6 and the circuit substrate 4, and the electrical connection between the two. FIG. 8 is a schematic cross-sectional view showing another circuit substrate of the present invention in practical use. Referring to FIG. 8, the arrangement of the carrier 500, the circuit substrate 400, and the wafer 600 is substantially the same as that shown in FIG. 7, but the first 16 I267969778 twfdoc/ of the laminated layer 3 (10) g, block, is cut in the solder mask layer 32o, and the 7th meaning load 500 is electrically connected. In the case of the ghost 312, the circuit substrate and the crystal substrate can be directly electrically connected by the convex substrate formed on the surface of the circuit substrate, the carrier table, and the wire bonding method. The electric wire between the soldering piece and the circuit board and the carrier, and the substrate and crystal of the sister. The switching method of the present invention is not limited to the above, the circuit substrate of the present invention is a manufacturing process towel of the circuit substrate, so that the circuit base of the job is integrated into the block to effectively simplify the reverse four sides of the structure of the flip chip I. The convex plate is intended to be connected to other components (such as the carrier, the wafer 4, when the circuit is connected to the base, so that the bumps on the circuit substrate can be increased according to the difference of 4=:. Furthermore, the solder mask layer is recessed or cut, so that the circuit substrate can be protruded and recessed through the solder balls formed on (10) and the other 5 through the bumps or although the present invention has been disclosed in the preferred embodiment. As defined above, any person skilled in the art, regardless of the scope of use, can make some changes and refinements, because:: the spirit of the scope of the application is attached to the application of the __defense & protection BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a conventional flip-chip package structure. FIG. 2 is a cross-sectional view showing the structure of the circuit substrate of the present invention. FIG. A cross-sectional view of a double-layered circuit material 丨 = a line having a single-layer circuit layer of the present invention The road substrate is shown as the production process profile of the hairline

126796^78twfd〇c/g

4A to 4E are cross-sectional views of the manufacturing process. Figs. 5A to 5E are diagrams showing another embodiment of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 7 is a cross-sectional view of a circuit substrate of an embodiment. The cross-sectional view 8 of the actual application is shown as another schematic diagram of the present invention. The cross section of the circuit board in actual application [main symbol description] 1〇〇: flip-chip sealing structure 110 · wafer 112 · Wafer 114: ball bottom metal layer 116: solder mask layer 120 · substrate 122 : pad 130 : bump 140 : underlying layer 200 · circuit substrate 200 · circuit substrate 210 · core layer 212 : second dielectric layer 214 : Conductive block 18 d〇c/g

214a: second bump 214b: metal layer 214c: third bump 220: laminated layer 222: first dielectric layer 224: wiring layer 224a: first conductor layer 224b: second conductor layer 226: solder mask layer 228 : first bump 230 : oxidation resistant layer 300 : laminated layer 300 , • 'laminated layer 300 ′′ : laminated layer 310 : composite conductive layer 310 a : first outer metal layer 310 b : intermediate metal layer 310 c : second outer layer Metal layer 312: first bump 312, • first bump 320: solder mask layer 320, solder mask layer 320,, solder mask layer 330: circuit layer 19 126796^78twf.doc/g 340: first Dielectric layer 350: anti-oxidation layer 360: sacrificial film 370: solder ball 400 · circuit substrate 400': circuit substrate 400": circuit substrate 400"": circuit substrate 500 · · carrier 600 · wafer 610 · primer material S: active surface 51: first surface 52 · second surface

Claims (1)

126 V 96^78twfd〇c/s X. Patent application scope: 1. A circuit substrate comprising: a core layer having at least one conductive structure penetrating the core layer; and a laminated layer disposed on the core layer The laminated layer includes: a first dielectric layer disposed on the core layer; a circuit layer disposed on the core layer and located in the first dielectric layer, wherein the circuit layer includes a core a first conductor layer connected to the layer and a second conductor layer on the first conductor layer; a solder mask layer disposed on the first dielectric layer; and at least one first bump disposed on the first The dielectric layer is located in the solder mask layer, wherein the first bump is electrically connected to the circuit layer, and the solder mask layer exposes a top surface of the first bump. 2. The circuit substrate of claim 1, wherein the core layer comprises: a second dielectric layer having a corresponding one of the first surface and a second surface; and at least one conductive block disposed on In the second dielectric layer, the conductive block includes a second bump, a third bump, and a metal layer, and the metal layer is disposed between the second bump and the third bump. 3. The circuit substrate of claim 2, wherein the material of the second bump comprises copper. 4. The circuit substrate of claim 2, wherein the material of the third bump comprises copper. 5. The circuit substrate according to claim 2, wherein the material of the gold 21 I267969778twf.d〇c/g layer comprises nickel. The material of the wiring layer of the circuit board according to the first aspect of the invention is the copper material. - The first substrate of the circuit board of the first aspect of the invention is the nickel material. 8+ Application for the circuit board of the first rhyme of the first town. The material of the bump includes copper. Further, a bump is formed on the bump, and the ram layer is disposed on a portion of the first bump exposed by the solder mask layer. The circuit substrate described in the above paragraph (4), wherein the anti-deuteration layer comprises a nickel/gold layer. The circuit substrate of claim 1, wherein the first bump protrudes from a surface of the solder mask layer. The circuit substrate of claim 2, wherein the first bump is recessed on a surface of the solder mask layer. A circuit board as claimed in claim 1, wherein the surface of the first block is cut to the surface of the solder mask layer. A method for fabricating a circuit substrate, comprising: providing a composite conductive layer, wherein the composite conductive layer comprises a plurality of metal patterned at least one metal layer on an outer side of the composite conductive layer to form a first plurality of first bumps Forming a solder mask layer between the first bumps, and the solder mask layer exposes the top surfaces of the brother-bumps; 22 I267969778twf.d〇c/g === electric layer "~ formation-line a top layer; a top layer; g /, a ''an electric layer exposing the circuit layer to provide a core layer, which is at least right-layer; and /, a through-structure through the core core layer and a 4-core layer' In order to make the top surface of the circuit layer and the method, the fabrication of the circuit substrate of the circuit substrate described in Item 14:; the conductive layer, the first layer of the outer metal layer, the second outer layer, and the An intermediate metal layer between the outer metal layer and the second outer reed, in the case of the composite, the composite conductor Η' /, VA from the metal layer, and in the patterning and the intermediate gold layer i. , patterning the second outer metal layer method, i bis, the production of the circuit substrate described in item 14 After the bonding of the core layer and the core layer, the emulsion layer is on the portion of the first bump that is exposed by the solder mask layer. 'Several methods, witnessing the production of the welding sleeve After the formation of It f, it further includes forming a sacrificial film to expose the top surface of the (four)-bump on the film system. The film of the circuit substrate described in the patent scope of the patent: 17 After the layer is bonded to the private layer, the removal of the sacrificial layer is performed to cause the bump to protrude from the solder mask layer. 23 126 V 96^?8twf d〇c/s 19. The method of manufacturing the circuit substrate of claim 14, wherein the bonding layer and the core layer further comprise removing a portion of the first bump to recess the first bump in the solder mask layer. The chip package structure comprises: a circuit substrate comprising: a core layer having at least one conductive structure extending through the core layer; and a stacked layer disposed on the core layer, the laminated layer comprising: a dielectric layer disposed on the core layer; a circuit layer disposed on the core layer, and Located in the first dielectric layer, wherein the circuit layer includes a first conductor layer connected to the core layer and a second conductor layer on the first conductor layer; a solder mask layer disposed on the first layer And the at least one first bump is disposed on the first dielectric layer and located in the solder mask layer, wherein the first bump is electrically connected to the circuit layer, and the solder mask The layer is exposed to the top surface of the first bump; and a wafer is disposed on the circuit substrate and electrically connected to the circuit substrate. The chip package structure according to claim 20, wherein The core layer includes: a second dielectric layer having a corresponding first surface and a second surface; and at least one conductive block disposed in the second dielectric layer, the conductive block including a second bump a third bump and a metal layer, and the metal layer 24 126 V969778twf.doc/g is disposed between the second bump and the third bump. The wafer package structure of claim 21, wherein the material of the second bump comprises copper. 23. The chip package structure of claim 21, wherein the material of the third bump comprises copper. 24. The wafer package structure of claim 21, wherein the material of the metal layer comprises a recording. The wafer package structure of claim 20, wherein the material of the first conductor layer comprises copper. 26. The chip package structure of claim 20, wherein the material of the second conductor layer comprises nickel. 27. The chip package structure of claim 20, wherein the material of the first bump comprises copper. 28. The chip package structure of claim 20, further comprising an anti-oxidation layer disposed on a portion of the first bump exposed by the solder mask layer. The wafer package structure of claim 28, wherein the oxidation resistant layer comprises a nickel/gold layer. The wafer package structure of claim 20, wherein the first bump protrudes from a surface of the solder mask layer. The wafer package structure of claim 20, wherein the first bump is recessed on a surface of the solder mask layer. The wafer package structure of claim 20, wherein the surface of the first bump is aligned with the surface of the solder mask layer. The wafer package structure of claim 20, wherein the wafer is electrically connected to the circuit substrate by a wire bonding technique. 34. The wafer package structure of claim 20, wherein the wafer is electrically connected to the wiring substrate by a flip chip bonding technique. 26