TWI297831B - Method for managing a memory device, computer system and computer-readable medium - Google Patents

Method for managing a memory device, computer system and computer-readable medium Download PDF

Info

Publication number
TWI297831B
TWI297831B TW093103219A TW93103219A TWI297831B TW I297831 B TWI297831 B TW I297831B TW 093103219 A TW093103219 A TW 093103219A TW 93103219 A TW93103219 A TW 93103219A TW I297831 B TWI297831 B TW I297831B
Authority
TW
Taiwan
Prior art keywords
memory
access
content
client
protected
Prior art date
Application number
TW093103219A
Other languages
English (en)
Chinese (zh)
Other versions
TW200426588A (en
Inventor
Debendra Das Sharma
Robert Safranek
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of TW200426588A publication Critical patent/TW200426588A/zh
Application granted granted Critical
Publication of TWI297831B publication Critical patent/TWI297831B/zh

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/14—Protection against unauthorised use of memory or access to memory
    • G06F12/1416—Protection against unauthorised use of memory or access to memory by checking the object accessibility, e.g. type of access defined by the memory independently of subject rights
    • G06F12/1425—Protection against unauthorised use of memory or access to memory by checking the object accessibility, e.g. type of access defined by the memory independently of subject rights the protection being physical, e.g. cell, word, block
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/14—Protection against unauthorised use of memory or access to memory
    • G06F12/1416—Protection against unauthorised use of memory or access to memory by checking the object accessibility, e.g. type of access defined by the memory independently of subject rights
    • G06F12/1425—Protection against unauthorised use of memory or access to memory by checking the object accessibility, e.g. type of access defined by the memory independently of subject rights the protection being physical, e.g. cell, word, block
    • G06F12/1441—Protection against unauthorised use of memory or access to memory by checking the object accessibility, e.g. type of access defined by the memory independently of subject rights the protection being physical, e.g. cell, word, block for a range
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/14—Protection against unauthorised use of memory or access to memory
    • G06F12/1416—Protection against unauthorised use of memory or access to memory by checking the object accessibility, e.g. type of access defined by the memory independently of subject rights
    • G06F12/145—Protection against unauthorised use of memory or access to memory by checking the object accessibility, e.g. type of access defined by the memory independently of subject rights the protection being virtual, e.g. for virtual blocks or segments before a translation mechanism

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Security & Cryptography (AREA)
  • Storage Device Security (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
TW093103219A 2003-03-31 2004-02-11 Method for managing a memory device, computer system and computer-readable medium TWI297831B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US10/404,881 US7296127B2 (en) 2003-03-31 2003-03-31 NoDMA cache

Publications (2)

Publication Number Publication Date
TW200426588A TW200426588A (en) 2004-12-01
TWI297831B true TWI297831B (en) 2008-06-11

Family

ID=32990210

Family Applications (1)

Application Number Title Priority Date Filing Date
TW093103219A TWI297831B (en) 2003-03-31 2004-02-11 Method for managing a memory device, computer system and computer-readable medium

Country Status (7)

Country Link
US (3) US7296127B2 (enExample)
EP (2) EP2287744A1 (enExample)
JP (1) JP4430624B2 (enExample)
KR (1) KR100831468B1 (enExample)
CN (1) CN1291329C (enExample)
TW (1) TWI297831B (enExample)
WO (1) WO2004095205A2 (enExample)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI421701B (zh) * 2010-12-06 2014-01-01 Inventec Corp 計算機系統
US8677182B2 (en) 2010-11-19 2014-03-18 Inventec Corporation Computer system capable of generating an internal error reset signal according to a catastrophic error signal

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7296127B2 (en) 2003-03-31 2007-11-13 Intel Corporation NoDMA cache
US20050182862A1 (en) * 2004-02-12 2005-08-18 Ritz Andrew J. System and method for detecting DMA-generated memory corruption in a PCI express bus system
CN100418074C (zh) * 2004-03-05 2008-09-10 菲尼萨公司 光学收发机中的分级和字节可配置存储器
US20070078879A1 (en) * 2005-09-30 2007-04-05 Safranek Robert J Active address table
US7594042B2 (en) * 2006-06-30 2009-09-22 Intel Corporation Effective caching mechanism with comparator coupled to programmable registers to store plurality of thresholds in order to determine when to throttle memory requests
US8782367B2 (en) * 2006-12-20 2014-07-15 Stmicroelectronics S.A. Memory area protection circuit
US8041912B2 (en) 2007-09-28 2011-10-18 Macronix International Co., Ltd. Memory devices with data protection
US7907432B2 (en) * 2009-06-30 2011-03-15 Netlogic Microsystems, Inc. Content addressable memory device for simultaneously searching multiple flows
US8898417B1 (en) 2009-10-20 2014-11-25 Micron Technology, Inc. Block-based storage device with a memory-mapped interface
US8572440B1 (en) * 2010-11-15 2013-10-29 E.Digital Corporation System and method for managing information stored in semiconductors
JP5790043B2 (ja) * 2011-03-14 2015-10-07 株式会社リコー データ転送システム及びデータ転送方法
US9471514B1 (en) * 2012-08-23 2016-10-18 Palo Alto Networks, Inc. Mitigation of cyber attacks by pointer obfuscation
US20160034404A1 (en) * 2014-07-31 2016-02-04 International Business Machines Corporation Managing access to storage
US12301561B2 (en) 2022-08-29 2025-05-13 Bank Of America Corporation Secure access to devices in a virtual environment using security tokens

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5134700A (en) * 1987-09-18 1992-07-28 General Instrument Corporation Microcomputer with internal ram security during external program mode
US5079737A (en) * 1988-10-25 1992-01-07 United Technologies Corporation Memory management unit for the MIL-STD 1750 bus
US5251304A (en) * 1990-09-28 1993-10-05 Motorola, Inc. Integrated circuit microcontroller with on-chip memory and external bus interface and programmable mechanism for securing the contents of on-chip memory
US5628023A (en) 1993-04-19 1997-05-06 International Business Machines Corporation Virtual storage computer system having methods and apparatus for providing token-controlled access to protected pages of memory via a token-accessible view
FR2725537B1 (fr) 1994-10-11 1996-11-22 Bull Cp8 Procede de chargement d'une zone memoire protegee d'un dispositif de traitement de l'information et dispositif associe
US5646890A (en) * 1996-03-29 1997-07-08 Aplus Integrated Circuits, Inc. Flexible byte-erase flash memory and decoder
US5809546A (en) * 1996-05-23 1998-09-15 International Business Machines Corporation Method for managing I/O buffers in shared storage by structuring buffer table having entries including storage keys for controlling accesses to the buffers
JP2916421B2 (ja) 1996-09-09 1999-07-05 株式会社東芝 キャッシュフラッシュ装置およびデータ処理方法
US5930826A (en) * 1997-04-07 1999-07-27 Aplus Integrated Circuits, Inc. Flash memory protection attribute status bits held in a flash memory array
US6473861B1 (en) * 1998-12-03 2002-10-29 Joseph Forte Magnetic optical encryption/decryption disk drive arrangement
US6412043B1 (en) 1999-10-01 2002-06-25 Hitachi, Ltd. Microprocessor having improved memory management unit and cache memory
JP4719957B2 (ja) * 2000-05-24 2011-07-06 株式会社日立製作所 記憶制御装置及び記憶システム並びに記憶システムのセキュリティ設定方法
JP4678084B2 (ja) 2000-09-29 2011-04-27 ソニー株式会社 メモリ装置およびメモリアクセス制限方法
JP3644494B2 (ja) 2001-04-13 2005-04-27 日本電気株式会社 情報検索装置
US7130951B1 (en) * 2002-04-18 2006-10-31 Advanced Micro Devices, Inc. Method for selectively disabling interrupts on a secure execution mode-capable processor
US6785790B1 (en) * 2002-05-29 2004-08-31 Advanced Micro Devices, Inc. Method and apparatus for storing and retrieving security attributes
US7296127B2 (en) 2003-03-31 2007-11-13 Intel Corporation NoDMA cache
US7146477B1 (en) * 2003-04-18 2006-12-05 Advanced Micro Devices, Inc. Mechanism for selectively blocking peripheral device accesses to system memory
US7665143B2 (en) * 2005-05-16 2010-02-16 Microsoft Corporation Creating secure process objects

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8677182B2 (en) 2010-11-19 2014-03-18 Inventec Corporation Computer system capable of generating an internal error reset signal according to a catastrophic error signal
TWI421701B (zh) * 2010-12-06 2014-01-01 Inventec Corp 計算機系統

Also Published As

Publication number Publication date
US20080040566A1 (en) 2008-02-14
HK1069450A1 (en) 2005-05-20
EP2287744A1 (en) 2011-02-23
WO2004095205A2 (en) 2004-11-04
US7571294B2 (en) 2009-08-04
EP1609069A2 (en) 2005-12-28
KR20060006791A (ko) 2006-01-19
US7296127B2 (en) 2007-11-13
CN1291329C (zh) 2006-12-20
US20040193755A1 (en) 2004-09-30
JP2006514770A (ja) 2006-05-11
WO2004095205A3 (en) 2004-12-29
TW200426588A (en) 2004-12-01
KR100831468B1 (ko) 2008-05-21
CN1534492A (zh) 2004-10-06
JP4430624B2 (ja) 2010-03-10
US20090292879A1 (en) 2009-11-26
EP1609069B1 (en) 2017-08-16

Similar Documents

Publication Publication Date Title
US7571294B2 (en) NoDMA cache
US7139890B2 (en) Methods and arrangements to interface memory
US6360282B1 (en) Protected control of devices by user applications in multiprogramming environments
JP5068108B2 (ja) メモリ・アドレスの変換およびピン止めのための方法およびシステム
US20210089678A1 (en) Built-in legal framework file management
CN108027779A (zh) 允许受保护的容器存储器与输入/输出设备之间的安全通信的处理器、方法、系统和指令
US20060112267A1 (en) Trusted platform storage controller
US11940927B2 (en) Technologies for memory tagging
US11106813B2 (en) Credentials for consent based file access
US7454787B2 (en) Secure direct memory access through system controllers and similar hardware devices
US11188477B2 (en) Page protection layer
CN109582603B (zh) 用于向共享虚拟存储器提供访问保护的技术
US7246213B2 (en) Data address security device and method
US11188680B2 (en) Creating research study corpus
US7430649B2 (en) Input/output device, computer, computer system, input/output control program, OS, page management program, and page management method
JP6257844B2 (ja) 実行制御装置及び実行制御方法及び実行制御プログラム
CN117592131A (zh) 半导体装置的数据标识辨识
HK1069450B (en) An apparatus and method for accessing memory

Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees