doc/g I297々62tQf 九、發明說明： 【發明所屬之技術領域】 本發明是有關於一種積體電路元件及其製造方法，且 特別是有關於一種半導體元件及其製造方法。 【先前技術】 在積體電路元件的發展過程中，藉由縮小元件的尺寸 可達到高速操作和低耗電量的目的。然而，由於目前縮小 元件尺寸的技術遭受到製程技術瓶頸、成本昂貴等因素的 限制’所以需發展其他不同於縮小元件的技術，以改善元 件的驅動電流。因此，有人提出利用應力（stress)控制的方 式’來克服元件縮小化的極限。 習知一種利用應力控制方式增加元件效能的方法 是^依照元件為N型或P型來選擇在基底上形成可當作接 觸囪 I虫刻中止層（contact etching st〇p iayer，cesL)的一層 回張力(tensile)或高壓縮(compression)的氮化石夕層，以提高 元件的驅動電流。 然而，利用應力層以提高元件效能之方法，仍然會存 在有一些問題。一般而言，於P型元件上形成一層壓縮應 (mpressive stress)層’可提南元件的電流增益(current gain)以及元件效能。但是，對一些p型元件而言，其會使 元件的可罪度(reliability)產生退化(degradation)。舉例來 說，於輸出輪入(I/O)的P型金氧半電晶體上形成一層壓縮 應力層，會出現臨界電壓(threshold voltage，Vt)漂移(shift) 、 象而造成使負偏壓溫度效應（negative bias ，丨g I297m〇c, temperature instability，NBTI)產生退化，進而降低電流增 益，以及影響元件的效能。 【發明内容】 有鑑於此’本發明的目的就是在提供一種半導體元件 的製造方法，能夠避免負偏壓溫度效應產生退化，電流增 益降低，進而影響元件的效能。 ”曰 本發明的另一目的是提供一種半導體元件，能夠避免 因負偏壓溫度效應產生退化而衍生的問題，且可提高元件 的效能。 本發明提出一種半導體元件的製造方法，首先提供一 ，底’此基底上已形成有第—型金氧半電晶體、輸出輸入 弟-型金氧半電晶體以及核心第二型金氧半電晶體。然 後，形成第一應力層，以覆蓋住基底、第一型金氧半電晶 體、輸出輸人第二型金氧半電日日日體與核心第二型金氣丰: °接著’至少移除核心第二型金氧半 f力層’以至少保留第—型金氧半電晶體上之第2力 曰n’rr第二型金氧半電晶體上形成第二應力層。 廍六：叙明的較佳實施例所述，更包括於形成有第-r層之輪出輸入第二型金氧半電晶體上，形成=;力 晶趙==佳實施例所述’上述第-型金氧半電 -岸力岸+電晶體為'型金氧半電晶體，則第 U 9為拉伸應力層，第二應力層為壓縮應力層。 電曰俨明的較佳實施例所述，上述之第一型金氧半 晶體與核心第=晶體，而輸出輸人第二型金氧半電 第一庭 金氧半電晶體為Ν型金氧半電晶體，則 ^昭曰為壓縮應力層，第二應力層為拉伸應力層。 姑所仓丨i、本♦月的較佳實施例所述’上述之第一應力層的 材貝例如是氮化矽。 材質較佳實施例所述，上述之第二應力層的 層以提出―種半導體元件，包括基底、第一應力 半電曰力層。其中，此基底上已形成有第一型金氧 入=-、輪出輪入第二型金氧半電晶體以及核心第二型 i iL半電晶。黎 上，或#一 t入^ 應力層配置於第一型金氧半電晶體 體上二型金氧半電晶體與輸出輸入第二型金氧半電晶 應力層配置於核心第二型金氧半電晶體上。 應力層佳實施例所述，更包括於覆蓋有第— 力層。 輪入弟二型金氧半電晶體上，配置有第二應 晶體:以::圭實施例所述，上述第-型金氧半電 體與核心第人電晶體，錢4輪人第二型金氧半電晶 -應力層為拉伸電:!體型金氧半電晶體’則第 依γ太级㈢，弟一應力層為壓縮應力層。 電晶體:心上述之第-型金氧半 晶體舆核心第二上曰:f而輪出輸入第二型金氧半電 支至乳半电晶體為N型金氧半電晶體，則 1297¾oc/g 弟=力刀層為墨縮應力層，第二應力層為拉伸應力層。 照本發明的較佳實施例所述，上述之第一岸力声的 材質例如是氮切。 Μ力層的 本發明的較佳實施例所述，上述之第二應力層的 材貝例如是氮化矽。 声拉ί發明是於輸出輸人第二型金氧半電晶體上形成一 "申應力層、一層拉伸應力層與一層壓縮應力層，或者 $不:成任何應力層。因此，可使得在基底施加負偏壓時， 不^累積在閘介電層中，因此不會有臨界電壓(thresh〇ld V^age ’ Vt)漂移(shift)的現象，亦即是不會有習知的負偏 疋恤度效應(negative bias temperature instability，NBTI)產 生退=之問題。另一方面，本發明之方法亦不會增加製程 中所萬之光罩數目，因此並不會額外增加製程成本。 ▲為瓖本發明之上述和其他目的、特徵和優點能更明顯 易It，下文特舉較佳實施例，並配合所附圖式，作詳細說 明如下。 ' 【實施方式】 圖1A至圖id為依照本發明一實施例所緣示之半導 體元件的製造方法之剖面示意圖。 首先，請參照圖1A，提供一基底1〇〇。基底1〇〇上已 形成有第一型金氧半電晶體102、輪出輸入第二型金氧半 電晶體104以及核心第二型金氧半電晶體1〇6。上述，第 一型金氧半電晶體102、輸出輸入第二型金氧半電晶體1〇4 以及核心第二型金氧半電晶體106之間是以隔離結構1〇8 1297520 rf_doc/g 區隔。在此，隔離結構1〇8例如是淺溝渠隔離結構。 上述，輪出輸入第二型金氧半電晶體1〇4為輸出輪 (I/O)金^半電晶體，核心第二型金氧半電晶體1〇6為核心 (:〇re)孟氧半電晶體。其中，第一型金氧半電晶體搬例如 疋N型金氧半電晶體，而輸出輸入第二型金氧半電晶體 1 曰〇4與核心第二型金氧半電晶體1〇6例如是p型金氧半電 晶體。而上述之第一型金氧半電晶體102是由閘介電層 l〇2a、多晶矽層102b、源極/没極區1〇2c與間隙壁〖ο% 所構成。輸出輸入第二型金氧半電晶體104是由閘介電層 l〇4a、多晶矽層i〇4b、源極/没極區104c與間隙壁1〇4^ 所構成。核心第二型金氧半電晶體1〇6是由閘^電層 106a、多晶矽層l〇6b、源極/汲極區106c與間隙壁丨06d 所構成。 在一實施例中，可於多晶矽層l〇2b、i〇4b、i〇6b以 及源極/汲極區l〇2c、104c、106c上形成金屬矽化物層（未 繪示）用以降低阻值，而金屬矽化物層的材質例如是矽化 鎳、石夕化鶴或石夕化钻等。在另一實施例中，視製程之需要， 還可在多晶矽層102b、104b、106b的侧壁處形成一 ^化石夕 間隙壁(未繪示）。 上述，第一型金氧半電晶體102、輪出輸入第二型金 氧半電晶體104以及核心第二型金氧半電晶體1〇6各構件 的材質與形成方法，是於此技術領域中具有通常知識者所 周知，於此不再贅述。 接著，請參照圖1B，於基底1〇〇上方形成第一應力 12975¾.^ 覆ί住基底J00、第—型金氧半金氧半電晶體 =輸入第二型金氧半金氧半電晶體刚與核心第二 金f半電晶體廳。在此，第—應力層no μ ί ress)層，其材質例如是氮秘或其他合適 他合壯是賴增触學氣相沈積法或其 接著，請參照圖lc，移除核心第二型金氧半電晶體 ^第一應力層m，以形成第一應力層咖。上述， =核=二型金氧半電晶體⑽上之第—應力層n =法例如疋’於第-應力層110上形成一圖案化光阻層(未 、’不）’以曝露出核心第二型金氧半電晶體1〇6上 力層110 ’錢再進行-爛製程，移除 = 層所覆蓋之第-應力層m，以形成第—應力層先阻 繼之，請參照圖1D，於核心第二型金氧半電晶體106 :成第二應力層，此，第二應力層 力(comp腦vest臟)層，其材_如是氮 之介電層。第二應力層112的形成方法例如是， 力層11G以及核Ά二型金氧半電晶體1%上，將辦 強化人學氣滅積法或其他合適之方法形成—層應力材= (未繪:）。織’於此應力材料層上形成—圖案化光阻層 (未繪示），以曝露出第-型金氧半電晶體1〇2 二 第二型金氧半電晶巧104上之第一應力層11〇，二、接著:』以 圖案化光阻層為罩幕’進行-烟製程，移除第_應力声 no’上方之應力材料層，以形成第二應力層112。〜曰 12975s^i^f-d〇c/g 由上述可知，本發明是於輸出輸入第二型金氧半電晶 體(即輸出輸入金氧半電晶體)上形成_層拉伸應力層，因 此於基底施加負偏壓時，則應力層中# Si_H鍵會斷開， Η可經由拉伸應力層穿出，而不會累積在閘介電層中，因 此不會有臨界電壓(threshold v〇ltage，Vt)漂移(δ_的現 象，亦即是不會有習知的負偏壓溫度效應㈣金— temperature instability，NBTI)產生退化之問題。 &本發明除了上述實施例之外，尚具有其他的實施型 =。圖2為依照本發明另—實施例㈣示之半導體元件的 ^造方法之麻#圖。其中圖2是接續上述實施例之圖 丄c進行，且於圖2中，盥圖1 用相同犧，並省略其；^簡1^目_冓件是使 請參照圖2 ’在上述之第一應力層11〇， 3=二型金Ϊ半電晶體104以及核心第二型金氧 庫=成:一應力層112,。在此，第二應力層 電声為力層，其财勤是氮切或其他合適之介 no曰，以二7 ί層;!!’的形成方法例如是，在第一應力層 υΜ及核心弟二型金氧半電晶體】 、 學氣相沈料料他合紅綠 1 增強化 繪示彳缺从 次小成—層應力材料層（未 /一、）。w後，於此應力材料層上形成—圖案化 :)。’以+曝露出第一型金氧半電晶體102上之第-應曰力声 移除部分應力材料層，·成第二應力^；；；烟製程， 圖3A至圖犯為依照本發明又—實施例崎示之半導 I29752fi wf.doc/g 體兀件的製造方法之剖面示意圖。其中圖3A是接續 上述 實施例之圖1B進行，且於圖3A至圖3B中，與圖ία至 圖1B相同的構件是使用相同的標號，並省略其說明。 斤請參照圖3A，在第一應力層11〇形成之後，移除核 心第二型金氧半電晶體106以及輸出輸入第二型金氧半電 晶體104上之第一應力層110，形成第一應力層110，，。上 述’移除核心第二型金氧半電晶體1〇6以及輸出輸入第二 塑金氧半電晶體1〇4上之第一應力層110的方法例如是， 於弟應力層丨1〇上形成一圖案化光阻層（未繪示），以曝 露出核心第二型金氧半電晶體1〇6以及輸出輸入第二型金 氧半電晶體104上之第一應力層n〇。然後，再進行一蝕 刻製程，移除未被圖案化光阻層所覆蓋之第一應力層 11〇 ’以形成第一應力層11〇，，。 接著，請筝照圖3B，在輸出輸入第二型金氧半電晶 體1〇4以及核心第二型金氧半電晶體1〇6上形成第二應力 層112’’。在此，第二應力層112，，為壓縮應力層，其材質 例如是氮切或其他合適之介電層。第二應力層112,，的形 成方法例如是，在第-應力層11G，，、輸出輸入第二型金氧 半电晶體104以及核心第二型金氧半電晶體1〇6上，以電 2增強化學氣相沈積法或其他合適之方法形成—層應力材 未緣不）。然後’於此應力材料層上形成一圖案化光 未緣示），以曝露出第-應力層11〇”以及輸出輸入第 :型金氧半電晶體1〇4。接著，以圖案化光阻層為罩幕， 違行-_製程，移除部分應力材料層，以形成第二應力 12 doc/g I29752fiiwf. 層 112，，。 同樣地，本發明是在輸出輸入第二型金氧半電晶體(即 輸出輸入金氧半電晶體)上形成一層拉伸應力層與一層壓 縮應力層，或者是不形成任何應力層，因此在基底施加負 偏壓時，則H+不會累積在閘介電層中，所以不會有臨界電 壓漂移的現象，也就是說不會造成習知的負偏壓溫度效應 產生退化之問題。 在上述實施例中，是以第一型金氧半電晶體102為N 型金氧半電晶體，輸出輸入第二型金氧半電晶體104與核 心第二型金氧半電晶體106為P型金氧半電晶體，而第一 應力層110、110’、110’’為拉伸應力層，第二應力層112、 112、112’’為壓縮應力層，為例做說明，然本發明並不限 定於此。當然，在另一實施例中，本發明之第一型金氧半 電晶體102可為p蜜金氧半電晶體，輸出輸入第二型金氧 半電晶體104與核心第二型金氧半電晶體106為N型金氧 半電晶體，而第一應力層110、110,、110，，為壓縮應力層， 弟一應力層112、112’、112’’為拉伸應力層。 以下是說明利用本發明之半導體元件的製造方法所 得到之半導體元件。 請再次參照圖1D，本發明之半導體元件包括基底 100、第一應力層110,以及第二應力層112。其中，基底 漏上,已形成有第一裂金氧半電晶體102、輸出輸入第二型 至氧半電日日體104以及核心第二型金氧半電晶體撕。第 -應力層110,配置於第一型金氧半電晶體1〇2以及輸出輪 13Doc/g I297々62tQf IX. Description of the Invention: TECHNICAL FIELD The present invention relates to an integrated circuit component and a method of fabricating the same, and more particularly to a semiconductor component and a method of fabricating the same. [Prior Art] In the development of integrated circuit components, high-speed operation and low power consumption can be achieved by reducing the size of components. However, since the current technology for reducing the size of components suffers from process bottlenecks and expensive costs, it is necessary to develop other techniques than the reduced components to improve the driving current of the components. Therefore, it has been proposed to overcome the limit of component miniaturization by using the method of stress control. A method for increasing the performance of a component by using a stress control method is to select a layer on the substrate that can be used as a contact etching st〇p iayer (cesL) according to whether the component is N-type or P-type. A tensile or high compression nitride layer is added to increase the drive current of the component. However, there are still some problems with the use of stress layers to improve component performance. In general, a layer of mpressive stress is formed on the P-type component to increase the current gain and component performance of the south component. However, for some p-type components, it can degrade the component's reliability. For example, a compressive stress layer is formed on a P-type MOS transistor of an output wheel (I/O), and a threshold voltage (Vt) shift occurs, causing a negative bias. The negative bias (丨g I297m〇c, temperature instability, NBTI) produces degradation, which in turn reduces current gain and affects component performance. SUMMARY OF THE INVENTION In view of the above, an object of the present invention is to provide a method for fabricating a semiconductor device which can avoid degradation of a negative bias temperature effect and a decrease in current gain, thereby affecting the performance of the device. Another object of the present invention is to provide a semiconductor device capable of avoiding problems caused by degradation of a negative bias temperature effect and improving the performance of the device. The present invention provides a method for fabricating a semiconductor device, first providing one. A first-type gold-oxygen semi-transistor, an output input-type MOS transistor, and a core second-type oxy-oxygen transistor are formed on the substrate. Then, a first stress layer is formed to cover the substrate. The first type of gold-oxygen semi-transistor, the output of the second type of gold-oxygen semi-electrical day and the day and the core of the second type of gold gas: ° then 'at least remove the core type 2 gold-oxygen half-force layer' Forming a second stressor layer on at least the second force 曰n'rr type 2 oxynitride semiconductor on the first type of MOS transistor. 廍6: as described in the preferred embodiment, including Formed on the second type of gold-oxygen semi-transistor formed on the wheel of the first-r layer, forming a == force crystal Zhao == the above-mentioned first-type gold-oxygen semi-electro-banking shore + transistor For a 'type gold oxide semi-transistor, the U 9 is a tensile stress layer, and the second stress layer is Compressive stress layer. According to a preferred embodiment of the invention, the first type of gold oxide half crystal and the core type = crystal, and the output of the second type of gold oxide semi-electric first chamber metal oxide semi-transistor In the case of a bismuth-type gold-oxygen semi-transistor, the first stress layer is a compressive stress layer, and the second stress layer is a tensile stress layer. The first stress described above is described in the preferred embodiment of the present invention. The material of the layer is, for example, tantalum nitride. According to a preferred embodiment of the material, the layer of the second stress layer is provided to provide a semiconductor element, including a substrate, a first stress semi-electrode force layer, wherein the substrate is on the substrate. Formed with a first type of gold oxygen in--, a wheel-out wheel into the second type of gold-oxygen semi-transistor and a core second-type i iL semi-electrode. Li Shang, or #一t into ^ stress layer is arranged in the first The type of gold oxide semi-electrode on the body of the second type of gold oxide semi-transistor and the input and output of the second type of gold oxide semi-electrode stress layer are disposed on the core type 2 metal oxide semi-transistor. The stress layer is better described in the embodiment, Included in the cover of the first force layer. On the wheel of the second type of metal oxide semi-transistor, equipped with a second crystal: to: According to the embodiment, the first type of gold-oxygen semi-electric body and the core first-person crystal, the money of 4 rounds of the second type of gold-oxygen semi-electron-stress layer is a tensile electricity: ! body type gold oxide semi-transistor' According to the γ-class (3), the stress layer of the brother is the compressive stress layer. The transistor: the first type-type MOS-semi-crystal 舆 core, the second upper 曰:f and the second type of gold-oxygen semi-electrical branch The milk semi-transistor is an N-type oxy-oxygen semi-transistor, and the 12973⁄4 oc/g brother = force blade layer is an ink shrinkage stress layer, and the second stress layer is a tensile stress layer. According to a preferred embodiment of the present invention, the above The material of the first shore force sound is, for example, a nitrogen cut. In the preferred embodiment of the present invention, the material of the second stress layer is, for example, tantalum nitride. The sound pull is in the output. A second type of metal oxide semi-transistor forms a "stress layer, a layer of tensile stress and a layer of compressive stress, or $not: into any stress layer. Therefore, when a negative bias is applied to the substrate, it does not accumulate in the gate dielectric layer, so there is no threshold voltage (thresh〇ld V^age 'Vt) shift, that is, it does not There is a known problem of negative bias temperature instability (NBTI). On the other hand, the method of the present invention does not increase the number of masks in the process, and therefore does not add additional process costs. The above and other objects, features, and advantages of the present invention will become more apparent from the aspects of the appended claims. [Embodiment] Figs. 1A to 1D are schematic cross-sectional views showing a method of manufacturing a semiconductor device according to an embodiment of the present invention. First, referring to FIG. 1A, a substrate 1 is provided. A first type of MOS transistor 102, a wheel input second type MOS transistor 104, and a core type 2 MOS transistor 1 〇 6 have been formed on the substrate 1 . In the above, the first type of MOS transistor 102, the input and output type 2 MOS transistor 1〇4, and the core type 2 MOS transistor 106 are isolated structures 1〇8 1297520 rf_doc/g area Separate. Here, the isolation structure 1〇8 is, for example, a shallow trench isolation structure. In the above, the second type of gold oxide semi-transistor 1〇4 is the output wheel (I/O) gold ^ semi-transistor, and the core second type gold-oxide semi-transistor 1〇6 is the core (: 〇re) Meng Oxygen semi-transistor. Wherein, the first type of MOS transistor is, for example, a 疋N-type MOS transistor, and the output is input to the second type MOS transistor 1 曰〇4 and the core type 2 MOS transistor 1〇6, for example It is a p-type gold oxide semi-electrode. The first type of MOS transistor 102 is composed of a gate dielectric layer 〇2a, a polysilicon layer 102b, a source/no-polar region 1〇2c, and a spacer ο%. The output input second type MOS transistor 104 is composed of a gate dielectric layer 104a, a polysilicon layer i〇4b, a source/nomogram region 104c, and a spacer 1〇4^. The core second type MOS transistor 1 〇 6 is composed of a gate electrode layer 106a, a polysilicon layer 106b, a source/drain region 106c, and a spacer 丨 06d. In one embodiment, a metal telluride layer (not shown) may be formed on the polysilicon layers l〇2b, i〇4b, i〇6b and the source/drain regions l〇2c, 104c, 106c to reduce the resistance. The material of the metal telluride layer is, for example, a nickel telluride, a shixihua crane or a shixi chemical drill. In another embodiment, a fossil spacer (not shown) may be formed at the sidewalls of the polysilicon layers 102b, 104b, 106b as needed for the process. In the above, the material and formation method of the first type of MOS transistor 102, the wheel input and output type 2 MOS transistor 104, and the core type 2 MOS transistor 1 〇6 are in the technical field. Those of ordinary knowledge are well known and will not be described here. Next, referring to FIG. 1B, a first stress 129753⁄4 is formed over the substrate 1〇〇. 基底 基底 基底 基底 基底 00 00 基底 基底 基底 00 = = = = = = = = = = = = = = = = = = = = = = = = = = = = = Just with the core second gold f semi-transistor hall. Here, the first layer of the stress layer no μ ί ress, the material of which is, for example, nitrogen secret or other suitable Hehe Zhuang is the Lai Zeng touch vapor deposition method or its subsequent, please refer to Figure lc, remove the core type II The gold oxide semi-electrode ^ first stress layer m to form a first stress layer. In the above, the n-core = di-type MOS semi-transistor (10)-the stress layer n = method, for example, 疋' forms a patterned photoresist layer (not, 'no') on the first-stress layer 110 to expose the core The second type of gold oxide semi-transistor 1〇6 upper force layer 110 'money re-running process, remove = the first layer of stress layer covered by the layer to form the first stress layer first, please refer to the figure 1D, in the core second type of gold oxide semi-transistor 106: into a second stress layer, this second stress layer force (comp brain vest dirty layer), the material - such as a dielectric layer of nitrogen. The method for forming the second stress layer 112 is, for example, a force layer 11G and a core-type bismuth oxynitride 1%, which will be formed by a reinforced gas annihilation method or other suitable method to form a layer stress material = (not painted:). Forming a patterned photoresist layer (not shown) on the layer of stressor material to expose the first type of gold-oxygen semi-transistor 1〇2 The stress layer 11 〇, 2, and then: "with the patterned photoresist layer as a mask" to perform a smoke process, removing the stress material layer above the first stress sound no' to form a second stress layer 112. ~曰12975s^i^fd〇c/g As can be seen from the above, the present invention forms a _ layer tensile stress layer on the output type input and output of the second type of gold oxide semi-transistor (i.e., output and output gold oxide semi-transistor). When a negative bias is applied to the substrate, the #Si_H bond in the stress layer is broken, and the germanium can pass through the tensile stress layer without accumulating in the gate dielectric layer, so there is no threshold voltage (threshold v〇ltage , Vt) drift (δ_ phenomenon, that is, there is no known negative bias temperature effect (4) gold-temperature instability (NBTI) produces degradation. & The present invention has other embodiments in addition to the above embodiments. Fig. 2 is a view showing a method of fabricating a semiconductor device according to another embodiment (4) of the present invention. 2 is continued from the above embodiment ,c, and in FIG. 2, FIG. 1 uses the same sacrifice, and omits it; ^1 _ _ 是 是 是 请 请 请 请 请 请 ' ' ' A stress layer 11 〇, 3 = a two-type metal Ϊ semi-transistor 104 and a core second-type MOS memory = a stress layer 112. Here, the second stress layer electroacoustic is a force layer, and its financial operation is nitrogen cutting or other suitable n曰, to form a layer of two layers; for example, the first stress layer and the core Di 2 type gold oxide semi-transistor], learning the vapor phase sink material hehe red green 1 enhanced depiction of the lack of sub-small-layer stress material layer (not / one,). After w, the stress material layer is formed - patterned :). 'excepting the first type of gold-oxygen semi-transistor 102 to expose a portion of the stress material layer to a second stress ^;;; smoke process, FIG. 3A to FIG. 3A Further, the semi-conductive I29752fi wf.doc/g of the embodiment shows a schematic cross-sectional view of the manufacturing method of the body member. 3A is the same as FIG. 1B of the above embodiment, and in FIG. 3A to FIG. 3B, the same members as those of FIG. 1A to FIG. 1B are denoted by the same reference numerals, and the description thereof will be omitted. Referring to FIG. 3A, after the first stress layer 11 is formed, the core second type MOS transistor 106 and the first stress layer 110 outputted to the second type MOS transistor 104 are removed to form a first a stress layer 110,. The above method of removing the core second type MOS transistor 1 〇 6 and outputting the first stress layer 110 on the second MOS transistor 1 〇 4 is, for example, on the stress layer 丨1〇 A patterned photoresist layer (not shown) is formed to expose the core second type MOS transistor 1 〇 6 and the first stress layer n 输出 outputted to the second MOS transistor 104. Then, an etching process is performed to remove the first stressor layer 11'' which is not covered by the patterned photoresist layer to form the first stressor layer 11'. Next, in accordance with Fig. 3B, a second stressor layer 112'' is formed on the output and input of the second type of oxy-oxygen semiconductor body 〇4 and the core type 2 oxy-oxygen semiconductor transistor 〇6. Here, the second stressor layer 112 is a compressive stress layer made of, for example, a nitrogen cut or other suitable dielectric layer. The second stress layer 112 is formed, for example, on the first stress layer 11G, the output input second type MOS transistor 104, and the core second type MOS transistor 1 〇6. 2 enhanced chemical vapor deposition or other suitable method to form - layer stress material. Then, a patterned light is formed on the stress material layer to expose the first stress layer 11 〇 and the output input type MOS transistor 1 〇 4. Next, the photoresist is patterned. The layer is a mask, the process is broken, the partial stress material layer is removed, to form a second stress 12 doc / g I29752 fiiwf. layer 112,. Similarly, the invention is in the output input type 2 gold oxide semi-electric A layer of tensile stress layer and a layer of compressive stress are formed on the crystal (ie, the output input MOS transistor), or no stress layer is formed. Therefore, when a negative bias is applied to the substrate, H+ does not accumulate in the gate dielectric. In the layer, there is no phenomenon of threshold voltage drift, that is, it does not cause the problem of degradation of the conventional negative bias temperature effect. In the above embodiment, the first type of MOS transistor 102 is used. The N-type MOS transistor, the output input second MOS transistor 104 and the core MOS transistor 106 are P-type MOS transistors, and the first stress layer 110, 110', 110 '' is the tensile stress layer, the second stress layer 112, 112, 112' 'The compressive stress layer is described as an example, but the invention is not limited thereto. Of course, in another embodiment, the first type of gold oxide semi-transistor 102 of the present invention may be a p-metal oxide semi-transistor. The second input type MOS transistor 104 and the core type MOS transistor 70 are N-type MOS transistors, and the first stress layers 110, 110, 110 are compressive stress layers. The first stress layer 112, 112', 112'' is a tensile stress layer. The semiconductor element obtained by the method for fabricating the semiconductor device of the present invention will be described below. Referring again to FIG. 1D, the semiconductor device of the present invention includes the substrate 100. a first stressor layer 110, and a second stressor layer 112. wherein the substrate is drained, a first cracked gold oxide half transistor 102, an output input second type to an oxygen half electricity day and a body 104, and a core second are formed. Type MOS thin crystal tear. The first stress layer 110 is disposed on the first type MOS transistor 1 〇 2 and the output wheel 13
1297m,〇〇/g 弟i孟氣半電晶體l〇4上，其材質例如是氮化石夕或其 他合適之介電層。第二應力層112配置於核心第二型金氧 半電晶體106上，其材質例如是氮化矽或其他合適之介電 層。 另外，請再次參照圖2，本發明之半導體元件包括基 底1〇〇、第一應力層110，以及第二應力層112,。其中，^ 底100上已形成有第一型金氧半電晶體102、輪出輸入第 二型金氧半電晶體104以及核心第二型金氧半電晶體 1〇6。第一應力層110,配置於第一型金氧半電晶體= 及輸出輸入第二型金氧半電晶體1()4上，其材質例如是氮 化矽或其他合適之介電層。第二應力層112配置於核心^ 二型金氧半電晶體106上，以及覆蓋有第一應力層ιι〇，之 輸出輸入第二型金氧半電晶體104上，其材質例如是氮化 矽或其他合適之介電層。 ^ 此外，請再次參照圖3B，本發明之半導體元件還包 括基底100、第一應力層U0，，以及第二應力層112，，。其 中，基底100上已形成有第一型金氧半電晶體91〇2、輸/出 輸入第二型金氧半電晶體1〇4以及核心第二型金氧半電晶 體106。第一應力層110”配置於第一型金氧半電晶體^ 上，其材質例如是氮化矽或其他合適之介電層。第二應力 層112’’配置於核心第二型金氧半電晶體1〇6上，其材g例 如是氣化石夕或其他合適之介電層。 為證實本發明之功效，以下是以圖4說明之。圖4為 本發明與習知之半導體元件的應力時間與臨界電壓漂移量 14 I297^a,oc/g 之關係圖。1297m, 〇〇/g 弟 i Mengqi semi-transistor l〇4, the material is, for example, a nitride layer or other suitable dielectric layer. The second stressor layer 112 is disposed on the core second type MOS transistor 106 and is made of, for example, tantalum nitride or other suitable dielectric layer. Further, referring again to Fig. 2, the semiconductor device of the present invention includes a substrate 1 第一, a first stressor layer 110, and a second stressor layer 112. Wherein, the first type MOS transistor 102, the wheel input second MOS transistor 104, and the core second type MOS transistor 1 〇 6 have been formed on the bottom 100. The first stressor layer 110 is disposed on the first type of MOS transistor and the output source of the second type MOS transistor 1 (4), and is made of, for example, tantalum nitride or other suitable dielectric layer. The second stress layer 112 is disposed on the core type MOS transistor 70 and covered with the first stress layer ιι, and the output is input to the second type MOS transistor 104, and the material thereof is, for example, tantalum nitride. Or other suitable dielectric layer. Further, referring again to FIG. 3B, the semiconductor device of the present invention further includes a substrate 100, a first stressor layer U0, and a second stressor layer 112. The first type of gold oxide semiconductor transistor 91?, the input/output input type 2 metal oxide half transistor 1?4, and the core type 2 gold oxide semiconductor layer 106 are formed on the substrate 100. The first stressor layer 110" is disposed on the first type of gold oxide semiconductor transistor, and the material thereof is, for example, tantalum nitride or other suitable dielectric layer. The second stress layer 112'' is disposed in the core type 2 gold oxide half. On the transistor 1〇6, the material g is, for example, a gasified fossil or other suitable dielectric layer. To confirm the efficacy of the present invention, the following is illustrated in Fig. 4. Fig. 4 is a stress of the present invention and a conventional semiconductor device. The relationship between time and threshold voltage drift amount 14 I297^a, oc/g.
一請蒼照圖4，圖中的測試物件分別是，於輸出輸入第 —型金氧半電晶體上形成壓縮應力層之半導體元件（以口 之付號表示）、於輸出輸入第二型金氧半電晶體上形成低應 2層之半導體元件（以♦之符號表示）以及於輸出輸入第二 ，金氧半電晶體上形成拉伸應力層之半導體元件（以△之 符唬表示）。在固定電壓的條件下，對上述之測試物件進行 f力日守間（stress time)對臨界電壓漂移量“vt)的變化之測 量。如圖4所示的應力時間與臨界電壓漂移量之關係圖可 隨著應力時間逐漸增加，於輸出輸人第二型金氧半電 上?成低應力層或拉伸應力層之半導體元件的臨界電 =沐移里皆較於輸出輸入第二型金氧半電晶體上形成壓縮 :力層之半導體元件的臨界賴漂移量少，其結果顯示本 ^明之半導體元件不會造成負偏壓溫度效應產生退化之問Please refer to Figure 4, the test object in the figure is a semiconductor component that forms a compressive stress layer on the output-type MOS transistor (indicated by the sign of the mouth), and the second type of gold is input at the output. A semiconductor element (indicated by ♦) of the lower two layers is formed on the oxygen semiconductor, and a semiconductor element (indicated by Δ) which forms a tensile stress layer on the MOS transistor is formed on the output second. Under the condition of a fixed voltage, the test object is subjected to the measurement of the change of the stress time to the threshold voltage drift amount "vt". The relationship between the stress time and the threshold voltage drift amount is shown in FIG. The graph can be gradually increased with the stress time, and the output voltage is input to the second type of gold oxide semi-electricity. The critical element of the semiconductor component that becomes the low stress layer or the tensile stress layer is compared with the output input type II gold. The formation of compression on the oxygen semiconductor: the critical element of the semiconductor layer has a small amount of drift, and the result shows that the semiconductor element of the present invention does not cause degradation of the negative bias temperature effect.
=所述，本發明之半導體元件及其製造方法，可使 付在基底施加負偏壓時，+ 不會有萨尺雷w 曰累貝在閘介電層中，因此 移的現象’亦即是不會有習知的負偏壓 二==化之問題。另一方面，相對於習知而言， 不會額外增加製程成本。“之衫數目，因此並 雖然本發明已以較佳實施 限定本發明，任钶嘹羽。戈上然其亚非用以 和範_，當可 15 rf.doc/g 範圍當視後附之申請專利範圍所界定者為準。 * 【圖式簡單說明】 • 圖1A至圖1D為依照本發明一實施例所繪示之半導 . 體元件的製造方法之剖面示意圖。 . 圖2為依照本發明另一實施例所繪示之半導體元件的 . 製造方法之剖面示意圖。 圖3A至圖3B為依照本發明又一實施例所繪示之半導 9 體元件的製造方法之剖面示意圖。 ® 圖4為本發明與習知之半導體元件的應力時間與臨界 電壓漂移量之關係圖。 【主要元件符號說明】 100 :基底 102 :第一型金氧半電晶體 102a、104a、106a :閘介電層 102b、104b、106b ··多晶矽層 102c、104c、106c :源極/汲極區 鲁 102d、104d、106d :間隙壁 104 :輸出輸入第二型金氧半電晶體 106 :核心第二型金氧半電晶體 - 108 :隔離結構 110、110’、110” ：第一應力層 .112、112’、112” ··第二應力層 16According to the semiconductor device of the present invention and the method of manufacturing the same, when a negative bias is applied to the substrate, + there is no samurai w 曰 曰 在 in the gate dielectric layer, so the phenomenon of shifting There is no known problem of negative bias two ==. On the other hand, there is no additional process cost relative to the prior art. "The number of shirts, and therefore, although the present invention has been limited to the present invention by a preferred embodiment, Ren Yu Yu. Geshang Ranqi is not used in conjunction with Fan _, when the 15 rf.doc / g range is attached to the application BRIEF DESCRIPTION OF THE DRAWINGS [FIG. 1A to FIG. 1D are schematic cross-sectional views showing a method of manufacturing a semiconductor device according to an embodiment of the present invention. FIG. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 3A to FIG. 3B are schematic cross-sectional views showing a method of fabricating a semiconductor device according to still another embodiment of the present invention. 4 is a relationship diagram between the stress time and the threshold voltage drift amount of the semiconductor device of the present invention. [Main component symbol description] 100: Substrate 102: First type MOS transistor 102a, 104a, 106a: Gate dielectric layer 102b, 104b, 106b · Polycrystalline germanium layer 102c, 104c, 106c: source/drain region Ru 102d, 104d, 106d: spacer 104: output input second type MOS transistor 106: core second type gold oxide Semi-transistor - 108 : isolation structure 110, 11 0', 110": first stress layer .112, 112', 112" · second stress layer 16