JP2011181841A - Method of manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an appropriate method of manufacturing a semiconductor device that integrates a fin-type MIS transistor, a planar-type MIS transistor, and a resistance element. <P>SOLUTION: The method includes steps of: forming a fin 10a; forming a first gate insulating film 14 and a first gate electrode film 15 on side faces of the fin; forming a semiconductor conduction section 16a that surrounds the first gate insulating film and first gate electrode film formed at the fin and on side faces of the fin, and contacts with the first gate electrode film; forming a second gate insulating film 20 and a second gate electrode film 21 on the semiconductor conduction section and in a planar-type MIS transistor forming region and a resistance element forming region; removing the second gate insulating film and the second gate electrode film formed on the semiconductor conduction section and in the resistance element forming region; and forming a semiconductor film for the resistance element on the semiconductor conduction section and in the planar-type MIS transistor forming region and the resistance element forming region. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a semiconductor device.

  As the semiconductor device is miniaturized, the amount of impurities in the channel region of the MIS transistor also decreases. Therefore, the fluctuation of the threshold value between transistors becomes a problem due to the statistical fluctuation of the impurity amount. For such a problem, a fin type MIS transistor having a double gate structure in which the channel region is sandwiched from both sides is attracting attention as a fully depleted transistor that does not depend on the amount of impurities in the channel region.

  However, the fin type MIS transistor has a three-dimensional structure, unlike a normal planar type MIS transistor. Therefore, it is not realistic to configure all circuits with fin-type MIS transistors. In view of this, a hybrid structure using fin-type MIS transistors for circuits that are sensitive to threshold fluctuations, such as SRAM, and using planar-type MIS transistors for other circuits has attracted attention (for example, see Patent Document 1).

  However, in the hybrid structure described above, a work function of a mid gap is required for the fin type MIS transistor, and a work function of a band edge is required for the planar type MIS transistor. Therefore, a very complicated manufacturing process is required to realize a hybrid structure. Considering that the resistance elements are also integrated, it is assumed that more problems will occur.

  Therefore, in a semiconductor device (semiconductor integrated circuit device) in which a fin-type MIS transistor, a planar MIS transistor, and a resistance element are integrated, an accurate manufacturing method is required.

JP 2008-172082 A

  An object of the present invention is to provide an accurate manufacturing method in a semiconductor device in which a fin type MIS transistor, a planar type MIS transistor, and a resistance element are integrated.

  According to one aspect of the present invention, there is provided a method of manufacturing a semiconductor device, including a step of forming a fin portion in a fin-type MIS transistor formation region, a first gate insulating film for a fin-type MIS transistor on the side surface of the fin portion, and a first Forming the gate electrode film, and surrounding the first gate insulating film and the first gate electrode film surrounding the first gate insulating film and the first gate electrode film formed on a side surface of the fin portion and the fin portion. Forming a semiconductor conductive portion; and forming a second gate insulating film and a second gate electrode film for the planar MIS transistor on the semiconductor conductive portion and in the planar MIS transistor formation region and the resistance element formation region. And a step of removing the second gate insulating film and the second gate electrode film formed on the semiconductor conductive portion and in the resistance element forming region. Then, after removing the second gate insulating film and the second gate electrode film, a semiconductor film for a resistive element is formed on the semiconductor conductive portion, and in the planar MIS transistor forming area and the resistive element forming area. A process.

  According to the present invention, it is possible to provide an accurate manufacturing method in a semiconductor device in which a fin type MIS transistor, a planar type MIS transistor, and a resistance element are integrated.

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  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

  1 to 22 are cross-sectional views schematically showing a manufacturing process of a semiconductor device (semiconductor integrated circuit device) according to an embodiment of the present invention. 1 to 11 show a manufacturing process of a planar type MIS transistor forming region and a resistance element forming region, and FIGS. 12 to 22 show a manufacturing process of a fin type MIS transistor forming region. ing. 1 to 11, the left side of the drawing shows a planar MIS transistor formation region, and the right side of the drawing shows a resistance element formation region. 12 to 22, the left side of the drawing shows a cross section perpendicular to the long axis direction of the fin portion, and the right side of the drawing shows a cross section parallel to the long axis direction of the fin portion.

  First, as shown in FIGS. 1 and 12, an element isolation region 11 is formed in a surface region of a single crystal silicon substrate (semiconductor substrate) 10. Subsequently, a sacrificial oxide film 12 is formed on the surface of the silicon substrate 10. Further, a silicon nitride film 13 is formed on the entire surface.

  Next, as shown in FIGS. 2 and 13, the silicon nitride film 13, the sacrificial oxide film 12, and the silicon substrate 10 are patterned in the fin-type MIS transistor formation region. Thereby, the fin portion 10 a is formed in the surface region of the silicon substrate 10. That is, an island-shaped semiconductor portion is formed in the surface region of the silicon substrate 10.

  Next, as shown in FIGS. 3 and 14, a gate insulating film (first gate insulating film) 14 for the fin-type MIS transistor is formed on the entire surface. This gate insulating film 14 is formed by forming a hafnium oxide film on an interface layer containing nitrogen. Subsequently, a gate electrode film (first gate electrode film) 15 for the fin-type MIS transistor is formed on the gate insulating film 14. The gate electrode film 15 is a metal electrode film made of TiN. As a result, a laminated film of the gate insulating film 14 and the gate electrode film 15 is formed on the entire surface including the side surfaces of the fin portion 10a. Further, a silicon film (conductive semiconductor film) 16 is formed on the gate electrode film 15.

  Next, as shown in FIGS. 4 and 15, a planarization process is performed by CMP (chemical mechanical polishing) or etch back. As a result, as shown in FIG. 15, the semiconductor conductive portion 16 a that surrounds the fin portion 10 a and the gate insulating film 14 and the gate electrode film 15 formed on the side surface of the fin portion 10 a and is in contact with the gate electrode film 15 is formed. As shown in FIG. 4, the gate insulating film 14, the gate electrode film 15, and the silicon film 16 are removed in the planar MIS transistor formation region and the resistance element formation region.

  Next, as shown in FIGS. 5 and 16, the SiGe layer 17, the interface layer 18, and the La layer 19 are formed in the planar MIS transistor formation region and the resistance element formation region. The SiGe layer 17 functions as a work function control layer for the gate electrode of the p-type MIS transistor, and the La layer 19 functions as a work function control layer for the gate electrode of the n-type MIS transistor. That is, the SiGe layer 17 functions as a threshold control layer of the p-type MIS transistor, and the La layer 19 functions as a threshold control layer of the n-type MIS transistor.

  Next, as shown in FIGS. 6 and 17, a gate insulating film (second gate insulating film) 20 for the planar MIS transistor is formed on the entire surface. This gate insulating film 20 is formed of a hafnium oxide film. Subsequently, a gate electrode film (second gate electrode film) 21 for the planar MIS transistor is formed on the gate insulating film 20. The gate electrode film 21 is a metal electrode film made of TiN. As a result, a stacked film of the gate insulating film 20 and the gate electrode film 21 is formed in the fin-type MIS transistor formation region, the planar MIS transistor formation region, and the resistance element formation region. For convenience, the La layer 19 is omitted in the drawings after the step of FIG.

  Next, as shown in FIGS. 7 and 18, the gate insulating film 20 and the gate electrode film 21 formed on the semiconductor conductive portion 16a and in the resistance element formation region are removed. That is, the gate insulating film 20 and the gate electrode film 21 formed in the fin-type MIS transistor formation region and the resistance element formation region are removed.

  Next, as shown in FIGS. 8 and 19, a silicon film (conductive semiconductor film) 22 for a resistance element is formed on the entire surface. That is, the resistive element silicon film 22 is formed on the semiconductor conductive portion 16a and in the planar MIS transistor forming region and the resistive element forming region. That is, the resistive element silicon film 22 is formed in the fin-type MIS transistor formation region, the planar MIS transistor formation region, and the resistance element formation region.

  Next, as shown in FIGS. 9 and 20, the silicon film 22, the gate electrode film 21, the gate insulating film 20, and the interface layer 18 are anisotropically etched in the planar MIS transistor formation region. In the resistance element formation region, the silicon film 22 is anisotropically etched. In the fin-type MIS transistor formation region, the silicon film 22, the semiconductor conductive portion 16a, the gate electrode film 15, and the gate insulating film 14 are anisotropically etched. Thereby, a gate electrode for the planar MIS transistor is formed in the planar MIS transistor formation region. In the resistance element formation region, a resistance for the resistance element using the silicon film 22 is formed. In the fin-type MIS transistor formation region, a gate electrode for a fin-type MIS transistor having a double gate structure sandwiching the fin portion 10a from both sides is formed. As already described, since the SiGe layer 17 and the La layer 19 are formed as the work function control layer for the planar MIS transistor, the work function of the gate electrode of the planar MIS transistor and the gate electrode of the fin MIS transistor. Work functions are different from each other. That is, the fin-type MIS transistor has a mid gap work function, and the planar MIS transistor has a band edge work function.

  In this embodiment, the gate electrode for the planar MIS transistor, the resistor in the resistance element formation region, and the gate electrode for the fin MIS transistor are processed in the same process, but the gate electrode for the planar MIS transistor and the fin type are used. The gate electrode for the MIS transistor may be processed in a separate process.

  Next, as shown in FIGS. 10 and 21, As ions are implanted into the n-type MIS transistor region, and B ions are implanted into the p-type MIS transistor region. Further, heat treatment is performed at 800 ° C. for 5 seconds. Thereby, a shallow diffusion layer 23 for the source / drain is formed. Subsequently, after a silicon nitride film 24 and a silicon oxide film 25 are deposited on the entire surface, the silicon nitride film 24 and the silicon oxide film 25 are etched back. As a result, a sidewall portion composed of the silicon nitride film 24 and the silicon oxide film 25 is formed on the sidewall of the gate electrode. Thereafter, P ions are implanted into the n-type MIS transistor region, and B ions are implanted into the p-type MIS transistor region. Further, heat treatment is performed at 1030 ° C. for 5 seconds. Thereby, a deep diffusion layer 26 for source / drain is formed.

  Next, as shown in FIGS. 11 and 22, after the silicon oxide film 27 is formed on the entire surface, the silicon oxide film 27 is etched back in a region other than the resistance element formation region. Subsequently, after a NiPt film having a thickness of about 10 nm is deposited on the entire surface, a heat treatment is performed at 350 ° C. for 30 seconds to react NiPt and silicon. Subsequently, the unreacted NiPt film is removed with a mixed solution of hydrochloric acid and nitric acid. Further, heat treatment is performed at 500 ° C. for 30 seconds. Thereby, the silicide layer 28 is formed. At this time, since the resistance in the resistance element formation region is covered with the silicon oxide film 27, no silicide is formed.

  As described above, as shown in FIGS. 11 and 22, a semiconductor device having a hybrid structure in which the fin-type MIS transistor, the planar MIS transistor, and the resistance element are formed on the same semiconductor substrate is obtained. That is, the fin MIS transistor 100 formed in the fin MIS transistor formation region, the planar MIS transistor (p-type MIS transistor 201, n-type MIS transistor 202) and resistor element formation region formed in the planar MIS transistor formation region. A semiconductor device having a hybrid structure including the resistance element 300 formed in the above can be obtained.

  As described above, in this embodiment, the gate insulating film 20 and the gate electrode film 21 formed in the fin-type MIS transistor formation region and the resistance element formation region are removed in the steps of FIGS. If the gate insulating film 20 and the gate electrode film 21 are not removed, the following problems occur.

  In the fin-type MIS transistor formation region, since the gate insulating film 20 is interposed between the gate electrode film 15 and the semiconductor conductive portion 16a and the conductive silicon film 22, the semiconductor conductive portion 16a and the silicon film 22 are electrically connected. It will stop conducting. As a result, an appropriate voltage cannot be applied to the gate electrode of the fin-type MIS transistor.

  In the resistance element formation region, the resistance element has a laminated structure of the silicon film 22 and the gate electrode film 21 which is a metal film, and therefore the resistance value of the resistance element is determined by the low resistance gate electrode film 21. Therefore, the resistance of the resistance element cannot be controlled by the impurity concentration in the silicon film. As a result, it becomes impossible to obtain a resistance element having an appropriate resistance value.

  In the present embodiment, the gate insulating film 20 and the gate electrode film 21 formed in the fin-type MIS transistor formation region and the resistance element formation region are removed in the steps of FIGS. can do. Therefore, an accurate manufacturing method can be realized in a semiconductor device (semiconductor integrated circuit device) in which a fin-type MIS transistor, a planar MIS transistor, and a resistance element are integrated. Therefore, it is possible to accurately manufacture a semiconductor device in which threshold control (work function control of the gate electrode) is performed in each of the planar MIS transistor and the fin MIS transistor.

  In the above-described embodiment, TiN films are used as the gate electrode films 15 and 21, but generally nitrides, carbides, silicon nitrides, and silicon carbides of group IV elements (Ti, Zr, Hf) are used. It is possible to use. It is also possible to use nitrides, carbides, silicon nitrides, and silicon carbides of group V elements (V, Nb, Ta). Further, nitrides, carbides, silicon nitrides and silicon carbides of group VI elements (Mo, W) can be used.

In the above-described embodiments, hafnium oxide films are used as the gate insulating films 14 and 20, but generally oxides such as Hf, Zr, Ti, Ta, Al, Sr, Y, and La are used. It is possible. In addition, oxides of these elements and silicon (for example, ZrSi _x O _y ) can be used. Alternatively, a laminated film of any combination of these oxides can be used.

  Although the embodiments of the present invention have been described above, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the spirit of the present invention. Furthermore, the above embodiments include inventions at various stages, and various inventions can be extracted by appropriately combining the disclosed constituent elements. For example, even if several constituent requirements are deleted from the disclosed constituent requirements, the invention can be extracted as an invention as long as a predetermined effect can be obtained.

DESCRIPTION OF SYMBOLS 10 ... Silicon substrate 10a ... Fin part 11 ... Element isolation region 12 ... Sacrificial oxide film 13 ... Silicon nitride film 14 ... Gate insulating film 15 ... Gate electrode film 16 ... Silicon film 16a ... Semiconductor conductive part 17 ... SiGe layer 18 ... Interface layer DESCRIPTION OF SYMBOLS 19 ... La layer 20 ... Gate insulating film 21 ... Gate electrode film 22 ... Silicon film 23 ... Shallow diffusion layer 24 ... Silicon nitride film 25 ... Silicon oxide film 26 ... Deep diffusion layer 27 ... Silicon oxide film 28 ... Silicide layer

Claims (5)

Forming a fin portion in the fin-type MIS transistor formation region;
Forming a first gate insulating film and a first gate electrode film for a fin-type MIS transistor on a side surface of the fin portion;
Forming a semiconductor conductive portion that surrounds and contacts the first gate insulating film and the first gate electrode film formed on a side surface of the fin portion and the fin portion;
Forming a second gate insulating film and a second gate electrode film for a planar MIS transistor on the semiconductor conductive portion and in a planar MIS transistor formation region and a resistance element formation region;
Removing the second gate insulating film and the second gate electrode film formed on the semiconductor conductive portion and in the resistance element formation region;
Forming a semiconductor film for a resistance element on the semiconductor conductive portion and in a planar MIS transistor formation area and a resistance element formation area after removing the second gate insulating film and the second gate electrode film; ,
A method for manufacturing a semiconductor device, comprising: The first gate insulating film, the first gate electrode film, the second gate electrode film, the second gate electrode film, and the second gate MIS transistor have a work function different from that of the planar MIS transistor. The method for manufacturing a semiconductor device according to claim 1, wherein a gate insulating film and the second gate electrode film are formed. The method of manufacturing a semiconductor device according to claim 1, further comprising a step of patterning the semiconductor film and the first gate electrode film to form a gate electrode for the fin-type MIS transistor. The method for manufacturing a semiconductor device according to claim 1, further comprising a step of patterning the semiconductor film and the second gate electrode film to form a gate electrode for the planar MIS transistor. 5. The semiconductor according to claim 4, wherein when forming the gate electrode for the planar MIS transistor, the semiconductor film in the resistance element formation region is patterned to form a resistance for the resistance element. 6. Device manufacturing method.

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