1286973 九、發明說明： 【發明所屬之技術領域】 本案係關於一種識別電路，尤指一種適用以辨別噴墨 頭之識別電路。 【先前技術】 近年來隨著個人電細普及與網際網路的快速發展，嘴 墨印表機目前已成為個人電腦設備中必備的產品。對—般 的使用者來說，一台基本型的喷墨印表機就足以應付各種 文件列印的需求。眾所週知，影響噴墨印表機列印品質之 因素有很多，例如墨水的組成，紙張的選擇以及墨水厘之 供墨方式等等。為追求更完美之列印品質，相關研發者已 投入大量時間與心力於墨水匣儲墨與供墨結構設計，以期 能付合結構簡單、製作成本低、南儲墨能力以及高列印品 質等要求。 喷墨列印技術發展至今，控制喷墨頭（printhead)釋出 墨滴至喷墨媒體之方式可大致分為兩大主流，其一係為熱 氣泡式（Thermal Bubble Ink Jet)技術，其操作原理係利用加 熱電阻器（thin film resistor)加熱使部分墨水產生氣泡進而 將墨水排擠出，並使之通過複數個喷孔喷至喷墨媒體上。 另一則為壓電致動式（Piezo-electric)技術，其原理是利用壓 電材料的壓電特性，於通電後而將墨水推出喷嘴。 由於每一種類型的喷墨列印技術都需要配合獨特的 1286973 嘴墨頭’再加上各種喷墨頭皆有其特殊的規格，包含：結 構、使用的墨水、喷孔數以及喷墨控制電路等特性，因此 需要搭配相容的列印系統，才能正確地完成列印工作，一 般而言，目前的印表機所設置的墨水匣是可以互換或是可 ' 同時承載兩種墨水匣，例如彩色墨水匣可與黑色墨水匣互 ' 換或是可同時承載彩色墨水匣及黑色墨水匣，由於彩色墨 水匣及黑色墨水匣所設置的喷墨頭的規格並不相同，因此 _ t使用者將墨水e安裝至印表機上時，印表機内部的控制 電路必須能夠識別墨水g之喷墨頭的規格，才能使用才:對 應的驅動程式進行驅動’故需要-識別電路做為印表機識 另’j喷墨頭，並將識別電路做為喷墨頭可用於印表機的依 因此，如何發展一種可改善上述習知技術缺失之用 辨別噴_之朗電路，實為目前物㈣料之問題。 【發明内容】 t案〇要目的在於提供-種用以辨 ^路’猎由計數電路及編碼電路來依序輸出關 ^ 資訊之控制信號，並透過輸出電路提供給印表、、 該喷墨頭之複數個識別信號，使印表機電路萨、代表 別信號來觸喷墨賴種類，使印表機與噴^複數個識 的搭配，並藉此達到識別喷墨頭的目的。·碩間有良好 為達上述目的，本案之-較廣義實施樣態為提供〜 - 識別電路，其係適用於一喷墨頭且與一 贺墨頭 I衣機電路連接， 7 1286973 用以接收該印表機電路所傳送之一第一時脈信號、一第二 時脈信號、一負載信號以及一電壓源，其係包含··一計數 電路’其係接㈣第-時脈信號、該第二時脈信號以及該 負载信號，因應該第一時脈信號、該第二時脈信號以及該 負載信號之觸發而並行輸出複數個第一控制信號；一編碼 電路，其係與該計數電路連接，用以接收該複數個第一控 制信號並串列輸出第二控制信號；以及一輸出電路，其係 與該編碼電路及該印表機電路連接，用以因應該第二控制 信號依序輸出代表該喷墨頭之複數個識別信號；其中，該 印表機電路係藉由該複數個識別信號來辨識該喷墨頭的 種類。 【實施方式】 體挺本案特徵與優點的實施例將在後段的.說明中詳 細敘述。應理解的是本案能夠在不同的態樣上具有各種的 變化，其皆不脫離本案的範圍，且其中的說明及圖示在本 質上係當作說明之用，而非用以限制本案。 請參閱第一圖，其係為本案較佳實施例之噴墨頭識別 電路之電路方塊示意圖，如第一圖所示，本案較佳實施例 之喷墨頭識別電路10主要係設置於一喷墨頭（未圖示） 内部且與印表機電路（未圖示）連接，並接收印表機電路 經由輸入端14所輸入之第一時脈信號（Clkl)、輸入端15 所輸入之第二時脈信號(Clk2)、輸入端16所輸入之負載信 1286973 號（Load)以及電源端π所輸入之電壓源（Vdd)，本案之 喷墨頭識別電路10係由計數電路Π、編碼電路12以及輸 出電路13所構成，用以依序串列輸出代表噴墨頭之複數 個識別信號至印表機電路，使印表機電路可藉由該複數個 識別信號來辨識該喷墨頭的種類，進而正確地控制該喷墨 . 頭運作。 • 計數電路11係由一個第一計數器111以及複數個第二 計數器112所構成，於本案實施例中，計數電路u内部係 包含4個計數器，第一計數器係接收第一時脈信號 (Clkl)、第二時脈信號(Clk2)以及負載信號(Load)，並因 應第一時滅信號（Clkl)、第二時脈信號(Clk2)以及負載信 號(Load)對其内部電路之觸發而輸出一第一控制信號’即 第1位元開關訊號’至編瑪電路12以及與其連接之弟'一 計數器112的輸入端（In)。 ‘ · 請參閲第二圖，其係為第一圖所示之弟一計數斋之電 _ 路結構圖，如圖所示，第一計數器111係包含接收第一時 脈信號（Clkl)之輸入端14、接收第二時脈信號(Clk2)之 輸入端15、接收負載信號（Load)之輸入端16、提供電 壓源(Vdd)之電源端17、用以輸出第〆控制信號之輸出端 (Out)llll、接地端I112、第一開關電晶體A1、第二開關 電晶體A2、第三開關電晶體A3、第四開關電晶體A4、第 五開關電晶體A5、第六電阻器R6、第七開關電晶體A7、 第八開關電晶體A8、第九開關電晶體A9、第十開關電晶 體A10以及第十一開關電晶體AH。 1286973 弟開關電晶體A1具有一源極（g；ource)及一沒極 (Drain)’以及接收第二時脈信號之一閘極(Gate);第二開 離電晶體A2具有與第一開關電晶體A1之源極連接之一汲 _ ,極、接收負載信號之一閘極以及與接地端m2連接之一源 • 極，苐二開關電晶體A3具有一源極、與第一開關電晶體 ， A1之汲極連接之一汲極，以及接收負載信號之一閘極；第 四開關電晶體A4具有一源極、與第三開關電晶體A3之源 _ 極連接之一汲極，以及接收第一時脈信號之一閘極；第五 開關電晶體A5具有與第三開關電晶體A3之源極及第四開 關電晶體A4之汲極連接之一汲極、與第一開關電晶體A1 之源極及第二開關電晶體A2之汲極連接之一閘極，以及 與接地端1112連接之一源極；第六電阻器R6係與電源端 17連接，第七開關電晶體A7具有與第六電阻器R6連接 之；及極·、與弟四開關電晶體A4之源極連接之^閘極， 以及與接地端1112連接之一源極；第八開關電晶體A8具 _ 有一源極、與第六電阻器R6及第七開關電晶體A7之汲極 連接之一汲極，以及接收第二時脈信號之一閘極；第九開 關電晶體A9具有與第八開關電晶體A8之源極連接之一源 極、接收負載信號之一閘極，以及與電源端17連接之一 . 汲極，第十開關電晶體A10具有一源極、與電源端17連 接之一汲極，以及接收第二時脈信號之一閘極；第十一開 關電晶體All具有與第十開關電晶體A10之源極及輸出端 1111連接之一汲極、與第九開關電晶體A9之源極連接之 一閘極，以及與接地端1112連接之一源極。 1286973 請再參閱第一圖，第二計數器112除了接收第一時脈 信號（Clkl)、第二時脈信號(Clk2)以及負載信號(Load)之 外，更接收前一個計數器所輸出之控制信號，並因應該第 一時脈信號（Clkl)、第二時脈信號（Clk2)以及負載信號 (Load)以及前一級計數器輸出之第一控制信號之觸發而並 行輸出3個第一控制信號至編碼電路12，即第2〜4位元 開關訊號，舉例而言，第一個第二計數器112將接收第一 時脈信號（Clkl)、第二時脈信號(Clk2)、負載信號(Load)以 及第一計數器111所輸出之第一控制信號，經内部電路運 作後輸出第二個第一控制信號，即第2位元開關訊號，至 編碼電路12以及與其連接之下一級第二計數器112的輸 入端（In) 1121，至於後續的第二計數器112的運作方式 以此類推，於此不再贅述。 ‘ 請參閱第三圖，其係為箄一圖所示之第二計數器之電 路結構圖，如圖所示，第一圖所示之每一第二計數器112 係包含接收第一時脈信號（Clkl )之輸入端14、接收第二 時脈信號(Clk2)之輸入端15、接收負載信號（Load)之輸 入端16、提供電壓源（Vdd)之電源端17、用以接收前一級 計數器所輸出之第一控制信號之輸入端（In) 1121、用以 輸出第一控制信號之輸出端（Out)1122、接地端1123、第十 二開關電晶體A12、第十三電阻器R13、第十四開關電晶 體A14、第十五開關電晶體A15、第十六開關電晶體A16、 第十七開關電晶體A17以及第十八開關電晶體A18。 第十二開關電晶體A12具有一源極、接收前一級計 11 1286973 數器所輸出之第一控制信號之一汲極，以及接收第一時脈 信號之一閘極；第十三電阻器R13係與電源端π連接； 第十四開關電晶體A14具有與第十三電阻器R13連接之一 没極、與第十'一開關電晶體A12之源極連接之一閘極，以 及與接地端1123連接之一源極；第十五開關電晶體A15 . 具有一源極、與第十三電阻器R13及第十四開關電晶體 ' A14之汲極連接之一没極，以及接收第二時脈信號之一閘 φ 極；第十六開關電晶體A16具有與第十五開關電晶體A15 之源極連接之一源極、接收負載信號之一閘極，以及與電 源端17連接之一汲極；第十七開關電晶體A17具有一源 極、接收第二時脈信號之一閘極，以及與電源端π連接 之一没極；第十八開關電晶體Α18具有與第十七開關電晶 體Α17之源極及輸出端1122連接之一汲極、與第十六開 •關電晶體Α16之源極連接之一閱極，以·及與接地端1123 連接之一源極。 _ 請再參閱第一圖，編碼電路12係與計數電路11及輸 出電路13電路連接，且由4個開關電晶體M3〜Μ6所構 成，每一個開關電晶體M3〜Μ6均分別與其相對應之計數 器的輸出端連接，用以接收第一控制信號並依序串列輸出 • 第二控制信號，其中，開關電晶體M3〜Μ6的閘極分別連 接至相對應的計數器的輸出端，汲極則依編碼設定連接至 電源端17或接地端，以接收電壓源（Vdd)或接地端的訊 號，而源極則連接至輸出電路13。 輸出電路13係與編碼電路12及印表機電路連接，且 12 1286973 系由第一開關電晶體M1及第二開關電晶體M2所組成， 主要用來接收輸入端16所輸入之負載信號以及編碼電路 U所依序串列輸出之第二控制信號，並因應第二控制信號 序輪出代表喷墨頭之複數個識別信號至印表機電路，使 印表機電路可藉由該複數個識別信號來辨識該喷墨頭的 種類’進而正確地控制該喷墨頭運作。 其中，第二開關電晶體M2的没極係與編碼電路12 ⑩的開關電晶體M3〜M6的源極連接、閘極則與輸入端16 連接，用以接收負載信號，而源極則與接地端連接，而第 一開關電晶體M2的作用係為當輸入端16輸入之負載信號 為高電壓信號時，第二開關電晶體M2將動作，用以將輸 出序列節點（Out-list node)上的信號重置（reset); 第一開關電晶體Ml的閘極係與編碼電路12的開關電晶體 M3〜.M6的源極連接，汲極則與輸·出端18連接，而辱極同 樣與接地端連接，其中輸出端18係與印表機電路連接， Φ 用以輸出代表喷墨頭之複數個識別信號至印表機電路。 請參閱第二圖並請配合第一圖及第四圖，其中第四圖 係為第一時脈信號、第二時脈信號以及負載信號之信號波 形圖，以下將說明第二圖所示之第一計數器m的作動方 式·· (1)負載信號輸入高電壓（high)信號·· 1·當輸入端16接收之負載信號為高電壓信號，且輸 入端15接收之第二時脈信號為低電壓信號時，第三開關 電晶體A3將導通，使電源端π提供的電壓源（vdd)信號 13 1286973 傳入第四開關電晶體A4與第五開關電晶體A5相接的一 端，並且因負載信號為高電壓信號，所以第二開關電晶體 A2則動作’進而將第五開關電晶體A5的閘極端做重置的 動作； 至於，在第一計數器111的輸出端1111方面，第九 開關電晶體A9將動作，使電源端17的電壓源（vdd)信號 經第九開關電晶體A9到第十一開關電晶體All的閘極 鲁 端，將使第Η 開關電晶體All動作，進而使輸出端mi 做重置的動作； 2.接著當第一時脈信號為高電壓信號時，第四開關電 晶體A4將導通，以使第七開關電晶體"的閘極端接收到 高電壓信號’如此一來，第七開關電晶體A7將動作，使 •接地端1112的低電壓信號傳送到第八開闞電晶體…與第 六電阻器R6相接的一端； _ 3·接著當第二時脈信號為高電壓信號時，第八開關電 晶體A8及第十開關電晶體A1〇將導通，但因第七開關電 曰曰體A7的閘極端為高電壓，所以第七開關電晶體A7將動 =，故第八開關電晶體A8與第六電阻器R6相接的一端及 第十一開關電晶體All的閘極端皆為低電壓，將使第十一 開關電晶體All不動作，如此高電壓信號將經由第十開關 電晶體A10到輸出端lni，即第一計數器Ul輸出高電 齡號。此時，第-開關電晶體A1亦動作，將電源端17 的高電壓信號，即電壓源（)，傳到第五開關電晶體A5 1286973 的閘極端，使第五開關電晶體A5動作，如此第四開關電 晶體A4與第五開關電晶體A5相接的一端將產生重置的動 作，即第四開關電晶體A4與第五開關電晶體A5相接的一 端輸入低電壓信號， • (2)負載信號輸入低電壓信號： 1·當輸入端16接收之負載信號為低電壓信號，且輸 鲁 入端15接收之第二時脈仏號為南電壓信號時，第三開關 電晶體A3不導通，使電源端17所傳送的電壓源（vdd) 信號無法傳入第四開關電晶體A4與第五開關電晶體A5相 接的一端，但因第一開關電晶體A1動作，所以第五開關 電晶體A5將導通，使接地端1112的低電壓信號傳到第四 開關電晶體A4與第五開關電晶體A5相接的一端，即第一 計數器111中第四開關電晶體A4與萆五.開關電晶體A5相 接的一端輸入低電壓信號； • 2·接著當第一時脈信號為高電壓信號時，第四開關電 晶體A4導通，第七開關電晶體A7的閘極端接收低電壓信 號，如此第七開關電晶體A7不動作，使接地端1112的低 電壓信號與第八開關電晶體A8與第六電阻器狀相接的一 端隔離； 3·接著當第二時脈信號為高電壓信號時，第八開關電 晶體A8及第十開關電晶體A10動作，且因第七開關電晶 體A7不動作，所以電源端17的電壓源（Vdd)信號將經 由第六電阻器R6及第八開關電晶體A8到第十一開關電 15 1286973 晶體All的閘極端，使第十一開關電晶體AU動作，如 此輸出端1111將接收到低電壓信號，即第一計數器m 輸出為低電壓信號。此時，第一開關電晶體A1亦動作， 將電源端17的電壓源（Vdd)信號傳到第五開關電晶體 A5的閘極端，使第五開關電晶體A5動作，如此第四開關 電晶體A4與第五開關電晶體A5相接的一端產生重置的動 作，使第一計數器111中第四開關電晶體A4與第五開關 電晶體A5相接的一端輸入低電壓信號。 請參閱第三圖並請配合第一圖、第二圖及第四圖，以 下將說明第三圖所示之第二計數器H2的作動方式： 當輸入端16輸入之負載信號為高電壓信號時，第一 計舞器111及第二計數器U2.之輸出端皆產生低電壓信 说並傳至下一第一汁數器112之輸入端，而在後續第二時 脈號為而電壓時，每一第二計數器112的輸入端1121 將接收其前一級計數器之輸出端所傳送的輸出信號。 (1)當輸入端1121輸入高電廢信號時： 1·當輸入端1121輸入高電壓信號，且第一時脈信號 為高電壓信號時，則第十二開關電晶體A12導通，以將輸 入化1121所傳送的的南電壓信號傳至第十四開關電晶體 A14的閘極端，使第十四開關電晶體AH動作，而接地端 1123的低電壓信號將傳到第十五開關電晶體A15與第十 1286973 三電阻器R13相接的一端； 2·接著當第二時脈信號為高電壓信號時， 昂9五開關 電晶體A15以及第十七開關電晶體An將動作，但因第十 四開關電晶體A14動作，則接地端1123的信號將傳到第 十五開關電晶體A15與第十三電阻器R13相接的一端以及 • 第十八開關電晶體A18的閘極端，所以第十八開關電晶體 ‘ A18無法動作，如此電源端17的電壓源（Vdd)信號將麫 φ 第十七開關電晶體A17傳到輸出端1122，即第二計數器 112輸出為高電壓信號。 (2)當輸入端1121輸入低電壓信號時： 1·當第一時脈信號輸入高電壓信號時，則第十二開關 電晶體A12導通，以將輸入端1121所輸入的低電壓信號 傳至第十四開關電晶體A14.的閘極端，使第·十四開關電晶 體A14無法動作，則接地端1123的低電壓信號與第十五 _ 開關電晶體A15與第十三電阻器R13相接的一端隔離； 2·接著當第二時脈信號輸入高電壓信號時，因第十 四開關電晶體A14的閘極端為低電壓，且第十五開關電晶 體A15及第十七開關電晶體A17將動作，如此一來，電源 端17的電壓源（Vdd)信號將經第十三電阻器R13及第十 五開關電晶體A15到第十八開關電晶體A18的閘極端，所 以第十八開關電晶體A18將動作，以使接地端1123的低 電壓信號經第十八開關電晶體A18傳到輸出端1122,即第 二計數器112輸出低電壓信號； 17 1286973 ^卜’第十六開關電晶體Αΐβ的設計作用係為，當輸 入端6輸人的負載信號為高電壓信號時，電源端17的電 壓源（Vdd)信號將經過第十六開關電晶體刷 開關電晶體剔的閉極端，則第十八開關電晶體 作，而將輸出端1122重置。 部 請再^閱第-圖並請配合上述第二圖及第 作說明’第-圖其動作方式係為：經由第 運算’輸出端將輸出—第—個第—控制信號，= -位元開關訊號’到下—級的第二計數器112，且 個第-控制信號也送至編碼電路12之開關電晶體m 極端’若第一計數器⑴的輸出端mi輸出的第一控制 Μ為尚電壓信號’其餘第—控制信號為低電壓信號 編碼電路12之開關電晶體Μ3將動作，但開關電晶體财 〜Μ6不動作，故將開關電晶體Μ3汲極端信聲，在此實施 例中為電源端17所提供之電壓源（Vdd )信號經開關電晶體 M3傳至輸出電路13之第-開關電晶體M1的閘極端，使第 一開關電晶體Ml動作，如此本案喷墨頭識別電路1〇之輸 出端18的信號將與接地端相連，· ' 反之，若第一計數器的輸出端llu輸出的第一 個第、一控制信號為低電壓信號，其餘第一控制信號亦為低 電壓信號，則編碼電路12之開關電晶體M3將無法動作，_ t開關電晶體M4〜M6亦不動作，故開關電晶體M3汲極端 信號，在此實施例中為電源端17及開關電晶體鼢〜舫汲 極端信號無法傳至輸出電路13之第一開關電晶體扪的閘 1286973 極端，使第一開關電晶體Ml無法動作，如此一來，喷墨 頭識別電路10之輸出端18的輸出信號將不受影響。矣 於，其它3個第二計數器112及開關電晶體M4、M5以及 與輸出電路13之第—開關電晶體叽的配合作動方式係 與上述相同，於此不再贅述。 故於本案實施例中，第一圖所示之喷墨頭識別電路1〇 之輸出電路13内部之輪出序列節點依序接收到的信號為 • high、high、low、hi^，相對的經由第一開關電晶體Ml 處理後輸出信號將變化為1〇w、1〇w、high、lGw，即輸出 端18將依序串列輸出代表喷墨頭之識別信號為i〇w、i〇w、 high、low ,當印表機電路接收到此識別信號後，則可判 另J噴墨頭疋否可用於此印表機上，使印表機與喷墨頭間有 良好的搭配，並藉此達到識別喷墨頭的目的。 •综上所述，本案之用以辨別噴墨頭之識別電路是以計 數電路及編碼電路來依序輸出關於喷墨頭資訊之控制信 _ 號’並透過輸出電路提供給印表機電路代表該噴墨頭之複 數個識別信號’使印表機電路藉由複數個識別信號來辨識 喷墨頭的種類，使印表機與喷墨頭間有良好的搭配，並藉 此達到識別喷墨頭的目的。本案之用以辨別喷墨頭之識別 電路極具產業之價值，爰依法提出申請。 本案得由熟知此技術之人士任施匠思而為諸般修 飾，然皆不脫如附申請專利範圍所欲保護者。 19 1286973 【圖式簡單說明】 第一圖：其係為本案較佳實施例之喷墨頭識別電路之電路 方塊示意圖。 第二圖··其係為第一圖所示之第一計數器之電路結構圖。 第三圖：其係為第一圖所示之第二計數器之電路結構圖。 第四圖：其係為第一圖運作之第一時脈信號、第二時脈信號 以及負載信號之信號波形圖。 1286973 【主要元件符號說明】1286973 IX. Description of the invention: [Technical field to which the invention pertains] This case relates to an identification circuit, and more particularly to an identification circuit suitable for discriminating an ink jet head. [Prior Art] In recent years, with the popularity of personal electric power and the rapid development of the Internet, the ink printer has become an essential product in personal computer equipment. For a typical user, a basic inkjet printer is sufficient for a variety of document printing needs. It is well known that there are many factors that affect the print quality of inkjet printers, such as the composition of the ink, the choice of paper, and the way the ink is supplied. In order to pursue a more perfect print quality, the relevant developers have invested a lot of time and effort in the design of ink storage and ink supply structure, in order to be able to pay for a simple structure, low production cost, south ink storage capacity and high print quality. Claim. Since the development of inkjet printing technology, the way to control the inkjet head to discharge ink droplets to the inkjet media can be roughly divided into two major mainstreams, one of which is the Thermal Bubble Ink Jet technology, which operates. The principle is that a portion of the ink is bubbled by heating with a thin film resistor to extrude the ink, and is sprayed onto the inkjet medium through a plurality of orifices. The other is the Piezo-electric technology, which uses the piezoelectric properties of the piezoelectric material to push the ink out of the nozzle after energization. Since each type of inkjet printing technology requires a unique 1286973 nozzle ink head' plus a variety of inkjet heads with special specifications, including: structure, ink used, number of orifices, and inkjet control circuitry Such characteristics, so it is necessary to use a compatible printing system to complete the printing work correctly. Generally speaking, the ink cartridges set by the current printers are interchangeable or can carry two ink cartridges at the same time, for example The color ink cartridge can be interchanged with the black ink cartridge or can carry both the color ink cartridge and the black ink cartridge. Since the specifications of the inkjet head provided by the color ink cartridge and the black ink cartridge are not the same, the user will When the ink e is mounted on the printer, the control circuit inside the printer must be able to recognize the specifications of the ink head of the ink g before it can be used: the corresponding driver is driven. Therefore, the identification-recognition circuit is used as the printer. Knowing the other 'j inkjet head, and using the identification circuit as the inkjet head can be used for the printer. Therefore, how to develop a circuit that can improve the above-mentioned conventional technology It is actually the problem of the current (four) materials. SUMMARY OF THE INVENTION The purpose of the t case is to provide a control signal for sequentially recording and outputting information by the counting circuit and the encoding circuit, and supplying the printing signal to the printing table through the output circuit. The plurality of identification signals of the head enable the printer circuit to represent the other types of signals to touch the inkjet type, so that the printer can be matched with the spray and the plurality of identifications, thereby achieving the purpose of identifying the inkjet head. · The master has a good purpose for the above purposes. In this case, the generalized implementation provides a ~- identification circuit that is suitable for an inkjet head and is connected to a Hecha-I machine circuit, 7 1286973 for receiving a first clock signal, a second clock signal, a load signal and a voltage source transmitted by the printer circuit, comprising: a counting circuit 'connecting (four) the first-clock signal, the The second clock signal and the load signal output a plurality of first control signals in parallel according to the triggering of the first clock signal, the second clock signal, and the load signal; an encoding circuit coupled to the counting circuit a connection for receiving the plurality of first control signals and serially outputting the second control signal; and an output circuit coupled to the encoding circuit and the printer circuit for sequentially following the second control signal And outputting a plurality of identification signals representing the inkjet head; wherein the printer circuit identifies the type of the inkjet head by the plurality of identification signals. [Embodiment] An embodiment of the features and advantages of the present invention will be described in detail in the description of the latter paragraph. It is to be understood that the present invention is capable of various modifications in various embodiments and is not intended to limit the scope of the invention. Please refer to the first figure, which is a circuit block diagram of the inkjet head identification circuit of the preferred embodiment of the present invention. As shown in the first figure, the inkjet head identification circuit 10 of the preferred embodiment of the present invention is mainly disposed on a spray. The ink head (not shown) is internally connected to the printer circuit (not shown), and receives the first clock signal (Clkl) input by the printer circuit via the input terminal 14 and the input of the input terminal 15. The two-clock signal (Clk2), the load signal input to the input terminal 16 and the voltage source (Vdd) input from the power supply terminal π, the inkjet head identification circuit 10 of the present invention is composed of the counting circuit Π, the encoding circuit 12 and the output circuit 13 is configured to sequentially output a plurality of identification signals representing the inkjet head to the printer circuit in sequence, so that the printer circuit can identify the inkjet head by the plurality of identification signals. The type, which in turn controls the inkjet. The head operates. The counting circuit 11 is composed of a first counter 111 and a plurality of second counters 112. In the embodiment of the present invention, the counting circuit u internally includes four counters, and the first counter receives the first clock signal (Clkl). The second clock signal (Clk2) and the load signal (Load) are outputted in response to the triggering of the internal circuit by the first time-off signal (Clkl), the second clock signal (Clk2), and the load signal (Load). The first control signal 'ie, the first bit switching signal' is supplied to the numerator circuit 12 and the input terminal (In) of the counter 112 connected thereto. ' Please refer to the second figure, which is the circuit diagram of the circuit shown in the first figure. As shown in the figure, the first counter 111 includes the first clock signal (Clkl). The input terminal 14, the input terminal 15 for receiving the second clock signal (Clk2), the input terminal 16 for receiving the load signal (Load), the power terminal 17 for supplying the voltage source (Vdd), and the output terminal for outputting the second control signal (Out)llll, ground terminal I112, first switching transistor A1, second switching transistor A2, third switching transistor A3, fourth switching transistor A4, fifth switching transistor A5, sixth resistor R6, The seventh switching transistor A7, the eighth switching transistor A8, the ninth switching transistor A9, the tenth switching transistor A10, and the eleventh switching transistor AH. 1286973 The switch transistor A1 has a source (g;ource) and a drain (Drain) and receives a gate of the second clock signal (Gate); the second open transistor A2 has a first switch One source of the transistor A1 is connected to a source, a gate, a gate receiving a load signal, and a source connected to the ground terminal m2. The second switching transistor A3 has a source and a first switching transistor. One of the drains of A1 is connected to one of the drains, and one of the gates of the receiving load signal; the fourth switching transistor A4 has a source, one of the source _ poles of the third switching transistor A3, and a receiving a gate of the first clock signal; the fifth switch transistor A5 has a drain connected to the source of the third switching transistor A3 and the drain of the fourth switching transistor A4, and the first switching transistor A1 The drain of the source and the second switching transistor A2 is connected to one of the gates, and one source connected to the grounding terminal 1112; the sixth resistor R6 is connected to the power supply terminal 17, and the seventh switching transistor A7 has The sixth resistor R6 is connected; and the pole is connected to the source of the fourth switching transistor A4. a gate, and a source connected to the ground terminal 1112; the eighth switch transistor A8 has a source, a drain connected to the drain of the sixth resistor R6 and the seventh switch transistor A7, and Receiving one of the gates of the second clock signal; the ninth switching transistor A9 has one source connected to the source of the eighth switching transistor A8, one gate receiving the load signal, and one connected to the power terminal 17. The tenth switch transistor A10 has a source, a drain connected to the power terminal 17, and a gate receiving the second clock signal; the eleventh switch transistor All has a tenth switch The source and output terminals 1111 of the crystal A10 are connected to one of the drains, one of the gates connected to the source of the ninth switch transistor A9, and one source connected to the ground terminal 1112. 1286973 Please refer to the first figure again. In addition to receiving the first clock signal (Clkl), the second clock signal (Clk2), and the load signal (Load), the second counter 112 receives the control signal output by the previous counter. And outputting three first control signals to the code in parallel due to triggering of the first clock signal (Clkl), the second clock signal (Clk2), and the load signal (Load) and the first control signal output by the previous stage counter The circuit 12, that is, the 2nd to 4th bit switching signals, for example, the first second counter 112 will receive the first clock signal (Clkl), the second clock signal (Clk2), the load signal (Load), and The first control signal outputted by the first counter 111 is outputted by the internal circuit to output a second first control signal, that is, a second bit switching signal, to the encoding circuit 12 and an input of the second counter 112 connected thereto. The end (In) 1121, as for the operation mode of the subsequent second counter 112, and so on, will not be described herein. Please refer to the third figure, which is a circuit diagram of the second counter shown in the first figure. As shown in the figure, each second counter 112 shown in the first figure includes receiving the first clock signal ( The input terminal 14 of the Clk1), the input terminal 15 receiving the second clock signal (Clk2), the input terminal 16 receiving the load signal (Load), the power supply terminal 17 providing the voltage source (Vdd), and the receiving device for receiving the previous stage counter An input terminal (In) for outputting the first control signal (1) 1121, an output terminal (Out) 1122 for outputting the first control signal, a ground terminal 1123, a twelfth switch transistor A12, a thirteenth resistor R13, and a tenth The four-switch transistor A14, the fifteenth switch transistor A15, the sixteenth switch transistor A16, the seventeenth switch transistor A17, and the eighteenth switch transistor A18. The twelfth switching transistor A12 has a source, a drain of the first control signal outputted by the first stage 1 11286973, and a gate receiving the first clock signal; the thirteenth resistor R13 Connected to the power supply terminal π; the fourteenth switching transistor A14 has a gate connected to the thirteenth resistor R13, a gate connected to the source of the tenth 'one switching transistor A12, and a ground terminal 1123 is connected to one source; the fifteenth switching transistor A15 has one source, one of the thirteenth connection with the thirteenth resistor R13 and the fourteenth switching transistor 'A14, and one second when receiving One of the pulse signals is a gate φ pole; the sixteenth switch transistor A16 has a source connected to the source of the fifteenth switch transistor A15, one of the gates receiving the load signal, and one of the terminals connected to the power terminal 17. The seventeenth switch transistor A17 has a source, receives a gate of the second clock signal, and has one pole connected to the power terminal π; the eighteenth switch transistor Α18 has a power switch with the seventeenth switch The source of the crystal crucible 17 and the output end 1122 are connected to one of the drains, and • Off with forty source of the transistor is connected Α16 read one pole to the ground end-1123 and connected to one source. _ Referring again to the first figure, the encoding circuit 12 is electrically connected to the counting circuit 11 and the output circuit 13, and is composed of four switching transistors M3 Μ Μ 6 , and each of the switching transistors M3 Μ Μ 6 respectively corresponds thereto. The output end of the counter is connected to receive the first control signal and serially output the second control signal, wherein the gates of the switching transistors M3 Μ6 are respectively connected to the output ends of the corresponding counters, and the drains are It is connected to the power terminal 17 or the ground terminal according to the code setting to receive the signal of the voltage source (Vdd) or the ground, and the source is connected to the output circuit 13. The output circuit 13 is connected to the encoding circuit 12 and the printer circuit, and 12 1286973 is composed of a first switching transistor M1 and a second switching transistor M2, and is mainly used for receiving the load signal input by the input terminal 16 and encoding. The circuit U sequentially outputs the second control signal in sequence, and in response to the second control signal sequence, a plurality of identification signals representing the inkjet head are rotated to the printer circuit, so that the printer circuit can be identified by the plurality of The signal is used to identify the type of the ink jet head' to thereby properly control the operation of the ink jet head. Wherein, the second pole of the second switching transistor M2 is connected to the source of the switching transistors M3 M M6 of the encoding circuit 12 10 , and the gate is connected to the input terminal 16 for receiving the load signal, and the source is grounded. The terminal is connected, and the first switching transistor M2 functions when the input signal input to the input terminal 16 is a high voltage signal, and the second switching transistor M2 is activated to output the output sequence node (Out-list node). The signal resets; the gate of the first switching transistor M1 is connected to the source of the switching transistors M3 to M6 of the encoding circuit 12, and the drain is connected to the input and output terminals 18, and the humiliation is the same Connected to the ground terminal, wherein the output terminal 18 is connected to the printer circuit, and Φ is used to output a plurality of identification signals representing the inkjet head to the printer circuit. Please refer to the second figure and please cooperate with the first picture and the fourth picture. The fourth picture is the signal waveform of the first clock signal, the second clock signal and the load signal. The following figure will be explained in the second figure. Operation mode of the first counter m·· (1) Load signal input high voltage signal··1· When the load signal received at the input terminal 16 is a high voltage signal, and the second clock signal received at the input terminal 15 is When the voltage is low, the third switching transistor A3 will be turned on, so that the voltage source (vdd) signal 13 1286973 provided by the power terminal π is transmitted to the end of the fourth switching transistor A4 and the fifth switching transistor A5, and The load signal is a high voltage signal, so the second switching transistor A2 acts 'and further resets the gate terminal of the fifth switching transistor A5; as for the output terminal 1111 of the first counter 111, the ninth switch The transistor A9 will operate so that the voltage source (vdd) signal of the power supply terminal 17 passes through the ninth switching transistor A9 to the gate terminal of the eleventh switching transistor All, which will cause the second switching transistor All to operate, thereby Output mi is reset 2. Then when the first clock signal is a high voltage signal, the fourth switching transistor A4 will be turned on, so that the gate terminal of the seventh switching transistor " receives a high voltage signal. Thus, the seventh switch The transistor A7 will operate to transmit the low voltage signal of the ground terminal 1112 to the end of the eighth open transistor ... which is connected to the sixth resistor R6; _ 3 · then when the second clock signal is a high voltage signal The eighth switch transistor A8 and the tenth switch transistor A1〇 will be turned on, but since the gate terminal of the seventh switch electrode body A7 is high voltage, the seventh switch transistor A7 will move =, so the eighth switch The end of the transistor A8 that is connected to the sixth resistor R6 and the gate of the eleventh switching transistor All are both low voltages, so that the eleventh switching transistor All does not operate, and the high voltage signal will pass through the tenth switch. The transistor A10 to the output terminal lni, that is, the first counter U1 outputs a high battery age number. At this time, the first switching transistor A1 also operates to transmit the high voltage signal of the power supply terminal 17, that is, the voltage source (), to the gate terminal of the fifth switching transistor A5 1286973, so that the fifth switching transistor A5 operates. The end of the fourth switching transistor A4 connected to the fifth switching transistor A5 will generate a reset action, that is, the end of the fourth switching transistor A4 connected to the fifth switching transistor A5 inputs a low voltage signal, • (2 The load signal is input to the low voltage signal: 1. When the load signal received by the input terminal 16 is a low voltage signal, and the second clock signal received by the input terminal 15 is a south voltage signal, the third switch transistor A3 is not Turning on, the voltage source (vdd) signal transmitted by the power terminal 17 cannot be transmitted to the end of the fourth switching transistor A4 and the fifth switching transistor A5, but the first switch transistor A1 operates, so the fifth switch The transistor A5 will be turned on, so that the low voltage signal of the ground terminal 1112 is transmitted to the end of the fourth switching transistor A4 and the fifth switching transistor A5, that is, the fourth switching transistor A4 and the fifth transistor in the first counter 111. One end of the switching transistor A5 is connected Low voltage signal; 2) Then, when the first clock signal is a high voltage signal, the fourth switching transistor A4 is turned on, and the gate terminal of the seventh switching transistor A7 receives a low voltage signal, so that the seventh switching transistor A7 is not Acting to isolate the low voltage signal of the ground terminal 1112 from the end of the eighth switching transistor A8 and the sixth resistor; 3. Then, when the second clock signal is a high voltage signal, the eighth switching transistor A8 And the tenth switch transistor A10 operates, and because the seventh switch transistor A7 does not operate, the voltage source (Vdd) signal of the power terminal 17 will pass through the sixth resistor R6 and the eighth switch transistor A8 to the eleventh switch. The gate terminal of the crystal 15 1286973 is turned to operate the eleventh switching transistor AU, so that the output terminal 1111 will receive the low voltage signal, that is, the first counter m is output as a low voltage signal. At this time, the first switching transistor A1 also operates to transmit the voltage source (Vdd) signal of the power terminal 17 to the gate terminal of the fifth switching transistor A5, so that the fifth switching transistor A5 operates, such that the fourth switching transistor One end of the A4 connected to the fifth switching transistor A5 generates a reset operation, and the one end of the fourth switching transistor A4 and the fifth switching transistor A5 of the first counter 111 is input with a low voltage signal. Please refer to the third figure and please cooperate with the first figure, the second figure and the fourth figure. The following describes the operation mode of the second counter H2 shown in the third figure: When the input signal input to the input terminal 16 is a high voltage signal The output ends of the first meter dancer 111 and the second counter U2. both generate a low voltage signal and transmit to the input end of the next first juice counter 112, and when the subsequent second clock signal is a voltage, The input 1121 of each second counter 112 will receive the output signal transmitted by the output of its previous stage counter. (1) When the input terminal 1121 inputs a high-power waste signal: 1. When the input terminal 1121 inputs a high-voltage signal, and the first clock signal is a high-voltage signal, the twelfth switch transistor A12 is turned on to input The south voltage signal transmitted by the step 1121 is transmitted to the gate terminal of the fourteenth switching transistor A14 to operate the fourteenth switching transistor AH, and the low voltage signal of the ground terminal 1123 is transmitted to the fifteenth switching transistor A15. One end connected to the tenth 12269973 three resistor R13; 2. Then when the second clock signal is a high voltage signal, the Ang 9 switch transistor A15 and the seventeenth switch transistor An will operate, but due to the tenth When the four-switch transistor A14 is activated, the signal of the ground terminal 1123 is transmitted to the end of the fifteenth switch transistor A15 and the thirteenth resistor R13 and the gate terminal of the eighteenth switch transistor A18, so the tenth The eight-switch transistor 'A18' is inoperable, so that the voltage source (Vdd) signal of the power terminal 17 transmits 麫φ the seventeenth switch transistor A17 to the output terminal 1122, that is, the second counter 112 outputs a high voltage signal. (2) When the input terminal 1121 inputs a low voltage signal: 1. When the first clock signal inputs a high voltage signal, the twelfth switching transistor A12 is turned on to transmit the low voltage signal input to the input terminal 1121 to The gate terminal of the fourteenth switch transistor A14. makes the fourteenth switch transistor A14 inoperable, and the low voltage signal of the ground terminal 1123 is connected to the fifteenth switch transistor A15 and the thirteenth resistor R13. One end is isolated; 2. When the second clock signal is input to the high voltage signal, the gate terminal of the fourteenth switching transistor A14 is low voltage, and the fifteenth switching transistor A15 and the seventeenth switching transistor A17 In this way, the voltage source (Vdd) signal of the power terminal 17 will pass through the thirteenth resistor R13 and the fifteenth switch transistor A15 to the gate terminal of the eighteenth switch transistor A18, so the eighteenth switch The transistor A18 will operate so that the low voltage signal of the ground terminal 1123 is transmitted to the output terminal 1122 via the eighteenth switching transistor A18, that is, the second counter 112 outputs a low voltage signal; 17 1286973^'the sixteenth switching transistor The design of Αΐβ is based on When the load signal of the input terminal 6 is a high voltage signal, the voltage source (Vdd) signal of the power terminal 17 will pass through the closed end of the sixteenth switch transistor switch transistor, and the eighteenth switch transistor is used. The output 1122 is reset. Please read the figure again and please cooperate with the above second figure and the description. The first mode is: The second signal 112 of the switching signal 'to the lower stage, and the first control signal is also sent to the switching transistor m terminal of the encoding circuit 12'. If the first control output of the output terminal mi of the first counter (1) is still voltage The signal 'the remaining first-control signal is the switching transistor Μ3 of the low-voltage signal encoding circuit 12 will operate, but the switching transistor Μ6 does not operate, so the switching transistor Μ3汲 extreme signal, in this embodiment is the power supply The voltage source (Vdd) signal provided by the terminal 17 is transmitted to the gate terminal of the first switching transistor M1 of the output circuit 13 via the switching transistor M3, so that the first switching transistor M1 operates, so that the inkjet head identification circuit 1 of the present invention The signal of the output terminal 18 is connected to the ground terminal. · On the contrary, if the first first control signal outputted by the output terminal llu of the first counter is a low voltage signal, the remaining first control signals are also low voltage signals. Encoding circuit 12 The switching transistor M3 will not operate, and the _t switch transistors M4 to M6 will not operate, so the switching transistor M3 汲 extreme signal, in this embodiment, the power supply terminal 17 and the switching transistor 鼢~舫汲 extreme signal cannot be transmitted. To the extreme of the gate 1269973 of the first switching transistor 输出 of the output circuit 13, the first switching transistor M1 is rendered inoperable, so that the output signal of the output terminal 18 of the inkjet head identification circuit 10 will not be affected. The other two second counters 112 and the switching transistors M4 and M5 and the first switching transistor 叽 of the output circuit 13 are the same as the above, and will not be described again. Therefore, in the embodiment of the present invention, the signals sequentially received by the wheel sequence node inside the output circuit 13 of the inkjet head recognition circuit 1 shown in the first figure are • high, high, low, hi^, and the relative via After the first switching transistor M1 processes, the output signal will change to 1〇w, 1〇w, high, lGw, that is, the output terminal 18 will serially output the identification signals representing the inkjet head as i〇w, i〇w. , high, low, when the printer circuit receives this identification signal, it can be judged whether the other J inkjet head can be used on the printer, so that the printer and the inkjet head have a good match, and Thereby, the purpose of identifying the inkjet head is achieved. In summary, the identification circuit for discriminating the inkjet head in the present case is to sequentially output the control signal _ of the inkjet head information by the counting circuit and the encoding circuit and provide the printer circuit representative through the output circuit. The plurality of identification signals of the inkjet head enable the printer circuit to identify the type of the inkjet head by a plurality of identification signals, so that a good match between the printer and the inkjet head is achieved, and thereby the inkjet recognition is achieved. The purpose of the head. The identification circuit used to identify the inkjet head in this case is of great industrial value and is submitted in accordance with the law. This case has been modified by people who are familiar with the technology, but it is not intended to be protected by the scope of the patent application. 19 1286973 BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a block diagram showing the circuit of the ink jet head recognition circuit of the preferred embodiment of the present invention. The second figure is a circuit configuration diagram of the first counter shown in the first figure. Third figure: It is a circuit structure diagram of the second counter shown in the first figure. The fourth picture is the signal waveform of the first clock signal, the second clock signal and the load signal of the operation of the first figure. 1286973 [Main component symbol description]
喷墨頭識別電路：10 第一計數器：111 輸出端：1111 編碼電路：12 輸出端：1122 輸入端：14、15、16、1121 輸出端：18 第二時脈信號：Clk2 電壓源·· Vdd 第二開關電晶體：A2 第五開關電晶體：A5 第六電阻器：R6 第八開關電晶體：A8 第十開關電晶體：A10 第十二開關電晶體：A12 第十四開關電晶體：A14 第十六開關電晶體：A16 第十八開關電晶體：A18 計數電路：11 第二計數器：112 接地端：1112 輸出電路：13 接地端：1123 電源端：17 第一時脈信號·· Clkl 負載信號：Load 第一開關電晶體：A1 第三開關電晶體：A3 第四開關電晶體：A4 第七開關電晶體·· A7 第九開關電晶體：A9 第十一開關電晶體：All 第十三電阻器：R13 第十五開關電晶體：A15 第十七開關電晶體·· A17 21Inkjet head recognition circuit: 10 First counter: 111 Output: 1111 Encoding circuit: 12 Output: 1122 Input: 14, 15, 16, 1121 Output: 18 Second clock signal: Clk2 Voltage source · · Vdd Second switch transistor: A2 Fifth switch transistor: A5 Sixth resistor: R6 Eight switch transistor: A8 Tenth switch transistor: A10 Twelfth switch transistor: A12 Fourteenth switch transistor: A14 Sixteenth switch transistor: A16 Eighteen switch transistor: A18 Counting circuit: 11 Second counter: 112 Ground terminal: 1112 Output circuit: 13 Ground terminal: 1123 Power terminal: 17 First clock signal · · Clkl load Signal: Load First switch transistor: A1 Third switch transistor: A3 Fourth switch transistor: A4 Seventh switch transistor · A7 Ninth switch transistor: A9 Eleventh switch transistor: All thirteen Resistor: R13 The fifteenth switch transistor: A15 The seventeenth switch transistor ·· A17 21