TWI473723B - An identification circuit for an inkjet printhead - Google Patents

Description

Identification circuit for inkjet head

The present invention relates to an identification circuit, and more particularly to an identification circuit suitable for an inkjet head.

With the advancement of technology, users are increasingly demanding products. Taking inkjet printers as an example, various inkjet printers have been developed for different printing needs, and each inkjet printer has a corresponding variety of cassettes, such as black cassettes. , color cassettes, and the number of nozzles on the inkjet head are different.

Since each type of inkjet printing technology requires a variety of corresponding inkjet heads, and various inkjet heads have their specific specifications, such as: structure, ink used, number of orifices, and inkjet control circuitry, etc. Therefore, a compatible inkjet system is required to properly perform the inkjet work. In general, the inkjet printers currently installed in the inkjet printers are interchangeable or can carry two ink cartridges at the same time. For example, the color ink cartridges may be different from the inkjet heads provided by the black ink cartridges. Therefore, when the user's ink cartridge is mounted on the inkjet printer, the control circuit inside the inkjet printer must be able to recognize the specifications of the inkjet head of the ink cartridge, so that the corresponding driver can be used for driving, so a need is required. The identification circuit serves as the basis for the inkjet printer to recognize the inkjet head.

Please refer to FIG. 1A, which is a schematic diagram of the circuit structure of the prior art identification circuit. As shown, the fuse 10 is connected between the identification signal ID and the switching element 12, and the driving control terminal receives an identification signal ID, and the switching element 12 is connected to the control contact 13 and An address signal Ai is received between the ground terminals 14 and controlled by the control contacts 13 for controlling the on and off of the switching elements 12. For example, when the address signal Ai received by the control contact 13 is relatively high (High), the switching element 12 is turned on, and when the identification signal ID is high, the fuse 10 will be broken. On the contrary, when the address signal Ai received by the control contact 13 is relatively logic low (Low), the switching element 12 is turned off, and the fuse 10 will not be blown by the potential of the identification signal ID. Please refer to FIG. 1B, which is a circuit diagram of a pull-down resistor connected to the address signal and the identification signal of FIG. 1A, respectively. As shown in the figure, the pull-down resistors 15 are respectively disposed between the address signal Ai and the ground and between the identification signal ID and the ground, and are mainly used to stabilize the voltage so that the switching element 12 can operate stably.

Please refer to FIG. 2A and FIG. 2B. FIG. 2A is a timing chart of the first printing direction address signal shown in FIG. 1A, and FIG. 2B is a second printing direction position shown in FIG. 1A. The address signal timing diagram, as shown in FIG. 2A and FIG. 2B, wherein the first printing direction, that is, the state where the address signal is relatively logic high, is sequentially outputted by A1~A16, and the address signal A16 is outputted. The address signal A1 is connected, that is, this is a forward printing signal. Conversely, the second printing direction, that is, the state in which the address signal is relatively logic high, is sequentially outputted by A16~A1, and the address signal A1 is outputted and then connected to the address signal A16, that is, it is a reverse printing signal. However, since the address signal Ai is a continuous signal when printed, the switching element 12 of FIG. 1A is continuously turned on, and an improper voltage difference is generated between the identification signal ID and the ground terminal 14, for example, electrostatic discharge ( Electrostatic Discharge (ESD), Electrical Overstress (EOS), etc., are prone to damage to the fuse 10 and circuit identification errors.

In view of this, how to develop an identification circuit suitable for an inkjet head to improve the above The lack of customary technology is an urgent problem to be solved.

The main purpose of the present invention is to provide an identification circuit suitable for an inkjet head, which solves the problem that an improper voltage difference is easily generated between the identification signal of the conventional identification circuit and the ground, and the fuse damage and the circuit identification error are caused.

In order to achieve the above object, a broader aspect of the present invention provides an identification circuit suitable for an inkjet head for receiving an identification signal, an address signal and a selection signal of a printer, the identification circuit comprising: a first switching element Electrically connected to the fuse and the ground, and the fuse receives the identification signal; and the second switching element is electrically connected to the first switching element and the address signal, and the address signal is when the second switching element is turned on. Providing an address signal to the first switching element to drive the first switching element to be turned on or not, and the selecting signal is used to convert the second element switch between an enabling level or an inactive level to Driving the second switching element to be turned on or not; wherein the selection signal is converted to an enable level earlier than the address signal, and the selection signal is later converted to the disable level than the address signal, and the address signal ratio identification signal Early conversion to enable level, and the address signal is converted to the disable level later than the identification signal to ensure that the first switching element can actually achieve conduction or not during printing to protect the fuse from being Destroyed and prevent the identification circuit generating a recognition error phenomenon.

10, 31‧‧‧Fuse

12‧‧‧Switching elements

13‧‧‧Control contacts

14, 33, 41, 51‧‧‧ Ground

15, 34‧‧‧ Pull-down resistor

3, 4, 5‧‧‧ identification circuit

30‧‧‧First switching element

32‧‧‧Second switching element

40‧‧‧ Third switching element

50‧‧‧Resistive components

Ai‧‧‧ address signal

IDS‧‧‧Selection signal

ID‧‧‧ identification signal

Figure 1A is a schematic diagram of the circuit architecture of the prior art identification circuit.

Figure 1B is a circuit diagram showing the connection of the pull-down resistors to the address signals and identification signals of Figure 1A, respectively.

Fig. 2A is a timing chart of the first printing direction address signal shown in Fig. 1A.

Fig. 2B is a timing chart of the second printing direction address signal shown in Fig. 1A.

Figure 3A is a circuit diagram of the identification circuit of the first preferred embodiment of the present invention.

Figure 3B is a circuit diagram showing the connection of the pull-down resistors to the address signals, selection signals, and identification signals of Figure 3A, respectively.

Fig. 4 is a timing chart corresponding to the selection signal, the address signal, and the identification signal shown in Fig. 3.

Figure 5 is a circuit diagram of the identification circuit of the second preferred embodiment of the present invention.

Figure 6 is a circuit diagram of the identification circuit of the third embodiment of the present invention.

Some exemplary embodiments embodying the features and advantages of the present invention are described in detail in the following description. It is to be understood that the present invention is capable of various modifications in the various aspects of the present invention, and the description and illustration are in the nature of

Please refer to FIG. 3A, which is a circuit diagram of the identification circuit of the first preferred embodiment of the present invention. As shown in the figure, the identification circuit 3 of the present invention is applied to an inkjet head (not shown), so that the printer (not shown) recognizes the inkjet head to complete the printing operation, and the identification circuit 3 of the present invention mainly includes the a switching element 30, a fuse 31, a second switching element 32, a ground terminal 33, an address signal Ai, a selection signal IDS, and an identification signal ID, and the first switching element 30 and the second switching element 32 may be, but are not limited to, an N type Gold oxygen half field effect transistor. The first switching element 30 is electrically connected to the fuse 31 and the grounding end 33, and the fuse 31 is configured to receive the identification signal ID. When the identification signal ID is a programming voltage, the fuse 31 is disconnected, and when the fuse 31 is read. , the identification signal ID is read first Taking the voltage, the second switching element 32 is electrically connected to the first switching element 30 and the address signal Ai, and the address signal Ai is when the second switching element 32 is turned on to provide the address signal Ai to the first switching element 30. The driving signal is connected to the second switching element 32 for electrically connecting the second switching element to the enabling or disabling level ( A transition is made between driving to drive the second switching element 32 to be turned on or off.

In this embodiment, the address signal Ai, the selection signal IDS, and the identification signal ID are each connected to a pull-up resistor. Please refer to FIG. 3B, which is a circuit diagram of a pull-down resistor connected to the address signal, the selection signal and the identification signal of FIG. 3A, respectively. As shown in the figure, the pull-down resistors 34 are respectively connected between the address signal Ai and the ground, between the selection signal IDS and the ground, and between the identification signal ID and the ground, mainly for stabilizing the voltage, so that the first switch The component 30 and the second switching component 32 are capable of stable operation.

Please refer to FIG. 4, which is a timing map of the selection signal, the address signal and the identification signal shown in FIG. As shown, the selection signal IDS is converted to an enable level earlier than the address signal Ai, and the selection signal IDS is converted to the disable level later than the address signal Ai, and the address signal Ai is compared to the identification signal. The ID is converted to the enable level early, and the address signal Ai is converted to the disable level later than the identification signal ID, and the timing correspondence between the selection signal IDS, the address signal Ai and the identification signal ID is not in the fourth diagram. Limited.

Referring to FIG. 3A and FIG. 4 again, in the embodiment, when the selection signal IDS is the enable level, the second switching element 32 is turned on, and drives the second switching element 32, when the address signal Ai and the selection When the signal IDS is an enable level, the first switching element 30 is turned on. At this time, when the identification signal ID is the programming voltage, the fuse 31 is in an open circuit, and if the reading of the fuse 31 is performed, the identification signal ID is read. Take the voltage. Furthermore, since the selection signal IDS is converted to the enable level earlier than the address signal Ai, and the selection signal IDS ratio bit The address signal Ai is converted to the disable level later. Therefore, when the selection signal IDS is still enabled, the second switching element 32 is still driven, and the address signal Ai is already disabled. The circuit level between the second switching element 32 and the first switching element 30 is pulled down to the low level of the pull-down resistor 34 (shown in FIG. 3B) of the address signal Ai, thereby making the first The switching element 30 is not turned on, so that the fuse 10 is not blown between the identification signal ID and the ground terminal 33 due to the occurrence of an improper voltage difference, so as to protect the fuse 31 from being burned, and the identification circuit is prevented from being generated. By recognizing the phenomenon of errors, it is possible to reduce the discharge element in which the gate of the first switching element 30 is disposed to reduce the layout area of the identification circuit, thereby reducing the cost of the wafer.

Please refer to FIG. 5, which is a circuit diagram of the identification circuit of the second preferred embodiment of the present invention. As shown in the figure, the identification circuit 4 of the present embodiment differs from the identification circuit 3 of the first preferred embodiment in that it further includes a third switching element 40, wherein the third switching element 40 is coupled to the first switching element 30 and the second The switching element 32 and the ground terminal 41 are electrically connected. In this embodiment, when the selection signal IDS is the enable level, the second switching element 32 is turned on. When the address signal Ai and the selection signal IDS are both enabled, the first switching element 30 and the third switching element 40. All of them are turned on, so that when the identification signal ID is the programming voltage, the fuse 31 is broken, and when the fuse 31 is read, the identification signal ID is the reading voltage. Since the circuit control and the actuating component of the identification circuit 4 of the present embodiment are similar to those of the foregoing embodiment, the similarities are not described herein again, the difference being that the third switching component 40 is connected to the first switching component 30 and the second switching component. 32 and the grounding end 41 are electrically connected. When the circuit between the second switching element 32 and the first switching element 30 still has a voltage level, the third switching element 40 can be self-primed to ground, and the second switching element 32 to the second The circuit voltage level between a switching element 30 is pulled down to a low level, so that the first switching element 30 is indeed not turned on, so that the identification signal ID and the ground terminal are The fuse 10 is not blown between the 33s due to an improper voltage difference, so as to protect the fuse 31 and avoid the recognition error of the identification circuit.

In some embodiments, the identification circuit of the present invention further connects a resistive element to the junction of the second current conducting end of the second switching element and the control end of the first switching element. Please refer to FIG. 6 , which is a circuit diagram of the identification circuit of the third embodiment of the present invention. As shown in the figure, the identification circuit 5 of the present embodiment differs from the identification circuit 3 of the first preferred embodiment in that a resistive element 50 is further included in place of the third switching element 40 of the second preferred embodiment, wherein the resistive element The 50 series is connected between the second switching element 32 and the grounding end 51. In this way, the resistance element 50 can be used to increase the discharge speed, so that the selection signal IDS and the address signal Ai can be simultaneously converted into the enabling level or the inactive level, if the second switching element 32 is between the first switching element 30 and the first switching element 30. When the circuit still has a voltage level, the resistance element 50 can be self-primed to ground, and the circuit voltage level between the second switching element 32 and the first switching element 30 is pulled down to a low level, thereby enabling the A switching element 30 is not turned on, so that the fuse 10 is not blown between the identification signal ID and the ground terminal 33 due to the occurrence of an improper voltage difference, so as to protect the fuse 31 and prevent the identification circuit from generating an identification error. The phenomenon can also improve the reading speed of the identification signal ID.

In summary, the identification circuit applicable to the inkjet head in the present case mainly transmits the second switching element through the selection signal, because the selection signal is converted to the enabling level earlier than the address signal, and the signal ratio is selected. The address signal is later converted to the disable level. Therefore, when the selection signal is still enabled, the second switching element is still driven, and the address signal is already disabled, so that the second switch is passed. The circuit level between the component and the first switching component is pulled down to a low level, so that the first switching component is not turned on, so that the identification signal and the ground terminal are not improperly generated. In the case of voltage difference, the fuse is blown to achieve the purpose of protecting the fuse from being burned, and the recognition circuit is prevented from generating an identification error, and the discharge element of the gate of the first switching element is further reduced to reduce the identification circuit layout. The area, in turn, reduces the cost of the wafer.

This case has been modified by people who are familiar with the technology, but it is not intended to be protected by the scope of the patent application.

3‧‧‧ Identification circuit

30‧‧‧First switching element

31‧‧‧Fuse

32‧‧‧Second switching element

33‧‧‧ Grounding terminal

Claims (5)

An inkjet head identification circuit for receiving an identification signal, an address signal and a selection signal of a printer, the identification circuit comprising: a first switching component, a fuse and a ground terminal Connected to the fuse to receive the identification signal; and a second switching element electrically coupled to the first switching element, the address signal, and the selection signal, the address signal being tied to the second switching element When the current is turned on, the address signal is provided to the first switching element to drive the first switching element to be turned on or not, and the selection signal is used to switch the second element to the enabling level or the inactive level. Converting between driving the second switching element to be turned on or not; wherein the selection signal is converted to an enabling level earlier than the address signal, and the selection signal is later converted to disabled than the address signal Level, and the address signal is converted to an enable level earlier than the identification signal, and the address signal is converted to a disable level later than the identification signal to ensure that the first switching element can be verified during printing Reach or not Used to protect the fuse is not burned and avoid a recognition error identification circuit generates the phenomenon. The identification circuit of claim 1, wherein the first switching element and the second switching element are field effect transistors. The identification circuit of claim 1, further comprising a third switching element electrically connected to the first switching element, the third switching element and the ground. The identification circuit of claim 1, further comprising a resistor element It is connected between the switching element and the ground. The identification circuit of claim 1, further comprising a plurality of pull-down resistors respectively connected between the address signal and the ground, between the selection signal and the ground, and the identification signal Used to stabilize the voltage between the ground and the ground.