1286972 九、發明說明： 【發明所屬之技術領域】 本案係關於一種嘴墨頭識別電路，尤指一種適用於印 表機之喷墨頭識別電路。 【先前技術】 φ 料來隨著個人電腦普及與網際網路的快速發展，嘴 墨印表機目前已成為個人電腦設備中必備的產品。對一般 的使用者來說，-台基本型的喷墨印表機就足以應付各種 - 文件列印的需求。眾所週知，影響喷墨印表機列印品質之 因素有很多，例如墨水的組成，紙張的選擇以及墨水匣之 供墨方式等等。為追求更完美之列印品質，相關研發者已 投入大.量·時間與心力於墨水匣儲墨與讲墨結構設計，q期 能符合結構簡單、製作成本低、高儲墨能力以及高列印品 • 質等要求。 喷墨列印技術發展至今，控制喷墨頭（printhead)釋出 墨滴至喷墨媒體之方式可大致分為兩大主流，其一係為熱 氣泡式（Thermal Bubble Ink Jet)技術，其操作原理係利用加 熱電阻器（thin film resistor)加熱使部分墨水產生氣泡進而 將墨水排擠出，並使之通過複數個喷孔喷至喷墨媒體上。 另一則為壓電致動式（Piezo-electric)技術，其原理是利用壓 電材料的壓電特性，於通電後而將墨水推出喷嘴。 由於每一種類型的喷墨列印技術都需要配合獨特的 1286972 喷墨頭，再加上各種喷墨頭皆有其特殊的規格，包含：結 構、使用的墨水、喷孔數以及喷墨控制電路等特性，因此 需要搭配相容的列印系統，才能正確地完成列印工作，一 般而言，目前的印表機所設置的墨水匣是可以互換或是可 同時承載兩種墨水匣，例如彩色墨水匣可與黑色墨水匣互 換或是可同時承載彩色墨水匣及黑色墨水匣，由於彩色墨 水匣及黑色墨水匣所設置的喷墨頭的規格並不相同，因此 當使用者將墨水匣安裝至印表機上時，印表機内部的控制 電路必須能夠識別墨水匣之喷墨頭的規格，才能使用相對 應的驅動程式進行驅動，故需要一識別電路做為印表機識 別喷墨巔，並將識別電路做為喷墨頭可用於印表機的依 據。 因此，如何發展一種可改善上述習知技術缺失之適用 於印表機之喷畢頭識別電路，實辱目前迫切需畢鮮決之問· 【發明内容】 本案之主要目的在於提供一種適用於印表機之喷墨 頭識別電路，藉由計數電路及編碼電路來依序輸出關於喷 墨頭資訊之控制信號，並透過輸出電路提供給印表機電路 代表該喷墨頭之複數個識別信號，使印表機電路藉由複數 個識別信號來辨識喷墨頭的種類，使印表機與喷墨頭間有 良好的搭配，並藉此達到識別喷墨頭的目的。 為達上述目的，本案之一較廣義實施樣態為提供一種喷墨頭 1286972 識別電路，其係適用於-喷墨頭且與1表機電路連接， 用以接收該印表機電路所傳送之一第一時脈信號、一第二 時脈信號、-負載信號以及-電壓源，其係一^ 電路，其係接收該第-時脈信號、該第二時脈信號以及該 負載信號，因應該第一時脈信號、該第_ : 負载松唬之觸發而並行輸出複數個第一控制信號；一編碼 電路’其係與該計數電路連接’用以接收該複數u個第、一控 制信號並串列輪出一第二控制信號，·以及一輪出電路，^ 係與該編碼電路及該印表機電路連接，用以因應該第二^ 制信號依序輸出代表該喷墨頭之識別信號；其中，該印表 機電路係籍由該複數個識別信號來辨識該噴墨頭的=類。 【實施方式】 •體現本案特徵與優點的實施例將在後段的說明中詳 細敘述。應理解的是本案能夠在不同的態樣上具有各種的 變化，其皆不脫離本案的範圍，且其中的說明及圖示在本 質上係當作說明之用，而非用以限制本案。 明參閱第一圖，其係為本案較佳實施例之噴墨頭識別 電路之電路方塊示意圖，如第一圖所示，本案較佳實施例 之喷墨頭識別電路10主要係設置於一喷墨頭（未圖示） 内部且與印表機電路（未圖示）連接，並接收印表機電路 經由輸入端14所輸入之第一時脈信號（cikl)、輪入端15 所輪入之第二時脈信號(Clk2)、輸入端16所輸入之負载信 1286972 號（Load)以及電源端17所輸入之電壓源(vdd)，本案之 喷墨頭識別電路10係由計數電路U、編碼電路12以及輸 出電路13所構成，用以依序串列輸出代表喷墨頭之複數 個識別信號至印表機電路，使印表機電路可藉由該複數個 識別信號來辨識該喷墨頭的種類，進而正確地控制該喷墨 頭運作。 計數電路11係由一個第一計數器m以及複數個第二 _ 計數器112所構成，於本案實施例中，計數電路η内部係 包含4個計數器，第一計數器係接收第一時脈信號 (Clkl)、第二時脈信號（Cik2)以及負載信號(Load)，並因 應第一時脈信號（Clkl)、第二時脈信號(Clk2)以及負载信 號(Load)對其内部電路之觸發而輸出一第一控制信號，即 第1位元開關訊號，至編碼電路12以及與其連接之第二 計數琴112的輸入端（in)。 請參閱第二圖，其係為第一圖所示之第一計數器之電 • 路結構圖，如圖所示，第一計數器111係包含接收第一時 脈信號（Clkl)之輸入端14、接收第二時脈信號（Clk2)之 輸入端15、接收負載信號（Load)之輸入端16、提供電 壓源(Vdd)之電源端17、用以輸出第一控制信號之輸出端 (Out)llll、接地端1112、第一開關電晶體A1、第二開關 電晶體A2、第三開關電晶體A3、第一負載電晶體T1、第 四開關電晶體A4、第五開關電晶體A5、弟^一負載電晶體 T2、第六開關電晶體A6以及第七開關電晶體A7。 第一開關電晶體A1具有一源極(Source)、接收負載信 ---------- 1286972 一閘極(Gate)以及接收電壓源(Vdd)之一汲^ (Drain)T^X^lf^晶體 Α1 —— '— 之源極連接之一汲極、接收第二時脈信號（Clk2)之閘極以 及與接地端1112連接之一源極；第三開關電晶體A3具有 一没極、與第一開關電晶體A1之源極及第二開關電晶體 A2之汲極連接之一閘極以及與接地端m2連接之一源 極；第一負載電晶體T1具有與電源端17連接之該閘極和 # 没極’以及與第三開關電晶體A3之汲極連接之源極；第 四開關電晶體A4具有一源極、接收第一時脈信號（clkl) 之閘極以及與第三開關電晶體A3之汲極及第一負載電晶 體tl之源極連接之一汲極；第五開關電晶體A5具有一汲 極、與第四開關電晶體A4之源極連接之一閘極以及與接 地端1112連接之一源極；第二負載電晶體丁2具有與電源 端17連接冬閘極和汲極，以及與第五開關零晶體A5之汲 極連接之源極；第六開關電晶體a6具有與輸出端ml連 鲁接之-源極、接收第二時脈信號（clk2)之一閑極以及與 第五開關電晶體A5之〉及極及第二負載電晶體T2之源極連 接之一/及極’第七開關電晶體Α7具有與第六開關電晶體 Α6之源極及輸出# mi連接之一没極、接收 負載信號 (Load)之閘極與接地端ιιΐ2連接之一源極) 议明再參閱第—圖，第二計數器112除了接收第一時脈 信號（Clkl)、第二時脈信號(Clk2)以及負載信號(Load)之 外，更接收前一個計數器所輸出之控制信號，並因應該第 一時脈&號（Qkl )、第二時脈信號(Clk2)、負載信號(Load) 1286972 以及別-級計數器輪出之第一控制信號之觸發而並行輸 出3個第-控制信號至編碼電路12，即第2〜4位元開關 .訊號’舉例而言’第—個第二計數器112將接收第一時脈 信號（衝）、第二時脈信號(do、負載信號①㈣以及 第-計數器111所輸出之第一個第一控制信號，經内部電 路運作後輸出第二個第-控制信號，即第2位元開關訊 號，至編碼電路12以及與其連接之下一級第二計數器112 φ 的輸入端（In) 1121，至於後續的第二計數器II2的運作 方式以此類推，於此不再贅述。 請參閲第三圖，其係為第一圖所示之第二計數器之電 路結構_ ’如圖所示，第一圖所示之每一第二計數器112 係包含接收第一時脈信號（Clkl)之輸入端14、接收第二 時脈彳&號(Clk2)之輸入端15、接收負載信號（Load)之輸 •入端I6、提供電壓源(Vdd)之電源端π ·、用以犖收前一級 計數器所輸出之第一控制信號之輸入端（In) 1121、用以 * 輸出第一控制信號之輸出端（〇ut)1122、接地端1123、第三 負載電晶體T3、第八開關電晶體A8、第九開關電晶體A9、 第十開關電晶體A10、第四負載電晶體T4、第十一開關電 晶體All、第十二開關電晶體A12。 第三負載電晶體T3具有一源極，以及與電源端17連 接之該閘極和汲極；第八開關電晶體A8具有與第三負载 電晶體T3之源極連接之一汲極、接收前一級計數器所輸 出之第一控制信號之一閘極以及與接地端1123連接之— 源極；第九開關電晶體A9具有一源極、接收第一時脈信 11 1286972 號之一閘極以及與第八開關電晶體A8之汲極及第三負載 電晶體T3之源極連接之一汲極；第十開關電晶體A10具 有一汲極、與第九開關電晶體A9之源極連接之一閘極以 及與接地端1123連接之一源極，·第四負載電晶體T4具有 與電源端17連接之閘極和汲極，以及與第十開關電晶體 A10之汲極連接之源極；第十一開關電晶體AU具有一源 極、接收第二時脈信號之一閘極以及與第十開關電晶體 • A10之汲極及第四負載電晶體T4之源極連接之一汲極； 第十二開關電晶體A12具有與第十一開關電晶體All之源 極及輸出端1122連接之一汲極、接收負载信號之一閘極 與該接地端1123連接之一源極。 請再參閱第一圖，編碼電路12係與計數電路η及輸 出電路13連接，且由4個開關電晶體Μ3〜Μό所構成， 每一旬開關'電晶體M3〜Μ6·均分別與其相對應之計數器的 • * * 鲁 輸出端連接，用以接收第一控制信號並依序串列輸出第二 控制信號，其中，開關電晶體M3〜Μ6的閘極分別連接至 相對應的計數器的輸出端，汲極則依編碼設定連接至電源 端17或接地端，以接收電壓源(Vdd)或接地端的訊號，而 源極則連接至輸出電路13。 輪出電路13係與編碼電路12及印表機電路連接，且 係由第一開關電晶體Ml及第二開關電晶體M2所組成， 主要用來接收輸入端16所輸入之負載信號以及編碼電路 U所依序串列輸出之第二控制信號，並因應第二控制信號 依序輪出代表喷墨頭之複數個識別信號至印表機電路，使 12 1286972 印表機電路可藉由該複數個識別信號來辨識該喷墨頭的 種類，進而正確地控制該喷墨頭運作。 其中，第二開關電晶體M2的汲極係與編碼電路12 的開關電晶體M3〜M6的源極連接、閘極則與輸入端16 連接，用以接收負載信號，而源極則與接地端連接，而第 二開關電晶體M2的作用係為當輸入端16輸入之負載信號 為高電壓信號時，第二開關電晶體M2將動作，用以將輸 _ 出序列節點（Out-1 ist node )上的信號重置（reset ); 第一開關電晶體Ml的閘極係與編碼電路12的開關電晶體 M3〜M6的源極連接，汲極則與輸出端18連接，而源極同 • · - 樣輿接地端連接，其中輸出端18係與印表機電路連接， 用以輸出代表喷墨頭之複數個識別信號至印表機電路。 請參閱第二圖並請配合第一圖及第四圖，其中第四圖 •係為第一時脈信號、第二時脈信號以及負載信號之信號波 . . ^ * 形圖，以下將說明第二圖所示之第一計數器111的作動方 • 式： (1)負載信號輸入高電壓（high)信號： 1.當輸入端16接收之負載信號為高電壓信號，且輸 入端15接收之第二時脈信號為低電壓信號時，第一開關 電晶體A1將導通，使電源端17提供的電壓源（Vdd)信號 傳入第三開關電晶體A3的閘極端，即第一計數器111輸 入高電壓信號至第三開關電晶體A3，如此第三開關電晶體 A3則動作，並將低電壓（low)信號傳至第四開關電晶體 13 1286972 A4與第一負载電晶體n相接的一端，至於 :11的輸出端’由於輸入端16接收之負載信號為高電十壓; "因此第七開關電晶體A7動作，將輸出端U11做重置 的動作； 2·當第一時脈信號為高電壓信號時，因第四開關電晶 體A4動作’且因第四開關電晶體A4與第一負載電晶體η 相接的端為低電壓信號，故將低電壓信號傳到第五開關 電晶體Α5的閘極’使第五開關電晶體Α5無法動作，故低 電壓信號信號將與第六開關電晶體Α6與第二負載電晶體 Τ2相接的那一端隔離； 3·當第二時脈信號為高電壓信號時，在第一計數器 111之輸出端1111，因第五開關電晶體Α5無法動作且第 六開關電晶體Α6動作，故電源端17的高電壓信號，即電 舉源’（Vdd)，經過第二負載電晶體Τ2及第六開關電晶體 A6傳至輸出端mi，至於，在第一計數器m的輸入端 15 ’因第二時脈信號為高電壓信號，故第二開關電晶體A2 動作，將使第三開關電晶體A3之閘極端為低電壓信號， 即第一計數器111輸入低電壓信號至第三開關電晶體A3。 (2)負載信號輸入低電壓信號： 1·當輸入端16接收之負載信號為低電壓信號，且輸 入端15接收之第二時脈信號為高電壓信號時，第二開關 電晶體A2將導通，使接地端m2的低電壓信號傳入第三 開關電晶體A3的閘極端，如此第三開關電晶體A3則無 1286972 法動作； 2·當輸入端16接收之負載信號為低電壓信號，且第 知脈彳㊁號為尚電壓信號時，因第三開關電晶體A3無法 動作’則電源端17的高電壓信號，即電壓源（Vdd)，將 、、二過第一負載電晶體T1及第四開關電晶體A4傳到第五開 關電晶體A5的閘極端，使第五開關電晶體A5動作，並將 低電壓k號傳至第六開關電晶體A6與第二負載電晶體η 相接的一端； 3·第二時脈信號為高電壓信號時，第六開關電晶體A6 將動作，且因第六開關電晶體…與第二負载電晶體以相 接的那一 4為低電壓信號，故將低電壓信號傳至輸出端 111卜 .明參閱弟二圖並請配合第一岡及第四圖，以下將說明 第三圖所示之第二計數器112的作動方式： (1)當輸入端16接收之負載信號為高電壓信號時，第一 。十數裔111的第七開關電晶體A7以及第二計數器112之 第十二開關電晶體A12將導通，使接地端1123的信號傳 入其下一級的第二計數器112之第八開關電晶體A8的閘 極端，如此一來第八開關電晶體A8的閘極端將為低電壓 信號，即每一第二計數器112之輸入端為 1121輸入低電 壓信號，而在後續第二時脈信號為高電壓信號時，每一第 一計數器112的輸入端（In) Π21將接收其前一個計數器 15 1286972 之輸出端的信號（如第一圖所示）。 (2) 當輸入端1121輸入高電壓信號時： 1·當輸入端1121輸入高電壓信號時，第八開關電晶 體A8則動作，使第九開關電晶體A9與第三負載電晶體T3 相接的一端接收到低電壓信號； 2·當第一時脈信號為高電壓信號時，則第九開關電晶 體A9導通，進而將低電壓信號傳至第十開關電晶體A1〇 # 的閘極’使第十開關電晶體A10無法動作，則接地端u23 的信號將與第Η 開關電晶體All隔離； • 3·當第二時脈信號為高電壓信號時，第十一開關電晶 體All動作，則將電源端17所提供之電壓源（Vdd)的高電 壓信號經過第四負載電晶體T4及第十一開關電晶體All 傳至輸出端1122。 • * - * . 鲁 (3) 當輸入端1121輸入低電壓信號時： 鲁 1·當輸入端1121輸入信號為低電壓時，第八開關電 晶體A8則無法動作，使第九開關電晶體A9與第三負載電 晶體T3相接的一端與接地端1123信號隔離； 2·當第一時脈信號輸入高電壓信號時，則第九開關電 晶體A9導通，進而將電源端17所提供之電壓源（Vdd)的 高電壓信號經過第三負載電晶體T3及第九開關電晶體A9 傳至第十開關電晶體A10的閘極端，使第十開關電晶體A10 動作，如此一來，第十一開關電晶體Al 1與第四負載電晶 體T4相接的一端將接收到接地端1123的低電壓信號； 16 1286972 3.當第二時脈信號輸入高電壓信號時，第十一開關電 晶體All將動作，進而將低電壓信號經過第十一開關電晶 體All傳至輸出端1122。 另外，第十二開關電晶體A12的設計作用係為，當輸 入端16輸入的負載信號為高電壓信號時，則將驅動第十 二開關電晶體A12動作，用以將輸出端1122做重置 (reset)的動作。 籲 請再參閱第一圖並請配合上述第二圖及第三圖的動 作說明，第一圖其動作方式係為：經由第一計數器111的 運算，輸出端1111將輸出一第一個第一控制信號，即第 一位元開關訊號，到下一級的第二計數器112,且將第一 控制信號也送至編碼電路12之開關電晶體M3的閘極端， 若第一計數器111的輸出端1111輸出的第一個第一控制 ‘信號為高電壓信號，其餘第一控制信號為低電壓信號，則 . . * - ^ 編碼電路12之開關電晶體M3將動作，但開關電晶體M4 • 〜M6不動作，故將開關電晶體M3汲極端信號，在此實施 例中為電源端17所提供之電壓源(Vdd)信號經開關電晶體 M3傳至輸出電路13之第一開關電晶體Ml的閘極端，使 第一開關電晶體Ml動作，如此本案喷墨頭識別電路10 之輸出端18的信號將與接地端相連； 反之，若第一計數器111的輸出端1111輸出的第一 個第一控制信號為低電壓信號，其餘第一控制信號亦為低 電壓信號’則編碼電路12之開關電晶體Μ 3將無法動作’ 且開關電晶體Μ4〜Μ6亦不動作，故開關電晶體M3汲極端 17 1286972 信號，在此實施例中為電源端17，及開關電晶體M4〜M6 汲極端信號無法傳至輸出電路13之第一開關電晶體Ml 的閘極端，使第一開關電晶體Ml無法動作，如此一來， 喷墨頭識別電路1〇之輸出端18的輸出信號將不受影響。 至於，其它3個第二計數器112及開關電晶體M4、M5以 及M6與輸出電路13之第一開關電晶體Ml的配合作動方 式係與上述相同，於此不再贅述。 • 故於本案實施例中，第一圖所示之喷墨頭識別電路10 之輸出電路13内部之輸出序列節點依序接收到的信號為 high、high、low、high，相對的經由第一開關電晶體M1 處理後輸出信號將變化為low、low、high、low，即輸出 端18將依序串列輸出代表喷墨頭之識別信號為1〇w、1〇w、 high、low ’當印表機電路接收到此識別信號後，則可判別 噴墨頭是否可用於此印表機上，使印表機與喷墨頭間有良 好的搭配，並藉此達到識別喷墨頭的目的。 •综上所述’本案適用於印表機之喷墨頭識別電路是以 計數電路及編碼電路來依序輸出關於喷墨頭資訊之控制 信號，並透過輸出電路提供給印表機電路代表該噴墨頭之 複數個識別信號，使印表機電路藉由複數個識別信號來辨 識喷墨頭的種類，使印表機與噴墨頭間有良好的搭配，並 藉此達到識別喷墨頭的目的。本案適用於印表機之喷墨頭 識別電路極具產業之價值，爰依法提出申請。 、 本案得由熟知此技術之人士任施匠思而為諸般修 飾，然皆不脫如附申請專利範圍所欲保護者。 18 1286972 【圖式簡單說明】 第一圖：其係為本案較佳實施例之喷墨頭識別電路之電路 方塊示意圖。 第二圖：其係為第一圖所示之第一計數器之電路結構圖。 第三圖：其係為第一圖所示之第二計數器之電路結構圖。 第四圖··其係為第一圖運作之第一時脈信號、第二時脈信號 以及負載信號之信號波形圖。1286972 IX. Description of the invention: [Technical field to which the invention pertains] The present invention relates to a nozzle ink recognition circuit, and more particularly to an inkjet head recognition circuit suitable for a printer. [Prior Art] With the popularity of personal computers and the rapid development of the Internet, the ink printer has become an essential product in personal computer equipment. For the average user, the basic inkjet printer is sufficient for a variety of - document printing needs. It is well known that there are many factors that affect the print quality of inkjet printers, such as the composition of the ink, the choice of paper, and the ink supply method of the ink cartridge. In order to pursue a more perfect print quality, the relevant developers have invested a large amount of time, time and effort in the ink 匣 ink storage and ink structure design, q phase can meet the simple structure, low production cost, high ink storage capacity and high column Printed goods, quality and other requirements. Since the development of inkjet printing technology, the way to control the inkjet head to discharge ink droplets to the inkjet media can be roughly divided into two major mainstreams, one of which is the Thermal Bubble Ink Jet technology, which operates. The principle is that a portion of the ink is bubbled by heating with a thin film resistor to extrude the ink, and is sprayed onto the inkjet medium through a plurality of orifices. The other is the Piezo-electric technology, which uses the piezoelectric properties of the piezoelectric material to push the ink out of the nozzle after energization. Since each type of inkjet printing technology requires a unique 1286972 inkjet head, plus a variety of inkjet heads have their own specifications, including: structure, ink used, number of orifices, and inkjet control circuitry. Other characteristics, so it is necessary to use a compatible printing system to complete the printing work correctly. Generally speaking, the ink cartridges set by the current printer are interchangeable or can carry two ink cartridges at the same time, such as color. The ink cartridge can be interchanged with the black ink cartridge or can carry both the color ink cartridge and the black ink cartridge. Since the ink cartridges of the color ink cartridge and the black ink cartridge are different in specifications, the user installs the ink cartridge to the ink cartridge. When the printer is on the printer, the control circuit inside the printer must be able to recognize the specifications of the inkjet head of the ink cartridge, so that the corresponding driver can be used for driving. Therefore, an identification circuit is required as the printer to recognize the inkjet cartridge. And the identification circuit is used as the basis for the inkjet head to be used for the printer. Therefore, how to develop a spray-head recognition circuit suitable for a printer can be improved by the above-mentioned conventional techniques, and it is urgent to ask for a fresh question. [Inventive content] The main purpose of the present invention is to provide a suitable printing The inkjet head recognition circuit of the watch machine sequentially outputs the control signal about the inkjet head information by the counting circuit and the encoding circuit, and supplies the plurality of identification signals representing the inkjet head to the printer circuit through the output circuit. The printer circuit is used to identify the type of the inkjet head by a plurality of identification signals, so that the printer and the inkjet head have a good match, thereby achieving the purpose of identifying the inkjet head. In order to achieve the above object, one of the more general embodiments of the present invention provides an inkjet head 1286972 identification circuit suitable for use in an inkjet head and connected to a meter circuit for receiving the transmission of the printer circuit. a first clock signal, a second clock signal, a load signal, and a voltage source, which are a circuit that receives the first clock signal, the second clock signal, and the load signal, a plurality of first control signals should be output in parallel according to the first clock signal, the trigger of the _: load load; an encoding circuit 'connected to the counting circuit' for receiving the plurality of first and first control signals And serially outputting a second control signal, and a round-out circuit, connected to the encoding circuit and the printer circuit, for sequentially indicating the identification of the inkjet head according to the second control signal a signal; wherein the printer circuit identifies the class of the inkjet head by the plurality of identification signals. [Embodiment] An embodiment embodying the features and advantages of the present invention will be described in detail in the following description. It is to be understood that the present invention is capable of various modifications in various embodiments and is not intended to limit the scope of the invention. Referring to the first drawing, which is a circuit block diagram of the ink jet head identification circuit of the preferred embodiment of the present invention, as shown in the first figure, the ink jet head identification circuit 10 of the preferred embodiment of the present invention is mainly disposed in a spray. The ink head (not shown) is internally connected to the printer circuit (not shown), and receives the first clock signal (cikl) input by the printer circuit via the input terminal 14, and the wheeled end 15 is rotated. The second clock signal (Clk2), the load signal input to the input terminal 16 (12847), and the voltage source (vdd) input from the power terminal 17, the inkjet head identification circuit 10 of the present invention is composed of the counting circuit U, The encoding circuit 12 and the output circuit 13 are configured to serially output a plurality of identification signals representing the inkjet head to the printer circuit, so that the printer circuit can identify the inkjet by the plurality of identification signals. The type of head, which in turn controls the operation of the inkjet head. The counting circuit 11 is composed of a first counter m and a plurality of second_counters 112. In the embodiment of the present invention, the counting circuit η internally includes four counters, and the first counter receives the first clock signal (Clkl). a second clock signal (Cik2) and a load signal (Load), and outputting a trigger for the internal circuit of the first clock signal (Clkl), the second clock signal (Clk2), and the load signal (Load) The first control signal, i.e., the first bit switching signal, is coupled to the encoding circuit 12 and the input terminal (in) of the second counter 112 connected thereto. Please refer to the second figure, which is a circuit diagram of the first counter shown in the first figure. As shown, the first counter 111 includes an input terminal 14 for receiving a first clock signal (Clkl), An input terminal 15 for receiving the second clock signal (Clk2), an input terminal 16 for receiving a load signal (Load), a power terminal 17 for supplying a voltage source (Vdd), and an output terminal for outputting the first control signal (Out) 111 , the grounding terminal 1112, the first switching transistor A1, the second switching transistor A2, the third switching transistor A3, the first load transistor T1, the fourth switching transistor A4, the fifth switching transistor A5, and the other The load transistor T2, the sixth switching transistor A6, and the seventh switching transistor A7. The first switching transistor A1 has a source (Source), a receiving load signal---------- 1286972 a gate (Gate) and a receiving voltage source (Vdd) 汲^ (Drain) T^ X^lf^ crystal Α1 —— '- the source is connected to one of the drains, the gate receiving the second clock signal (Clk2) and one source connected to the ground terminal 1112; the third switching transistor A3 has a a gate electrode connected to the drain of the first switching transistor A1 and the second switching transistor A2 and a source connected to the ground terminal m2; the first load transistor T1 has a power supply terminal 17 Connecting the gate and #无极' and a source connected to the drain of the third switching transistor A3; the fourth switching transistor A4 has a source, a gate receiving the first clock signal (clkl), and One of the drains connected to the drain of the third switching transistor A3 and the source of the first load transistor t1; the fifth switching transistor A5 has a drain and one of the sources connected to the fourth switching transistor A4 a gate and a source connected to the ground terminal 1112; the second load transistor 2 has a winter gate and a drain connected to the power terminal 17, and The fifth switch zero crystal A5 is connected to the source of the drain; the sixth switch transistor a6 has a source connected to the output terminal ml, a source, a second clock signal (clk2), and a fifth switch. One of the connection of the transistor A5 and the source of the second and second load transistor T2/the pole 'the seventh switch transistor Α7 has one of the source and the output of the sixth switch transistor Α6 The gate of the receiving load signal (Load) is connected to one of the sources of the ground terminal ιι 2). Referring again to the first diagram, the second counter 112 receives the first clock signal (Clkl) and the second clock signal (Clk2). In addition to the load signal (Load), it receives the control signal output by the previous counter, and responds to the first clock & number (Qkl), the second clock signal (Clk2), and the load signal (Load) 1286972. And triggering the first control signal of the other-stage counter to output three first-control signals to the encoding circuit 12 in parallel, that is, the second to fourth bit switches. The signal 'for example, the first second counter 112 Will receive the first clock signal (rush), the second clock signal (do, load letter 1 (4) and the first first control signal outputted by the first counter 111 is outputted by the internal circuit to output a second first control signal, that is, the second bit switching signal, to the encoding circuit 12 and the first stage connected thereto The input end (In) 1121 of the second counter 112 φ, as for the operation mode of the subsequent second counter II2, and so on, will not be described here. Please refer to the third figure, which is the second figure shown in the first figure. Circuit structure of the counter _ 'As shown, each second counter 112 shown in the first figure includes an input terminal 14 that receives the first clock signal (Clk1) and a second clock 彳 & number (Clk2) The input terminal 15 of the receiving load signal (Load), the power receiving terminal I6 of the voltage source (Vdd), and the input terminal for receiving the first control signal output by the previous stage counter (In 1121, an output terminal (〇ut) 1122 for outputting the first control signal, a grounding terminal 1123, a third load transistor T3, an eighth switching transistor A8, a ninth switching transistor A9, and a tenth switching transistor A10, fourth load transistor T4, eleventh switch transistor Body All, the twelfth switching transistor A12. The third load transistor T3 has a source and the gate and the drain connected to the power terminal 17; the eighth switch transistor A8 has a drain connected to the source of the third load transistor T3, before receiving a gate of the first control signal outputted by the first stage counter and a source connected to the ground terminal 1123; the ninth switch transistor A9 has a source, receives a gate of the first clock signal 11 1286972, and The drain of the eighth switching transistor A8 and the source of the third load transistor T3 are connected to one of the drain electrodes; the tenth switching transistor A10 has a drain and a gate connected to the source of the ninth switching transistor A9. a pole and a source connected to the ground terminal 1123, the fourth load transistor T4 has a gate and a drain connected to the power terminal 17, and a source connected to the drain of the tenth switch transistor A10; a switching transistor AU has a source, a gate receiving a second clock signal, and a drain connected to a source of the tenth switch transistor A10 and the fourth load transistor T4; The second switching transistor A12 has the eleventh switching transistor All One of a source and a drain connected to an output terminal 1122, electrode 1123 is connected to the ground terminal, one signal source receiving one load gate. Referring to the first figure, the encoding circuit 12 is connected to the counting circuit η and the output circuit 13, and is composed of four switching transistors Μ3~Μό, each of which corresponds to the transistors M3~Μ6· respectively. The counter of the counter is connected to receive the first control signal and serially output the second control signal, wherein the gates of the switching transistors M3 to Μ6 are respectively connected to the output ends of the corresponding counters. The bungee is connected to the power terminal 17 or the ground terminal according to the code setting to receive the signal of the voltage source (Vdd) or the ground, and the source is connected to the output circuit 13. The turn-out circuit 13 is connected to the encoding circuit 12 and the printer circuit, and is composed of a first switching transistor M1 and a second switching transistor M2, and is mainly used for receiving the load signal input by the input terminal 16 and the encoding circuit. U sequentially outputs the second control signal in sequence, and sequentially rotates a plurality of identification signals representing the inkjet head to the printer circuit in response to the second control signal, so that the 12 1286972 printer circuit can be used by the plural An identification signal is used to identify the type of the ink jet head, thereby properly controlling the operation of the ink jet head. The drain of the second switching transistor M2 is connected to the source of the switching transistors M3 M M6 of the encoding circuit 12, and the gate is connected to the input terminal 16 for receiving the load signal, and the source and the ground are connected. Connected, and the second switching transistor M2 functions as the load signal input to the input terminal 16 is a high voltage signal, the second switching transistor M2 will act to output the output node (Out-1 ist node) The signal on the reset (reset); the gate of the first switching transistor M1 is connected to the source of the switching transistors M3 M M6 of the encoding circuit 12, and the drain is connected to the output terminal 18, and the source is the same - - 舆 ground connection, wherein the output 18 is connected to the printer circuit for outputting a plurality of identification signals representing the inkjet head to the printer circuit. Please refer to the second figure and please cooperate with the first picture and the fourth picture. The fourth picture is the signal wave of the first clock signal, the second clock signal and the load signal. ^ * Figure, the following will explain The operation of the first counter 111 shown in the second figure is: (1) The load signal inputs a high voltage signal: 1. When the input signal received by the input terminal 16 is a high voltage signal, and the input terminal 15 receives the signal. When the second clock signal is a low voltage signal, the first switching transistor A1 will be turned on, so that the voltage source (Vdd) signal provided by the power terminal 17 is transmitted to the gate terminal of the third switching transistor A3, that is, the first counter 111 is input. The high voltage signal is sent to the third switching transistor A3, so that the third switching transistor A3 operates, and the low voltage signal is transmitted to the end of the fourth switching transistor 13 1286972 A4 connected to the first load transistor n As for: 11 output terminal 'since the load signal received by the input terminal 16 is high voltage ten voltage; " therefore the seventh switch transistor A7 action, the output terminal U11 to reset action; 2 · when the first clock When the signal is a high voltage signal, due to the fourth switching transistor The A4 action 'and the end of the fourth switching transistor A4 connected to the first load transistor η is a low voltage signal, so the low voltage signal is transmitted to the gate of the fifth switching transistor Α5 to make the fifth switching transistor Α5 cannot operate, so the low voltage signal signal will be isolated from the end of the sixth switching transistor Α6 and the second load transistor Τ2; 3. When the second clock signal is a high voltage signal, at the first counter 111 The output terminal 1111, because the fifth switch transistor Α5 is inoperable and the sixth switch transistor Α6 is operated, the high voltage signal of the power terminal 17, that is, the electric source '(Vdd), passes through the second load transistor Τ2 and the The six-switch transistor A6 is transmitted to the output terminal mi. As a result, at the input terminal 15' of the first counter m, since the second clock signal is a high voltage signal, the second switching transistor A2 acts to make the third switching transistor The gate of A3 is a low voltage signal, that is, the first counter 111 inputs a low voltage signal to the third switching transistor A3. (2) Load signal input low voltage signal: 1. When the load signal received by the input terminal 16 is a low voltage signal, and the second clock signal received by the input terminal 15 is a high voltage signal, the second switching transistor A2 will be turned on. , the low voltage signal of the ground terminal m2 is transmitted to the gate terminal of the third switching transistor A3, so that the third switching transistor A3 has no 1286972 method; 2. The load signal received by the input terminal 16 is a low voltage signal, and When the second pulse is the voltage signal, the third switch transistor A3 cannot operate, then the high voltage signal of the power terminal 17, that is, the voltage source (Vdd), will pass through the first load transistor T1 and The fourth switching transistor A4 is transmitted to the gate terminal of the fifth switching transistor A5 to operate the fifth switching transistor A5, and the low voltage k number is transmitted to the sixth switching transistor A6 to be connected to the second load transistor η. One end; 3) When the second clock signal is a high voltage signal, the sixth switching transistor A6 will operate, and the fourth switching transistor... and the second load transistor are connected to each other as a low voltage signal. Therefore, the low voltage signal is transmitted to the output terminal 111. Please refer to the second figure and please cooperate with the first and fourth figures. The following describes the operation of the second counter 112 shown in the third figure: (1) When the load signal received by the input terminal 16 is a high voltage signal ,the first. The seventh switch transistor A7 of the fifteen 111 and the twelfth switch transistor A12 of the second counter 112 will be turned on, so that the signal of the ground terminal 1123 is transmitted to the eighth switch transistor A8 of the second counter 112 of the next stage. The gate terminal is such that the gate terminal of the eighth switching transistor A8 will be a low voltage signal, that is, the input of each second counter 112 is a low voltage signal of 1121, and the subsequent second clock signal is a high voltage. At the time of the signal, the input (In) Π21 of each first counter 112 will receive the signal at the output of its previous counter 15 1286972 (as shown in the first figure). (2) When the input terminal 1121 inputs a high voltage signal: 1. When the input terminal 1121 inputs a high voltage signal, the eighth switching transistor A8 operates to connect the ninth switching transistor A9 with the third load transistor T3. One end receives a low voltage signal; 2. When the first clock signal is a high voltage signal, the ninth switching transistor A9 is turned on, and then the low voltage signal is transmitted to the gate of the tenth switching transistor A1〇# When the tenth switch transistor A10 is inoperable, the signal of the ground terminal u23 will be isolated from the second switch transistor A1; • 3. When the second clock signal is a high voltage signal, the eleventh switch transistor All operates. Then, the high voltage signal of the voltage source (Vdd) provided by the power terminal 17 is transmitted to the output terminal 1122 through the fourth load transistor T4 and the eleventh switch transistor A1. • * - * . Lu (3) When the input terminal 1121 inputs a low voltage signal: Lu 1 · When the input terminal 1121 input signal is low voltage, the eighth switch transistor A8 cannot operate, so that the ninth switch transistor A9 The end connected to the third load transistor T3 is isolated from the ground terminal 1123; 2. When the first clock signal is input with a high voltage signal, the ninth switch transistor A9 is turned on, and the voltage supplied from the power terminal 17 is further supplied. The high voltage signal of the source (Vdd) is transmitted to the gate terminal of the tenth switching transistor A10 through the third load transistor T3 and the ninth switching transistor A9, so that the tenth switching transistor A10 operates, and thus, the eleventh The end of the switching transistor A1 and the fourth load transistor T4 will receive the low voltage signal of the ground terminal 1123; 16 1286972 3. When the second clock signal is input to the high voltage signal, the eleventh switch transistor All The action is performed to pass the low voltage signal through the eleventh switching transistor A1 to the output terminal 1122. In addition, the twelfth switching transistor A12 is designed to operate when the load signal input to the input terminal 16 is a high voltage signal, and the twelfth switching transistor A12 is driven to reset the output terminal 1122. (reset) action. Please refer to the first figure and please cooperate with the operation descriptions of the above second and third figures. The first mode is operated by the operation of the first counter 111, and the output terminal 1111 will output a first first control. The signal, that is, the first bit switching signal, goes to the second counter 112 of the next stage, and also sends the first control signal to the gate terminal of the switching transistor M3 of the encoding circuit 12, if the output terminal 1111 of the first counter 111 outputs The first first control 'signal is a high voltage signal, and the remaining first control signal is a low voltage signal, then . . . - - ^ The switching transistor M3 of the encoding circuit 12 will operate, but the switching transistor M4 • ~ M6 does not Action, so the switching transistor M3 汲 extreme signal, in this embodiment, the voltage source (Vdd) signal provided by the power supply terminal 17 is transmitted to the gate terminal of the first switching transistor M1 of the output circuit 13 via the switching transistor M3. The first switching transistor M1 is operated, so that the signal of the output terminal 18 of the inkjet head recognition circuit 10 of the present invention is connected to the ground terminal; conversely, if the first first control signal is outputted from the output terminal 1111 of the first counter 111 Low The voltage signal, the remaining first control signal is also a low voltage signal 'the switching transistor Μ 3 of the encoding circuit 12 will not operate' and the switching transistor Μ4~Μ6 will not operate, so the switching transistor M3 汲 extreme 17 1286972 signal, In this embodiment, the power supply terminal 17 and the switching transistors M4 to M6 汲 the extreme signal cannot be transmitted to the gate terminal of the first switching transistor M1 of the output circuit 13, so that the first switching transistor M1 cannot be operated, thus The output signal of the output terminal 18 of the ink jet head recognition circuit 1 will not be affected. The other two second counters 112 and the switching transistors M4, M5 and M6 and the first switching transistor M1 of the output circuit 13 are the same as described above, and will not be described again. In the embodiment of the present invention, the output sequence nodes in the output circuit 13 of the inkjet head recognition circuit 10 shown in the first figure sequentially receive signals of high, high, low, and high, and the first ones are via the first switch. After the transistor M1 is processed, the output signal will change to low, low, high, low, that is, the output terminal 18 will serially output the identification signals representing the inkjet head as 1 〇 w, 1 〇 w, high, low ' After receiving the identification signal, the watch circuit can determine whether the inkjet head can be used on the printer, so that the printer and the inkjet head have a good match, thereby achieving the purpose of identifying the inkjet head. • In summary, the inkjet head identification circuit applied to the printer is a control circuit for outputting information about the inkjet head in sequence by the counting circuit and the encoding circuit, and is provided to the printer circuit through the output circuit. The plurality of identification signals of the inkjet head enable the printer circuit to identify the type of the inkjet head by a plurality of identification signals, so that a good match between the printer and the inkjet head is achieved, thereby achieving recognition of the inkjet head the goal of. This case is applicable to the inkjet head of the printer. The identification circuit is of great industrial value and is submitted in accordance with the law. This case can be modified by people who are familiar with this technology. However, they are all protected by the scope of the patent application. 18 1286972 BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a block diagram showing the circuit of the ink jet head recognition circuit of the preferred embodiment of the present invention. Second figure: It is a circuit structure diagram of the first counter shown in the first figure. Third figure: It is a circuit structure diagram of the second counter shown in the first figure. The fourth figure is a signal waveform diagram of the first clock signal, the second clock signal, and the load signal of the operation of the first figure.
19 1286972 【主要元件符號說明】19 1286972 [Description of main component symbols]
14、15、16、1121 電源端：17 喷墨頭識別電路：10 第一計數器：111 輸出端：1111 編碼電路：12 輸出端：1122 輸入端 輸出端：18 第二時脈信號：Clk2 電壓源：Vdd 第二開關電晶體：A2 第一負載電晶體：T1 第五開關電晶體：A5 第六開關電晶體：A6 第八開關電晶體：A8 第十開關電晶體：A10 第十二開關電晶體：A12 第四負載電晶體：T4 計數電路：11 第二計數器：112 接地端：1112 輸出電路：13 接地端：1123 第一時脈信號：Clkl 負載信號：Load 第一開關電晶體：A1 第三開關電晶體：A3 第四開關電晶.體·· A4 第二負載電晶體：T2 第七開關電晶體：A7 第九開關電晶體：A9 第十一開關電晶體：All 第三負載電晶體·· T3 2014, 15, 16, 1121 Power supply: 17 Inkjet head identification circuit: 10 First counter: 111 Output: 1111 Encoding circuit: 12 Output: 1122 Input output: 18 Second clock signal: Clk2 voltage source :Vdd second switching transistor: A2 first load transistor: T1 fifth switching transistor: A5 sixth switching transistor: A6 eighth switching transistor: A8 tenth switching transistor: A10 twelfth switching transistor :A12 Fourth load transistor: T4 Counting circuit: 11 Second counter: 112 Ground terminal: 1112 Output circuit: 13 Ground terminal: 1123 First clock signal: Clkl Load signal: Load First switch transistor: A1 Third Switching transistor: A3 fourth switching transistor. body · A4 second load transistor: T2 seventh switching transistor: A7 ninth switching transistor: A9 eleventh switching transistor: All third load transistor · · T3 20