EP1561587B1

EP1561587B1 - Inkjet printer identification circuit

Info

Publication number: EP1561587B1
Application number: EP20040029570
Authority: EP
Inventors: Hung-Lieh Hu
Original assignee: International United Technology Co Ltd
Current assignee: International United Technology Co Ltd
Priority date: 2004-02-05
Filing date: 2004-12-14
Publication date: 2009-08-19
Anticipated expiration: 2024-12-14
Also published as: EP1561587A1; CN1651246A; CN1332812C; DE602004022628D1

Description

BACKGROUND OF THE INVENTION

Field of the Invention

This invention generally relates to an identification module for an inkjet print head, and more particularly to an identification module having combination logic circuit for an identification circuit of an inkjet printer.

Description of Related Art

FIG. 5 is a schematic diagram of a conventional identification circuit for an inkjet printer, disclosed by Hewlett-Packard Company in US Patent No. 5,363,134 entitled "Integrated circuit printhead for an ink jet printer including an integrated identification circuit". The identification module 526 provides the identification information of the inkjet print head 52 for the inkjet printer 50. The inkjet print head is disposed inside the inkjet printer 50. The inkjet printer 50 includes a controller 502 for controlling the operation of the inkjet 50, and a head drive circuit 504 for driving the inkjet print head 52. The inkjet printer 50 further includes three buses 506A-506C for example coupled between the controller 502 and the head drive circuit 504 for transmitting the digital control signals from the controller 502 to the head drive circuit 504, and for the head drive circuit 504 to output the corresponding analog voltage pulse to the circuits of the inkjet print head 52. The inkjet print head 52 includes an array circuit 522 for heating the ink based on the output signal of the head drive circuit 504 to eject the ink out of the nozzle. The identification module 526 provides the identification information of the inkjet print head 52 for the inkjet printer 50. The temperature sensing circuit 524 provides the temperature-related and other information relevant to the inkjet print head for the inkjet printer 50. A plurality of row lines (or so-called address lines) 528A and column lines (not shown in FIG. 5) are disposed between the head drive circuit 504 and array circuit 522. The head drive circuit 504 selects and drives the devices of the array circuit 522 via these row lines 528A and column lines. The detailed operation will be described as follows.
FIGs. 6A and 6B show a diagram of the array circuit and a circuit of a resistor unit, respectively. The array circuit 522 includes a plurality of resistor units 69 arranged in a plurality of rows and columns for heating the ink to eject out the ink through the nozzle. A plurality of row lines (e.g., A0-A5) and column lines (e.g., power supply lines P0-P5) are connected to the array circuit 522 to selectively provide the energy for the resistor unit 69 so that the selected resistor unit 69 can generate heat to vaporize the ink and eject drops of ink out of nozzles. Each resistor unit 69 includes a resistor 63 and a transistor 64, wherein the transistor 64 is coupled to one of the address lines A0-A5 to control the current flowing through the resistor 63. When a positive voltage is supplied respectively to the row line and the column line connected to the resistor unit 69, the transistor will be turned on and the current will flow through the resistor 63. Hence, the resistor 63 will vaporize the ink and eject drops of ink out of nozzles.
FIG. 7 is a conventional identification module. The identification module 526 is coupled to a plurality of row lines (e.g., A1-A13) and includes a plurality programmable paths consisting of a plurality of fuses (e.g., F1-F13) and a plurality of transistors (e.g., Q1-Q13). Each programmable path includes a fuse series-connected to the gate of a corresponding transistor. Each programmable path provides one-bit identification code for the inkjet printer 50. The one-bit identification code is "1" or "0" depending on whether the fuse is blown or not. Hence, the combination of the one-bit identification codes can provide different identification information for the inkjet printer 50.
In brief, the conventional identification circuit requires a row line for one bit identification code. Further, only one row line can be at logic high at a time. Therefore, to provide more identification codes, the cost of the identification circuit is higher and the size of the identification circuit becomes larger.

SUMMARY OF THE INVENTION

The present invention is directed to an identification circuit for an inkjet printer by using fewer control input terminals and control lines to read more identification codes. The control lines can use the existing address lines or power supply lines in the print head for reading the input signals of the identification codes.
The present invention is directed to an identification method for an inkjet printer, which is based on the combination or ways of arrangement of the logic levels of the control signal to read one of the memory units.
One or part or all of these and other features and advantages of the present invention will become readily apparent to those skilled in this art from the following description wherein there is shown and described a preferred embodiment of this invention, simply by way of illustration of one of the modes best suited to carry out the invention. As it will be realized, the invention is capable of different embodiments, and its several details are capable of modifications in various, obvious aspects all without departing from the invention. Accordingly, the drawings and descriptions will be regarded as illustrative in nature and not as restrictive.
According to an embodiment of the present invention, an inkjet printer identification module according to claim 1 is provided. According to another embodiment of the present invention, an inkjet printer identification circuit according to claim 2 is provided.
In an embodiment of the present invention, each memory unit includes a fuse or a low-power (less than 0.3W) resistor.
In an embodiment of the present invention, each identification unit includes a NAND gate. The NAND gate includes a plurality of NAND gate input terminals and a NAND gate output terminal, wherein one of the plurality of NAND gate input terminals is coupled to the data input terminal, one of the other of the plurality of NAND gate input terminals is coupled to the control input terminal, the NAND gate output terminal is an output terminal of the identification unit.
In an embodiment of the present invention, each of the identification units comprises a plurality of AND gates and a NOR gate. Each of the AND gates includes a plurality of AND gate input terminals and a AND gate output terminal. One of the AND gate input terminals is coupled to one of the data input terminals, and the other AND gate input terminals are coupled to the control input terminal. The NOR gate includes a plurality NOR gate input terminals and a NOR gate output terminal. Each of the AND gate output terminals is connected to one of the NOR gate input terminals, and the NOR gate output terminal is the output terminal of the identification unit.
In an embodiment of the present invention, the control lines are power supply lines or address lines.
The document US-A-6 022 094 discloses an ink jet print head identification system for providing print head identifying information to the electronics of an ink jet printer including one or more parallel load, serial out, dynamic shift registers integrated into a print head chip having a plurality of address lines interconnecting the printer electronics and the print head electronics. The memory input of each shift register is electrically connected to a memory matrix that supplies digital bits of information to the shift register in response to receiving a decode signal function from the printer electronics. In a preferred embodiment, two of the address lines provide each of the registers with successive sequential clock signals to serially shift the bit of information received from the shift register's corresponding memory matrix to an output line where the print head identifying information is read by the printer electronics. Embodiments of the invention may employ any number of shift registers and memory matrices independent of the number of available address lines.
The present invention is also directed to an inkjet printer identification method according to claim 9.
In an embodiment of the present invention, the reading of the memory unit includes reading the content stored in the memory units via address lines or power supply lines.
The present invention utilizes the combination logic in the identification module so that it can use fewer control terminals and control lines to read more identification codes. The control lines can use the existing address lines or power supply lines in the print head for reading the input signals of the identification codes.
The above is a brief description of some deficiencies in the prior art and advantages of the present invention. Other features, advantages and embodiments of the invention will be apparent to those skilled in the art from the following description, accompanying drawings and appended claims.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic diagram of an inkjet printer in accordance with an embodiment of the present invention.
FIG. 2A is a schematic diagram of an identification module of an identification circuit of an inkjet printer in accordance with an embodiment of the present invention.
FIG. 2B is a block diagram of an identification module of an identification circuit of an inkjet printer in accordance with an embodiment of the present invention.
FIG. 3A is an identification unit with four data input terminals and two control input terminals in accordance with an embodiment of the present invention.
FIG. 3B is an identification unit with two data input terminals and one control input terminal in accordance with an embodiment of the present invention.
FIG. 3C is an identification unit with one data input terminal and one control input terminal in accordance with an embodiment of the present invention.
FIG. 3D is a NMOS circuit to implement the logic circuit enclosed in the dash circle 306 shown in FIG. 3A in accordance with an embodiment of the present invention.
FIG. 3E is a fuse circuit in accordance with an embodiment of the present invention.
FIG. 4 is a flow chart of an identification method for an inkjet printer in accordance with an embodiment of the present invention.
FIG. 5 is a schematic diagram of a conventional identification circuit for an inkjet printer.
FIG. 6A shows an array circuit of a conventional inkjet printer.
FIG. 6B shows a circuit of a conventional resistor unit.
FIG. 7 is a conventional identification module.

DESCRIPTION OF THE EMBODIMENTS

FIG. 1 is a schematic diagram of an inkjet printer in accordance with an embodiment of the present invention. The inkjet printer 10 includes a control circuit 102 for controlling the operation of the inkjet printer 10. The inkjet print head 20 includes a plurality of control lines 110 and an identification module 106. The identification module 106 is coupled to the control lines 110. The inkjet printer identification circuit 100 is coupled to an inkjet printer 10 and an inkjet print head 20. The inkjet printer identification circuit 100 provides the content stored in the inkjet print head 20 for the inkjet printer 10. The inkjet printer identification circuit 100 includes the control circuit 102, a plurality of control lines 110 and the identification module 106.
In an embodiment of the present invention, the content stored in the inkjet print head 20 can be, but not limited to, the ink cartridge product number, the number of inkjet nozzles, the volume of the ink, the manufactured date, the status of an ink cartridge or the type of the ink.
In this embodiment, the control circuit 102 provides the control signal to these control lines 110. The control lines 110 can be, but not limited to, the power supply lines or the address lines.
In an embodiment of the present invention, the identification module 106 is coupled to the control circuit 102 via the signal transmission line 112 and sends the content in the inkjet print head 20 to the inkjet printer 10.
In this embodiment, the control lines 110, for example, are coupled to the array circuit 108. In a practical circuit design, the control lines 110 can be coupled to the other external circuits.
FIG. 2A is a schematic diagram of an identification module of an identification circuit of an inkjet printer in accordance with an embodiment of the present invention. In this embodiment, the identification module 106 can use, for example, four control input terminals A, B, C, and D to provide 2*2*2*2 = 16 different identification information via a combination logic. It should be noted that the identification module 106 is not limited to four control input terminals but can be more than or less than four control input terminals depending on how much content is required to be stored in the inkjet print head.
FIG. 2B is a block diagram of an identification module of an identification circuit of an inkjet printer in accordance with an embodiment of the present invention. The identification module 106 includes identification units 202, 204, 206, 208, and 210. The data input terminals (e.g., F1-F16) of the identification units 202-208 are coupled to a plurality of memory units 230 respectively. The identification units 202-208 receive the signals from the control input terminals A and B respectively. Further, the four input terminals of the identification unit 210 are coupled to the four output terminals of the identification units 202-208 respectively and receive the signals from the control input terminals C and D. It should be noted that the identification module 106 is not limited to only four identification units. Accordingly, one identification unit may also be used to achieve the purpose of the present invention. In such embodiment, the output terminal of the identification unit is coupled to the signal transmission line 112.
In an embodiment of the present invention, the memory unit 230 includes a fuse or a low-power resistor less than 0.3W.
FIG. 3A is an identification unit with four data input terminals (F1~F4) and two control input terminals (A and B) in accordance with an embodiment of the present invention. In this embodiment, the identification unit 202 includes AND gates 312, 314, 316, and 318 and a NOR gate 320. The AND gate 312 receives the signals from the data input terminal F1, and A', B'. The AND gate 314 receives the signals from the data input terminal F2, and A, B'. The AND gate 316 receives the signals from the data input terminal F3, and A', B. The AND gate 318 receives the signals from the data input terminal F4, and A, B. The NOR gate 320 receives the output signals from the AND gates 312-318. In the identification unit 202, operation performed by each of the AND gates 312-318 results in logic 1 only when all inputs of corresponding AND gates are logic 1. The NOR gate 320 will output logic 0 when any one of the inputs of NOR gate 320 is logic 1; the NOR gate 320 will output logic 1 only when all inputs of the NOR gate 320 are logic 0. The output terminal of the NOR gate 320 is the output terminal of the identification unit 202.
In this embodiment, the number of control input terminals is not limited to two (e.g., control input terminals A and B); it can be only single control input terminal (e.g., a control input terminal A). As shown in FIG. 3B, when the identification unit 202 has a control input terminal A and two data input terminals F1 and F2, the AND gate 312 receives the signals from F1 and A; the AND gate 314 receives the signals from F2 and A'. When both of the input terminals of each AND gate (312 and 314) are logic 1, the AND gates 312 and 314 will output logic 1. The NOR gate 320 will output logic 0 only when any one of the inputs of the NOR gate 320 is logic 1; the NOR gate 320 will output logic 1 only when all inputs of the NOR gate 320 are logic 0.
In other words, in the above embodiment, when there are n control input terminals, the identification circuit can read the content stored in 2n (F1-F2n) memory units.
In the above embodiment, the identification unit 202 includes AND gates 312, 314, 316, and 318 and a NOR gate 320. In another embodiment, as shown in FIG. 3C, when there is only a control input terminal A and a data input terminal F1, the identification unit 202 can only include a NAND gate 322. In such embodiment, the NOR gate 320 in FIG. 3A is not required.
FIG. 3D is a NMOS circuit to implement the logic circuit enclosed in the dash circle 306 shown in FIG. 3A. In this embodiment, the four AND gates of FIG. 3A are implemented by four sets of NMOS transistor units 340, 350, 360, and 370 respectively. Each NMOS transistor unit includes three NMOS transistors. For example, the NMOS transistor unit 340 includes 3 NMOS transistors to receive the input signals F1, A', and B'; the NMOS transistor unit 350 includes 3 NMOS transistors to receive the input signals F2, A, a nd B'; the NMOS transistor unit 3 60 includes 3 NMOS transistors to receive the input signals F3, A', and B; the NMOS transistor unit 370 includes 3 NMOS transistors to receive the input signals F4, A, and B. The operation is the same as the above identification unit 202.
FIG. 3E is a fuse circuit in accordance with an embodiment of the present invention. In this embodiment, the memory unit 230 can be implemented by a fuse circuit as shown in FIG. 3E. The on/off of the fuse 352 is controlled by the NMOS transistor 354. The gate of the NMOS transistor 354 is coupled to one of the input signals F1-F16. When the gate of the NMOS transistor 354 receives logic 1, the NMOS transistor 354 will be turned on and the output of the memory unit 230 is logic 0; when the gate of the NMOS transistor 354 receives logic 0, the NMOS transistor 354 will be turned off and the output of the memory unit 230 is logic 1.
FIG. 4 is a flow chart of an identification method for an inkjet printer in accordance with an embodiment of the present invention. The first step is to obtain a control signal (S402). The next step is to analyze the control signal and obtain the arrangement of the signal levels of the control signal (S404). Then based on the arrangement of the signal levels of the control signal, one of the memory units will be selected for reading (S406). That is, the content stored in the selected memory unit will be read.
In an embodiment of the present invention, the identification method reads the content stored in the memory units via the identification unit through a plurality of address lines or power supply lines.
In light of the above, the inkjet printer identification circuit of the present invention utilizes the digital multiplexer (which can be a 2-to-1 multiplexer, 4-to-1 multiplexer, 8 -to-1 multiplexer, etc. depending on the circuit design). Hence, it can use fewer control input terminals and control lines to read more identification codes. In addition, the control lines can use the existing address lines or power supply lines in the inkjet print head for reading the input signals of the identification codes. Further, because the present invention uses parallel input, the clock signal is not required to read the identification code.
The foregoing description of the preferred embodiment of the present invention has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form or to exemplary embodiments disclosed. Accordingly, the foregoing description should be regarded as illustrative rather than restrictive. Obviously, many modifications and variations will be apparent to practitioners skilled in this art. The embodiments are chosen and described in order to best explain the principles of the invention and its best mode practical application, thereby to enable persons skilled in the art to understand the invention for various embodiments and with various modifications as are suited to the particular use or implementation contemplated. It is intended that the scope of the invention be defined by the claims appended hereto. It should be appreciated that variations may be made in the embodiments described by persons skilled in the art without departing from the scope of the present invention as defined by the following claims.

Claims

An inkjet printer identification module (106), for providing a content stored in an inkjet print head for an inkjet printer, said inkjet print head disposed inside said inkjet printer, comprising:
a plurality of memory units (230),

a plurality of identification units (202, 204, 206, 208, 210),

wherein each of said plurality of identification units (202, 204, 206, 208, 210) includes at least one control input terminal (A), an output terminal and a plurality of data input terminals, each of said plurality of data input terminalsis coupled to a corresponding one of said plurality of memory units (230) respectively, each of said identification units (202, 204, 206, 208, 210) is capable of receiving contents output from said memory units (230) in parallel, said control input terminal (A) is adapted to be coupled to corresponding one of a plurality of control lines (110), each of said identification units (202, 204, 206, 208, 210) is capable of being responsive to said at least one control signal received from said plurality of control lines (110) and logically operated with the contents for outputting an output signal based on the result of the logical operation of the received control signal and the contents stored in at least one of said plurality of memory units (230) via said output terminal.
An inkjet printer identification circuit, for providing a content stored in an inkjet print head for an inkjet printer, said inkjet print head disposed inside said inkjet printer, comprising an identification module according to claim 1, wherein the identification circuit further comprises:
a plurality of control lines (110) coupled to the control input terminals of the identification units; and

a control circuit (102), providing a control signal to said plurality of control lines (110).
The circuit of claim 2, wherein said identification module (106) is electrically coupled to said control circuit (102) via a transmission line (112).
The circuit of claim 2, wherein said plurality of control lines (110) are power supply lines.
The circuit of claim 2, wherein said plurality of control lines (110) are address lines.
The inkjet printer identification module (106) of claim 1 or circuit of claim 2, wherein each of said memory units, (230) includes a fuse.
The inkjet printer identification module (106) of claim 1 or circuit of claim 2, wherein each of said memory units (230) includes a low-power resistor.
The inkjet printer identification module (106) of claim 1 or circuit of claim 2, wherein each of said plurality of identification units (202, 204, 206, 208, 210) includes:
a plurality of AND gates, each of said plurality of AND gates including a plurality of AND gate input terminals and an AND gate output terminal, at least one of said plurality of AND gate input terminals being coupled to one of said plurality of data input terminals,

the other said plurality of AND gate input terminals being coupled to said control input terminal (A); and

a NOR gate, including a plurality of NOR gate input terminals and a NOR gate output terminal, each of said plurality of AND gate output terminals being coupled to one of said

plurality of NOR gate input terminals, said NOR gate output terminal being said output terminal of said identification unit.
An inkjet printer identification method comprising:
using at least one control signal provided to a plurality of identification units (202, 204, 206, 208, 210) to read contents stored in a plurality of memory units (230) coupled to corresponding said identification units (202, 204, 206, 208, 210), each of said identification units (202, 204, 206, 208, 210) including at least one control input terminal (A), an output terminal and a plurality of data input terminals, each of said data input terminals being electrically coupled to a corresponding memory unit, wherein said contents of said memory units (230) are read in parallel from respective outputs of said memory units (230) by said identification units (202, 204, 206, 208, 210) via corresponding data input terminals based on an arrangement of a signal level of said control signal, each of said identification units (202, 204, 206, 208, 210) is capable of being responsive to said at least one control signal and logically operated with the contents for outputting an output signal based on the result of the logical operation of the received control signal and the contents stored in at least one of said plurality of memory units (230) via said output terminal.
The method of claim 9, wherein the step of reading said memory units (230) includes reading said contents stored in said memory units (230) via address lines.
The method of claim 9, wherein the step of reading said memory units (230) includes reading said contents stored in said memory units (230) via power supply lines.
The method of claim 9, wherein said content at least includes one of an ink cartridge product number, a number of inkjet nozzle, a volume of ink, a manufacturing date, a status of an ink cartridge, a type of an ink.
The method of claim 9, wherein each of said memory units (230) includes a fuse.
The method of claim 9, wherein each of said memory units (230) includes a low-power resistor.
The method of claim 9, wherein each of said identification units includes:
a plurality of AND gates, each of said plurality of AND gates including a plurality of AND gate input terminals and an AND gate output terminal, one of said plurality of AND gate input terminals being coupled to corresponding one of said plurality of data input terminals, the other said plurality of AND gate input terminals being coupled to said control input terminal (A); and

a NOR gate, including a plurality of NOR gate input terminals and a NOR gate output terminal, each of said plurality of AND gate output terminals being coupled to one of said plurality of NOR gate input terminals, said NOR gate output terminal being said output terminal of said identification unit.