1286368 九、發明說明： 【發明所屬之技術領域】 本發明係關於一種整合靜態隨機存取記憶體之互補式金氧半 導體影像感測器。尤指一種具有高密度之單電晶體靜態隨機存取 記憶體(1T-SRAM)之影像感測器。 【先前技術】 φ 互補式金氧半導體(complementary metal-oxide semiconductor， CM0S)影像感測器(image sensor)係採用傳統的CMOS電路製程製 作，可將影像感測器以及其所需要的相關周圍電路製作在一起。 相較於習知之載子偶合裝置(charge-coupled devices, CCDs)製程中 需要30至40個光罩製程，CMOS影像感測器僅需大約20個光罩 製程，其製程不僅簡化許多，製造成本亦較載子偶合裝置低廉。 此外’ CMOS影像感測器尚具有小尺寸、高量子效率(quantum • efficiency)以及低雜訊(read-out n〇ise)等優勢。 然而，習知之CMOS影像感測器因其記憶體，如DRAMs，與 影像感測器係分別製作於不同晶片上，致使該影像系統難以縮小 化。因此美國專利第6,563，187號便揭示一種CMOS影像感測器， 特別指將影像感測器、相關影像訊號處理電路以及記憶體元件如 DRAMs或SRAMs整合於同一晶片以降低成本及耗電量之CMOS 影像感測器。 ⑧ 1286368 仁由於DRAM必須週期性的檢查電容器上的電壓，並且需要 經常充電姐如免#料遺失，喊成記鐘更新。若使用不需 ，行更新動狀SRAM，又因其每位元具有4至6個電晶體在 S曰=上所佔據之面積為舰河的四倍，積集度因此降低許多，實 不符7L件尺寸日域物小之要求。另外根據該專利所揭示之 技術’記憶體之整合步驟係於各邏輯元件皆已形成後始進行，因 此仍具有較複雜之製程。 【發明内容】 因此，本發明之主要目的在於提供一種具有高密度⑽触班 density)之單電晶體靜態隨機存取記憶體之互補式金氧半導體影 像感測器及其製作方法。 根據本發明之—健實關，提供—半導縣底，該基底定義 像素_區、—邏輯電路區以及—記憶體區，且該像素陣列 區該邏輯電路區及該記憶體區間係由複數個淺溝隔離所隔離。 該像素陣痛内具有複數似補式金氧半導娜像制元件，該 邏輯電路區内具有―邏輯電路，而該記憶體區内具有複數個單電 曰曰體靜恶隨機存取記憶體。該單電晶體靜態隨機存取記憶體係由 一電容結構及一電晶體組成。該電容結構包含一藉由離子佈植形 成於該基底内作為電容下電極capacit〇r ^1对6)之摻雜區、一 设於該摻雜區上之電容介電層、一設於該電容介電層上之電容上 電極(topcapacitorplate);該電晶體係具有一閘極介電層、一閘極、 1286368 -沒極及-延伸至該電容上電極下方而與該摻雜電性連接之源 極。值得注意的是，該雷交彡士 ’、 構之該電容介電層與該電晶體之該 閘極介電層係為同一層。 由於本發明提供之電容結構之電容介電層與電晶體之間極介 電層^同-層，即該電容介電層與該間極介電層可同時形成， 而電，結構之電容上電極與電晶體之祕亦可啊形成。故本發 方法係於製组補式錄料體影像_器各元件之 二機X/僅增加—光軍製程’即可整合此高密度單電晶體靜 滅機存取記鋪觸輯魏槪財錢轉體雜感測器 上0 ϋ本發明之上述目的、特徵、和優點能更明顯易懂，下文特 牛車又佳實施方式，並配合所_式，作詳細說明如下。然而如下 之較佳實施方式姻式僅供參考與_，並非 以限制者。 【實施方式】 明參閱第1圖至第7圖。第j圖至第7圖為本發明於半導體』 :ίο:亡整合互補式金氧半導體電晶體影像感測器之影像感測天 件、邏輯電路元件、及記舖之示_。魏提供—基底獅，《 如一 +導體晶IRwafer)，且基底⑽表面定義有—像素陣列區4〇 —路區⑼、以及一記憶體區8〇。如第i圖所示，一 P则 1286368 雜井H)2形成於像素陣列區4〇内，—N型接雜井ι〇4形成於賴 電路區60内，以及另一 N型摻雜井1〇6形成於記麵區8〇内。 此外，絲觸中另形成有複數個淺溝隔離(swaibwtreneh is〇lati〇n，stI)108，誠隔離像素陣舰4〇、邏輯電路區6〇、以及 記憶體區80。 明參閱第2圖，接著形成一具有開口之圖案化光阻層於基 底100上，並透過光阻層200之開口進行一離子佈植製程，以於 記憶體區之N型摻雜井106内形成一摻雜區2〇2當作電容下電極。 請參閱第3 ®，移除光阻層細後，於基底1〇〇上形成一介電 層300，例如石夕氧化合物和氮石夕化合物，且介電層之厚度可依 電路設計或元件特性所需作調整，使得形成於像素陣列區4〇、邏 輯電路區60、以及記憶體區8〇之介電層具有相同或不同的厚 度。為了方便說明起見’第3騎示之實施_揭露—相同厚度 的介電層300，且介電層300係作為像素陣列區4〇與邏輯電路區 6〇内各電晶體之祕介電層，以及記，隨區8()内之單電晶體靜態 ，機存取記憶體之電晶體之閘極介電層，_亦作為單電晶體靜 悲隨機存取纖體之電容結構之電容介電層。然而，於其他實施 例中’各_介㈣與電容介電層亦可_多次製程步驟使其分 別具有不同之厚度，或由不同之介電層組成。舉例來說，電容介 ^ θ可由氮化石夕、氮化石夕與氧化石夕之混合物《高介電常數材料構 成而閘極;丨電層則可由氧化石夕、氮氧化石夕或高介電常數材料所 1286368 構成。 請參閱第4圖及第5圖，隨後於介電層300上形成一多晶矽層 400，並選擇性地於多晶矽層4〇0上再形成一多晶金屬矽化物 (polycide)層402，並於後續進行一自對準金屬矽化物製程 (salicide)。於本實施例中，係利用多晶矽層4〇〇與金屬石夕化物4〇2 構成閘極，但本發明之應用並不限於此，而可僅利用多晶矽層4〇〇 • 製作閘極。接著，於金屬矽化層402上形成一圖案化之光阻層 4〇4，用來定義像素陣列區40、邏輯電路區6〇、記憶體區8〇内之 各電晶體之閘極，與記憶體區8〇内電容結構之電容上電極。接著， 利用光阻層404當作-侧遮罩來對多晶石夕層働及金屬石夕化層 進行飿刻製程。之後，移除光阻層仙4，在像素陣列區4〇、 邏輯電路區60、記憶體區80内同時形成複數個電晶體之閘極500 以及電容結構之電容上電極502。 請再參閱第5圖，於基底⑽上再形成—具有開口之_匕光 用以疋義影像感測元件之感光區域。接著對基 =離子佈植製程，以於基底丨。。中形成一 摻之蝴柄—軒編形成一淺p型 凊參閱第6圖， 圖案化光阻層(未顯 移除光阻層504之後，接著利用—遮罩，例如 示）’於像素陣列區4〇内之ρ型摻雜井1〇2中 1286368 形成複數個N動缚_雄6Q2(lightlyd减ldd)。再利用 另-遮罩於邏輯電路區60之N型摻雜井1〇4中及記憶體區8〇内 之N型摻雜井106中形成複數個p型輕摻雜沒極6〇4。 如第7圖所示，接著於像素陣列區40、邏輯電路區60、記憶 體區80内之電晶體的閘極5〇〇以及電容結構之電容上電極5〇2進 行側壁子7GG之製作’而待壁子形成後，利用-遮罩，例 φ 如圖案化光阻層(未顯示），於像素陣列區40内之p型摻雜井1〇2 中形成複數個N型重摻雜沒極（heavily doped drain，HDD)702。然 後再利用另一遮罩於邏輯電路區60之N型摻雜井i〇4中及記憶體 區80内之N型摻雜井1〇6中形成複數個n型重摻雜汲極704,當 作各電晶體之汲極及與源極。如此即完成電晶體部分的邏輯製程。 此外，為因應高積集度以及高電容面積之需求，本發明另提供 一較佳之第二實施例。首先如前述實施例之第1圖所示，本第二 實施例亦提供一基底100，基底100定義有一像素陣列區4〇、一 邏輯電路區60、以及一記憶體區80。一 P型摻雜井1〇2形成於像 素陣列區40内，一 N型摻雜井104形成於邏輯電路區60内，以 及一 N型摻雜井1〇6形成於記憶體區80内。另有複數個淺溝隔離 108形成於基底1〇〇中，用以隔離像素陣列區40、邏輯電路區6〇、 以及記憶體區80。 接著請參閱第8圖與第9圖。第8圖與第9圖為本發明第二實 1286368 施例中記憶體區80之邱八 1圖至第7隱-/ 本發明之第二實施例與第 3 ^ 7圖所不之實施例的主要不同之處在於第2圖與第3圖中 U冓及製備電容的相關步驟，因此為了方便說明起見，以 :敘述僅針對記憶體區⑽内之電料加綱，而其他元件之製程 步驟皆相似於第1圖至第7圖所示之實施例。如第8圖所示，形 成^有開口之圖案化光阻層_於基底腦上，上述開口暴露 刀土底100及口[5分淺溝隔離⑽。之後透過光阻層綱之開口 對淺溝隔離1G8進行侧，藉由淺溝隔離之材f (二氧化石夕） ”基底100之材質(石夕你刻選擇比的不同而於淺溝隔離中形成 「凹槽802。再利用光阻層800作為遮罩對基底1〇〇及凹槽脱 進行-離子佈植製程，以於記憶體區8〇暴露之部分基底麵及凹 槽02侧壁曝4之基底1〇〇形成一摻雜區202當作電容下電極。 入如第9圖所示，接著移除光阻層8〇〇，再於基底1〇〇上形成一 介電層300，同樣地，介電層3〇〇係作為像素陣列區4〇與邏輯電 路區60内各電晶體之閘極介電層、記憶體區6〇内之單電晶體靜 機存取記憶體之電晶體之閘極介電層，以及電容結構之電容 w電層，但閘極介電層與電容介電層亦可分別由不同材質與製程 加以製作，且介電層300之厚度亦可依所需調整。值得注意的是， 由於圖案化光阻層800之開口位置的不同以及多了 一步利用此開 口的蝕刻步驟，因此電容介電層300係覆蓋凹槽802之一側壁並 增加電容面積。接著再於記憶體區8〇之基底1〇〇上形成一電容上 電極502，其中值得說明的是於本實施例中，電容上電極5〇2與像 1286368 素陣列區4〇、賴電路區0()、記鐘區⑽内之酿係為分 •開衣作、而有別於前述實施例之作法，且製作電容上電極地之 步驟可視需要於形成閘極之前或之後進行。#電容上電極观 形成之=，、後續製程可如前述第一實施例之作法與圖示所示進 行卩兀成本發明具有部分製作於凹槽内之電容結構之單電晶體 靜態隨機存取記憶體之式金氧轉體影像感湘。ΒΒ • 糾:本發明另提供一較佳之第三實施例，其係提供-整合深 溝渠式單電晶體靜態隨機存取記憶體之CM〇s影像感測器。請參 閱第10圖及第11圖，第10圖及第11圖為本發明第三實施例中 記憶體區80之部分放大圖。由於本發明之第三實施例與第二實施 例主要不同之處係在於電谷結構之不同，且其他元件之製程步驟 亦相似於第1圖至第7圖所示之實施例，因此為了方便說明起見， 以下敘述僅針對記憶體區80内之電容詳加說明。如第1〇圖所示， 藝形成-具有開口之圖案化光阻層82〇於基底腦上，用以暴露出 部分基底励及部分淺溝隔離·。之後透過光阻層82()之開口對 部分基底100及部分淺溝隔離⑽進行侧而形成一深溝渠822， 且殊溝渠822係貫穿部分淺溝隔離108。接著利用石申石夕玻璃(arsenic silicate glass，ASG)擴散技術，或是直接利用光阻層82〇作為遮罩 對基底100及深溝渠822進行一斜角離子佈植製程，以於深溝渠 822側壁及底部曝露之基底1〇〇形成一摻雜區222作為電容下電 極0 12 1286368 如第11圖所示，移除光阻層820後，再於基底1〇〇上形成一 介電層3〇〇，同樣地，介電層3〇0可作為像素陣列區仙與邏輯電 ‘ 路區60内各電晶體之閘極介電層、記憶體區80内之單電晶體靜 態Ik機存取記憶體之電晶體之閘極介電層，亦可僅作為 之電容介電層之用。值得注意的是，由於酿光== 口位置的不同以及形成深溝渠的侧步驟，摻雜區222係位於深 溝渠222侧壁及底部之基底100内，且電容介電層係覆蓋深 •溝渠822之侧壁及底部，因而增加電容面積並更增加元件之積隼 度。接著再於記憶體區80之基底100上形成一電容上電極5〇= 其中值得說明的是於本實施例中，電容上電極观與像素陣列區 4〇、邏輯電路區60、記憶體區80内之閘極5〇〇係為分開製作，且 製作電容上電極502之步驟可視需要於形成閘極5〇〇之前或之後 進行。當電容上電極5〇2形成之後，後續製程可如前述第一實施 例之作法與圖示所示進行，以完成本發明具有深溝渠式電容結構 #之早電晶體靜態隨機存取記憶體之互補式金氧半導體影像感測 器。 綜上所述’本發明係提供一整合影像感測元件、邏輯電路與單 電晶體靜態隨機存取記憶體之互補式金氧半導體影像感測器。與 習知技術相比，躲邏難財僅增加—鮮製程柯完成此^ 高密度單電晶體靜態隨機存取記憶體之CM〇s影像感測器之整、 合0 13 1286368 以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍 所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。 【圖式簡單說明】 ^聰第7圖為根據她嫩合單電晶麟隨機存取 =憶體之互_錢轉贿像_紅妓餘實 意 圖。 第第=:Γ第二較、 圖為本發明第三較佳實施例之部分放大示意圖。 【主要元件符號說明】 100 基底 102 104 、 106 Ν型摻雜井 108 200、404 、504、800、820 光阻層 202 > 222 摻雜區 300 400 多晶梦層 402 500 閘極 502 506 深Ν型摻雜區 508 602 Ν型輕摻雜没極 604 700 側壁子 702 704 Ρ型重摻雜汲極 802 822 深溝渠 ?型摻雜井 淺溝隔離 介電層 金屬矽化層 電容上電極 淺ρ型摻雜區 ρ型輕摻雜汲極 Ν型重摻雜汲極 凹槽1286368 IX. Description of the Invention: [Technical Field of the Invention] The present invention relates to a complementary oxy-oxide semiconductor image sensor incorporating a static random access memory. In particular, an image sensor with a high density single crystal static random access memory (1T-SRAM). [Previous technology] φ Complementary metal-oxide semiconductor (CMOS) image sensor is fabricated by a conventional CMOS circuit process, and can be used for image sensors and related peripheral circuits. Made together. Compared with the conventional charge-coupled devices (CCDs) process, which requires 30 to 40 mask processes, the CMOS image sensor requires only about 20 mask processes, and the process is not only simplified, but also the manufacturing cost. It is also cheaper than the carrier coupling device. In addition, CMOS image sensors have the advantages of small size, high quantum efficiency (quantum • efficiency) and low noise (read-out n〇ise). However, conventional CMOS image sensors are fabricated on different wafers due to their memory, such as DRAMs, and image sensor systems, making the image system difficult to downsize. Therefore, U.S. Patent No. 6,563,187 discloses a CMOS image sensor, in particular, integrating image sensors, related image signal processing circuits, and memory components such as DRAMs or SRAMs on the same wafer to reduce cost and power consumption. CMOS image sensor. 8 1286368 Ren due to DRAM must periodically check the voltage on the capacitor, and need to be recharged often if the material is missing, shouting into a clock update. If it is not needed, the dynamic SRAM is updated, and because it has 4 to 6 transistors per bit, the area occupied by S曰= is four times that of the ship, and the accumulation degree is reduced by many, which does not match 7L. The size of the piece is small. In addition, according to the technology disclosed in the patent, the integration step of the memory is performed after each logic element has been formed, and thus still has a complicated process. SUMMARY OF THE INVENTION Accordingly, it is a primary object of the present invention to provide a complementary MOS image sensor having a high density (10) touch-shift density of a single transistor static random access memory and a method of fabricating the same. According to the present invention, a solid-state, providing a semi-conducting bottom, the substrate defining a pixel_region, a logic circuit region, and a memory region, and the logic circuit region and the memory region of the pixel array region are plural A shallow trench isolation is isolated. The pixel matrix has a complex complement-type MOS semiconductor component, the logic circuit region has a logic circuit, and the memory region has a plurality of single-electron corpus static random access memory. The single transistor static random access memory system is composed of a capacitor structure and a transistor. The capacitor structure comprises a doped region formed by ion implantation in the substrate as a capacitor lower electrode capacit〇r ^1 pair 6), a capacitor dielectric layer disposed on the doped region, and a capacitor layer disposed thereon a top-capacitor plate on the capacitor dielectric layer; the transistor system has a gate dielectric layer, a gate, a 1286368-nanopole, and an extension to the capacitor upper electrode to electrically connect the doping The source. It is worth noting that the lightning contact gentleman's structure has the same dielectric layer as the gate dielectric layer of the transistor. Because the capacitor dielectric structure provided by the present invention has a dielectric layer between the dielectric layer and the transistor, that is, the capacitor dielectric layer and the interlayer dielectric layer can be simultaneously formed, and the capacitance of the electrical structure is The secret of the electrode and the transistor can also be formed. Therefore, the method of the present invention is based on the production of the supplementary recording material image _ device two components X / only increase - Guangjun process 'can integrate this high-density single crystal static machine access record shop touch Wei Weicai money The above-mentioned objects, features, and advantages of the present invention can be more clearly understood. The following embodiments of the special vehicle are also described in detail below. However, the following preferred embodiment is for reference only and is not intended to be limiting. [Embodiment] See Fig. 1 to Fig. 7 for details. Figures j to 7 show the image sensing artifacts, logic circuit components, and recordings of the invention in the semiconductor: ίο: dead integrated complementary MOS transistor image sensor. Wei provides a base lion, such as a + conductor crystal IRwafer, and the surface of the substrate (10) is defined as a pixel array region 4 - a road region (9), and a memory region 8 〇. As shown in the figure i, a P is 1286368, the well H) 2 is formed in the pixel array region 4〇, the N-type well ι is formed in the circuit region 60, and another N-type doping well is formed. 1〇6 is formed in the recording area 8〇. In addition, a plurality of shallow trench isolations (swibwtreneh is〇lati〇n, stI) 108 are formed in the silk contact, and the pixel array ship 4〇, the logic circuit area 6〇, and the memory area 80 are isolated. Referring to FIG. 2, a patterned photoresist layer having an opening is formed on the substrate 100, and an ion implantation process is performed through the opening of the photoresist layer 200 for the N-type doping well 106 in the memory region. A doped region 2〇2 is formed as a capacitor lower electrode. Referring to FIG. 3, after removing the photoresist layer, a dielectric layer 300 is formed on the substrate 1 , such as a compound and a nitridant compound, and the thickness of the dielectric layer can be determined by circuit design or component. The characteristics are adjusted so that the dielectric layers formed in the pixel array region 4, the logic circuit region 60, and the memory region 8A have the same or different thicknesses. For the sake of convenience of explanation, the implementation of the third riding method _ exposes the dielectric layer 300 of the same thickness, and the dielectric layer 300 serves as the secret dielectric layer of each of the transistors in the pixel array region 4 and the logic circuit region 6 , and remember that the single transistor in the area 8 () is static, the gate access dielectric of the memory transistor of the memory, _ also serves as the capacitance of the capacitor structure of the single crystal static random access random volume. Electrical layer. However, in other embodiments, each of the dielectric layers may be formed with different thicknesses or by different dielectric layers. For example, the capacitance θ can be composed of a mixture of high dielectric constant material and a gate of a mixture of nitriding cerium, nitrite and oxidized oxide; the cerium layer can be composed of oxidized stone, oxynitride or high dielectric. The constant material is composed of 1286368. Referring to FIG. 4 and FIG. 5, a polysilicon layer 400 is formed on the dielectric layer 300, and a polycrystalline metal layer 402 is selectively formed on the polysilicon layer 4〇0. A self-aligned metal telluride process is subsequently performed. In the present embodiment, the gate electrode is formed of the polysilicon layer 4 〇〇 and the metal iridium compound 4 〇 2, but the application of the present invention is not limited thereto, and the gate electrode can be formed only by using the polysilicon layer. Next, a patterned photoresist layer 4〇4 is formed on the metal deuteration layer 402 for defining the gates of the respective pixel transistors in the pixel array region 40, the logic circuit region 6〇, and the memory region 8〇, and the memory. Capacitor upper electrode of the capacitor structure within 8 体 of the body region. Next, the photoresist layer 404 is used as a side mask to perform a etch process on the polycrystalline slab layer and the metal slab layer. Thereafter, the photoresist layer 4 is removed, and a plurality of transistor gates 500 and a capacitive upper electrode 502 of the capacitor structure are simultaneously formed in the pixel array region 4, the logic circuit region 60, and the memory region 80. Please refer to Fig. 5 again, and then formed on the substrate (10) - having an opening for the photosensitive area of the image sensing element. Next, the base = ion implantation process is applied to the substrate. . Forming a blended handle--Xuanbian to form a shallow p-type 凊 See Figure 6, patterning the photoresist layer (after removing the photoresist layer 504, then using a mask, for example, shown) in the pixel array 1286368 in the p-type doping well 1〇2 in the zone 4〇 forms a plurality of N-bindings_Xiong 6Q2 (lightlyd minus ldd). A plurality of p-type lightly doped immersions 6 〇 4 are formed in the N-type doping well 106 in the N-type doping well 1 〇 4 and the memory region 8 另 in the logic circuit region 60. As shown in FIG. 7, the fabrication of the sidewall spacer 7GG is performed in the pixel array region 40, the logic circuit region 60, the gate 5〇〇 of the transistor in the memory region 80, and the capacitor upper electrode 5〇2 of the capacitor structure. After the wall is formed, a plurality of N-type heavily doped forms are formed in the p-type doping well 1〇2 in the pixel array region 40 by using a mask, such as a patterned photoresist layer (not shown). Heavily doped drain (HDD) 702. Then, another n-type heavily doped drain 704 is formed in the N-type doping well 〇6 of the logic circuit region 60 and the N-type doping well 1 〇6 in the memory region 80, As the drain and source of each transistor. This completes the logic process of the transistor section. Furthermore, the present invention provides a preferred second embodiment in response to the need for high integration and high capacitance area. First, as shown in Fig. 1 of the foregoing embodiment, the second embodiment also provides a substrate 100 defining a pixel array region 4, a logic circuit region 60, and a memory region 80. A P-type doping well 1〇2 is formed in the pixel array region 40, an N-type doping well 104 is formed in the logic circuit region 60, and an N-type doping well 1〇6 is formed in the memory region 80. A plurality of shallow trench isolations 108 are formed in the substrate 1 to isolate the pixel array region 40, the logic circuit region 6A, and the memory region 80. Next, please refer to Figure 8 and Figure 9. 8 and 9 are the second embodiment of the memory region 80 of the second embodiment of the present invention, and the second embodiment and the seventh embodiment of the present invention. The main difference is the steps related to the preparation of the capacitance in the second and third figures. Therefore, for the sake of convenience of explanation, the description is only for the electric material in the memory region (10), and other components are The process steps are similar to the embodiments shown in Figures 1 through 7. As shown in Fig. 8, a patterned photoresist layer having an opening is formed on the base brain, and the opening exposes the bottom 100 and the mouth [5 points shallow trench isolation (10). Then, through the opening of the photoresist layer, the shallow trench is isolated from the side of the 1G8, and the material of the base 100 is separated by the shallow trench isolation material f (the dioxide dioxide) (the stone is separated from the shallow trench by the difference of the selection ratio). Forming a "groove 802. The photoresist layer 800 is used as a mask to perform the ion implantation process on the substrate 1 and the recess, so as to expose the exposed surface portion of the memory region 8 and the sidewall of the recess 02. A substrate 1 is formed as a capacitor lower electrode. As shown in FIG. 9, the photoresist layer 8 is removed, and a dielectric layer 300 is formed on the substrate 1 . Similarly, the dielectric layer 3 is used as the gate dielectric region 4 and the gate dielectric layer of each transistor in the logic circuit region 60, and the single crystal static memory access memory in the memory region 6〇. The gate dielectric layer of the crystal and the capacitor w electrical layer of the capacitor structure, but the gate dielectric layer and the capacitor dielectric layer can also be fabricated by different materials and processes, and the thickness of the dielectric layer 300 can also be Need to be adjusted. It is worth noting that due to the difference in the opening position of the patterned photoresist layer 800 and the use of one step The etching step of the opening, so that the capacitor dielectric layer 300 covers one sidewall of the recess 802 and increases the capacitance area. Then, a capacitor upper electrode 502 is formed on the substrate 1 of the memory region 8 ,, wherein it is worth noting that In the present embodiment, the capacitor upper electrode 5〇2 and the image processing area of the 1286368 pixel array area 4, the circuit area 0 (), and the clock area (10) are divided and opened, and are different from the foregoing embodiment. The method of making the upper electrode of the capacitor may be performed before or after the formation of the gate. The formation of the upper electrode of the capacitor is performed, and the subsequent process may be performed as shown in the foregoing first embodiment. The present invention provides a preferred embodiment of a single transistor static random access memory having a capacitive structure partially formed in a recess. Provided as a CM〇s image sensor integrating a deep trench type single transistor static random access memory. Please refer to FIG. 10 and FIG. 11 , and FIG. 10 and FIG. 11 are diagrams of the third embodiment of the present invention. A partial enlarged view of the memory area 80. The third embodiment of the present invention is mainly different from the second embodiment in the structure of the electric valley, and the processing steps of other components are similar to the embodiments shown in FIGS. 1 to 7, so that the description is convenient for convenience. For the sake of clarity, the following description is only for the capacitance in the memory region 80. As shown in FIG. 1 , the patterned photoresist layer 82 having an opening is attached to the base brain to expose a portion of the substrate. The shallow trench isolation is performed. Then, a portion of the substrate 100 and a portion of the shallow trench isolation (10) are laterally formed through the opening of the photoresist layer 82 () to form a deep trench 822, and the trench 822 is penetrated through the shallow trench isolation 108. Using an arsenic silicate glass (ASG) diffusion technique, or directly using the photoresist layer 82 as a mask to perform an oblique ion implantation process on the substrate 100 and the deep trench 822 to form a sidewall of the deep trench 822 And the bottom exposed substrate 1 〇〇 forms a doped region 222 as a capacitor lower electrode 0 12 1286368. As shown in FIG. 11 , after removing the photoresist layer 820 , a dielectric layer 3 is formed on the substrate 1 . Oh, similarly, the dielectric layer 3〇0 The gate dielectric layer of each transistor in the pixel array area and the logic circuit, and the gate dielectric layer of the transistor of the single-crystal static Ik memory access memory in the memory area 80, Can be used only as a capacitor dielectric layer. It is worth noting that due to the difference in the position of the brewing light == port and the side step of forming the deep trench, the doping region 222 is located in the substrate 100 of the sidewall and bottom of the deep trench 222, and the capacitor dielectric layer covers the deep trench. The sidewalls and bottom of 822 increase the capacitance area and increase the component's accumulation. Then, a capacitor upper electrode 5 is formed on the substrate 100 of the memory region 80. It is worth noting that in the embodiment, the capacitor upper electrode view and the pixel array region 4, the logic circuit region 60, and the memory region 80 The inner gate 5 is made separately, and the step of fabricating the capacitor upper electrode 502 can be performed before or after the gate 5 is formed. After the capacitor upper electrode 5〇2 is formed, the subsequent process can be performed as shown in the foregoing first embodiment to complete the early transistor static random access memory having the deep trench capacitor structure of the present invention. Complementary CMOS image sensor. In summary, the present invention provides a complementary MOS image sensor that integrates an image sensing element, a logic circuit, and a single crystal SRAM. Compared with the prior art, the escaping is difficult to increase only - the fresh process of the process is completed by the CM 〇 image sensor of the high-density single-crystal static random access memory (0 13 1286368). For the preferred embodiment of the present invention, the equivalent variations and modifications made to the scope of the present invention should be within the scope of the present invention. [Simple description of the map] ^ Cong 7th figure is based on her tenderness single electric crystal Lin random access = recall of the mutual _ money transfer bribe like _ red 妓 实 。. The first =: Γ second comparison, which is a partially enlarged schematic view of a third preferred embodiment of the present invention. [Main component symbol description] 100 substrate 102 104, 106 掺杂 type doping well 108 200, 404, 504, 800, 820 photoresist layer 202 > 222 doped region 300 400 polycrystalline dream layer 402 500 gate 502 506 deep Ν-type doped region 508 602 Ν type lightly doped 604 700 sidewall 702 704 Ρ type heavily doped 汲 802 822 deep trench? type doping well shallow trench isolation dielectric layer metal germanium layer capacitor upper electrode shallow ρ Type doped region p-type lightly doped germanium-type heavily doped gate trench