JP2835405B2 - Semiconductor device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to an improvement in a stacked memory cell structure using transistor isolation.

[Prior Art] FIG. 9 schematically shows a cross section of a schematic configuration of two bits adjacent to each other in a stacked memory cell using this type of transistor isolation according to a conventional example.

In the configuration of the conventional device shown in FIG. 9, reference numeral 1 denotes a p-type silicon semiconductor substrate, and reference numerals 2c and 3c denote two adjacent portions of the selected portion on the semiconductor substrate 1, respectively.
These are the gate insulating films for the individual transistors formed corresponding to the bits, and the gate electrodes formed so as to be superimposed on the respective gate insulating films 2c.

Reference numerals 4 and 5 are in the active region surrounded by the transistor isolation on the semiconductor substrate 1, and are similarly formed separately for each of the gate insulating film 2c and the gate electrode 3c. The gate insulating film of each active transistor thus formed, and the gate electrode disposed on each of the gate insulating films 4. Reference numerals 6 and 7 denote the respective active transistors diffused on the main surface of the substrate.
n ^- -type source / drain region, and the n ^- and n ⁺ -type source / drain regions formed by diffusion superimposed on type source / drain region 6. Gate insulating film 4, Gate electrode 5, Source /
The drain regions 6 and 7 constitute a switching element in each adjacent two-bit memory cell portion.

Further, 8, 9 and 10 represent one n for each gate electrode 5.
^A capacitor charge storage electrode (storage node) partially connected to ⁺ source / drain region 7 and extending over gate electrodes 3c and 5 via interlayer insulating film 11, the capacitor insulating film, and a capacitor counter electrode (cell ), Which constitute a charge storage region in each adjacent memory cell portion for 2 bits.

Further, reference numeral 12 denotes an interlayer insulating film which covers adjacent two-bit individual memory cell portions, and reference numeral 13 denotes each gate electrode 5.
A bit line partially connected to the other n ⁺ -type source / drain region 7 common to the memory cells and extending via an interlayer insulating film 12 on each memory cell portion.

In the case of the device configuration according to this conventional example, each charge storage region separated by a transistor in each memory cell portion of adjacent two bits and each switching element corresponding to each charge storage region With each other,
The structure is such that they are juxtaposed on the same flat main surface of a semiconductor substrate.

[Problems to be Solved by the Invention] In the conventional stacked memory cell configuration composed of two adjacent bits using transistor isolation, as described above, each charge accumulation region formed by stacking in the transistor isolated region And the corresponding switching elements are arranged side by side on the same flat main surface of the semiconductor substrate, and the step of the transistor isolation portion in each charge storage region is extremely steep. At the time of processing and forming the gate electrode in the device, a part of the used conductive material may remain in a frame shape along the step of the transistor isolation portion, which causes inconvenience such as a short circuit between adjacent memory cells. There is a problem that a problem arises.

SUMMARY OF THE INVENTION The present invention has been made to solve such a conventional problem, and it is intended to reduce a step on a switching element side on a transistor isolation side as much as possible to form a gate electrode on an active transistor as a switching element. It is an object of the present invention to provide a semiconductor device which can facilitate formation of a semiconductor device.

[Means for Solving the Problems] In order to achieve the above object, a first aspect of the present invention is to provide a switching element and a charge storage area in an active region surrounded by transistor isolation on a semiconductor substrate. A stacked memory cell using transistor isolation configured and provided, comprising: a gate electrode formed on a semiconductor substrate with a first insulating film interposed; and a second insulating film formed on the gate electrode. By combining anisotropic etching and isotropic etching, a tapered inclined surface is formed on an end side surface of the electrode and the second insulating film on the switching element side so as to gradually rise from the semiconductor substrate side. This is a semiconductor device in which a side wall insulating film is formed in a self-aligned manner only on an inclined plane.

According to a second aspect of the present invention, there is provided a stacked memory cell using a transistor isolation formed by providing a switching element and a charge storage region in an active region surrounded by a transistor isolation on a semiconductor substrate. And at least a part of the gate electrode of the transistor isolation is buried in the dug substrate, so that the level difference between the transistor isolation side and the switching element side is made as small as possible. A semiconductor device characterized by the above-mentioned.

[Operation] In the first aspect of the present invention, anisotropic etching and isotropic etching are combined on the side surfaces of the gate electrode and the second insulating film on the switching element side to gradually stand from the semiconductor substrate side. Since the rising tapered inclined surface is formed and the side wall insulating film is formed only on the tapered inclined surface in a self-aligned manner, it is possible to easily form the gate electrode in the active transistor as a switching element. According to the second aspect of the present invention, at least a part of the gate electrode for transistor isolation is buried in a portion dug on the transistor isolation side of the semiconductor substrate. The formation of the gate electrode in the active transistor can be facilitated.

Embodiments of the Invention Hereinafter, embodiments of a semiconductor device according to the present invention will be described with reference to the drawings.

FIG. 1 is a diagram showing two adjacent blocks to which the first embodiment of the present invention is applied.
FIG. 2 is a cross-sectional view schematically showing a schematic configuration of a stacked memory cell for bits, and FIG. 2 is a schematic diagram showing a schematic configuration of a stacked memory cell for two adjacent bits to which the second embodiment of the present invention is applied. It is sectional drawing shown in FIG. These first
In FIG. 2 and FIG. 2, the same reference numerals as those in FIG. 9 indicate the same or corresponding parts.

That is, also in the structure of the first embodiment shown in FIG. 1, reference numeral 1 denotes a p-type silicon semiconductor substrate, and 2a denotes a selected portion on the semiconductor substrate 1 which is subjected to a thermal oxidation process, so that it is divided into two bits each. 3a is a correspondingly formed gate insulating film for transistor isolation, and is formed on each of these gate insulating films 2a so as to be overlapped, and has a resistance value reduced by doping with impurities such as arsenic or phosphorus. This is a gate electrode of each transistor isolation made of a silicon film. Each of these gate electrodes 3a is formed later by using isotropic dry or wet etching or a combination of isotropic etching and anisotropic etching when selectively forming the polycrystalline silicon film. The end 31 on the switching element side is tapered so as to gradually rise from the substrate side, so that the end 31 has a gentle slope, so that the step with respect to the switching element is sufficiently reduced. .

Also, reference numerals 4 and 5 are in the active region surrounded by the respective transistor isolations on the semiconductor substrate 1 and similarly correspond to the respective gate insulating films 2a and the gate electrodes 3a having the tapered ends 31. The gate insulating films of the active transistors, which are separately formed by the same materials and means as those described above, and are set as one set, and the gate electrodes formed so as to be superimposed on the respective gate insulating films 4 are shown. Numerals 6 and 7 denote n ^- type source / drain regions of these active transistors diffused on the main surface of the substrate, and
n ⁺ diffusedly formed on n ⁻ type source / drain region 6
Source / drain regions, each of these low concentrations,
And LDD (Lig)
htly Dopped Drain) transistors. The gate insulating film 4, the gate electrode 5, and the source / drain regions 6 and 7 constitute respective switching elements in each of adjacent two-bit memory cell units.

Further, 8, 9 and 10 represent one n for each gate electrode 5.
A capacitor charge storage electrode (storage node) such as a polycrystalline silicon film which is partially connected to the ⁺ type source / drain region 7 and extends over the gate electrodes 3 and 5 via the interlayer insulating film 11; , And similarly, a capacitor counter electrode (cell plate) such as a polycrystalline silicon film, and these constitute respective charge storage regions in adjacent two-bit individual memory cell portions.

Reference numeral 12 denotes an interlayer insulating film that covers each individual memory cell portion for adjacent two bits, and reference numeral 13 denotes a part connected to the other n ⁺ -type source / drain region 7 common to each gate electrode 5. And a bit line such as a polycrystalline silicon film extending over each memory cell portion via an interlayer insulating film 12.
In this manner, here, a 1-transistor, 1-capacitor DRAM (Dynamic Random Access Memory) composed of two adjacent bits is used.
Access Memory) is obtained.

Therefore, in the configuration of the first embodiment, the end of the gate electrode 3a of the transistor isolation on the side of the switching element is provided.
31 is formed on a tapered inclined surface that gradually rises from the semiconductor substrate 1 side, so that the tapered end of the gate electrode 3a is formed.
Due to the presence of 31, the steepness of the portion corresponding to the end of the separation portion as in the conventional case is effectively reduced, and the step on the transistor separation side with respect to the switching element side can be sufficiently reduced, As a result, the gate electrode 5 of each active transistor as a switching element can be formed easily without causing a short circuit between adjacent regions.

Next, in the configuration of the device of the second embodiment shown in FIG. 2, instead of forming the tapered inclined surface of the end 31 on the switching element side in the gate electrode 3a of each transistor isolation in the device of the first embodiment. Here, only each transistor separation side of the semiconductor substrate 1 is dug to a predetermined depth in advance by, for example, anisotropic etching, etc.
In the same manner as in the first embodiment, a gate insulating film 2b formed by a thermal oxidation process in each transistor isolation and a gate electrode 3b formed of a polycrystalline silicon film are formed on each of the dug portions 1b. Are formed so that at least a part of the gate electrode 3b is embedded.

Therefore, in the configuration of the second embodiment, at least a part of the gate electrode 3b for transistor isolation is formed so as to be buried in the dug portion 1b dug on the transistor isolation side of the semiconductor substrate 1. Due to the reduction in the stacking height associated with the embedding of the part, again, the steepness of the part corresponding to the end of the separation part as in the conventional case is effectively reduced,
The step on the transistor isolation side with respect to the switching element side can be sufficiently reduced. As a result, the gate electrode 5 of the active transistor as a switching element can be easily formed without causing a short circuit between adjacent regions.

In the above-described first and second embodiments, a normal stacked cell is used as a capacitor. However, with the increase in integration and miniaturization, a capacitor having a structure in which a larger capacitance can be obtained in a smaller area is required. It has become. Next, the structure of a memory cell that can meet such a requirement will be described.

FIG. 3 is a cross-sectional view schematically showing a schematic configuration of a memory cell according to a third embodiment of the present invention, in which a first transistor gate electrode 3a having a tapered inclined surface is provided.
Corresponds to the embodiment of FIG. FIG. 4 is a sectional view schematically showing a schematic configuration of a memory cell according to a fourth embodiment of the present invention, which corresponds to the second embodiment in which a gate electrode for transistor isolation is embedded in a semiconductor substrate. ing. In FIGS. 3 and 4, the same reference numerals as those in FIGS. 1 and 2 indicate the same or corresponding parts as those shown in FIGS. 1 and 2.

In the embodiment shown in FIGS. 3 and 4, the bit line 13 and the n ⁺ -type source / drain region 7 of the active transistor
For example, it is made of tungsten and is connected via a plug 16 extending in a direction perpendicular to the main surface of the semiconductor substrate 1.
In the embodiment shown in FIGS. 3 and 4, since there is no inclined portion of the bit line shown in FIGS. 1 and 2, two-bit individual memory cell portions can be arranged close to each other. . Therefore, this structure is suitable for high integration and miniaturization of DRAM.

A pad 15 is interposed between the plug 16 and the source / drain region 7. As will be described later, the pad 15 prevents side walls of the semiconductor substrate 1 and the gate electrode 5 from being etched when a contact hole is opened in the interlayer insulating film 12. Capacitor charge storage electrode 8
Stands for a vertical wall extending in a direction perpendicular to the main surface of the semiconductor substrate 1
Has 81. In the upright wall portion 81, both the inner wall portion and the outer wall portion are used as capacitors. Therefore, the effective surface area of the charge storage electrode 8 used as a capacitor has been dramatically increased. On the gate electrode 5 of the active transistor and the gate electrodes 3a and 3b of the transistor isolation, a shielding film 14 made of, for example, a nitride compound is formed.
As will be described later, the shielding film 14 prevents the insulating film on each gate electrode from being etched.

Next, with reference to FIGS. 5A to 50, a description will be given of the manufacturing process of the memory cell shown in FIG.

Referring to FIG. 5A, for example, the entire main surface side of p-type silicon semiconductor substrate 1 is thermally oxidized to form oxide film 21. Next, a polycrystalline silicon film 22 doped with phosphorus is formed on the oxide film 21 by a low pressure CVD method. Next, an insulating film 23 is formed on the polycrystalline silicon film 22 by a low pressure CVD method. Next, a photoresist film 24 is formed, only a predetermined region is exposed and developed, and the photoresist film 24 is left only in a region to be a separation region.

Next, referring to FIG. 5B, anisotropic etching is performed using the photoresist film 24 as a mask to pattern the insulating film 23 into a predetermined shape. Next, the photoresist film 24 is removed.

Next, referring to FIG. 5C, using the insulating film 23 selectively left in the predetermined region as a mask as described above, the polycrystalline silicon film 22 is anisotropic so as to have a tapered shape rising from the substrate. Etching is performed by etching, isotropic etching, or etching combining them. In this way, a structure having a tapered inclined portion shown in FIG. 5C is obtained.

Next, an insulating film is formed over the entire main surface of the semiconductor substrate by using a low pressure CVD method, and then the formed insulating film is subjected to anisotropic etching. As a result, a gate electrode 3a and a gate insulating film 2a for transistor isolation having the sidewall insulating film 4a on the tapered inclined portion 31 shown in FIG. 5D are obtained.

Next, referring to FIG. 5E, oxide film 25 is formed on the entire main surface of semiconductor substrate 1. Next, a polycrystalline silicon film 26 doped with phosphorus is formed by, for example, a low pressure CVD method, and then an oxide film 27 is formed on the polycrystalline silicon film 26 by, for example, a low pressure CVD method. Next, a photoresist film 28 is formed in a predetermined region by using a photolithography method, and the polysilicon film 26 and the oxide film 27 are etched using the photoresist film 28 as a mask. As a result, as shown in FIG. 5F, the gate electrode 5 and the gate insulating film 4 of the switching element are formed. At the same time, word lines 17 of adjacent memory cells are formed. Next, the gate electrode 5
Then, impurities are ion-implanted into the surface of the semiconductor substrate 1 using the isolation region 20 as a mask. As a result, an impurity region having a relatively low concentration (10 ¹⁶ to 10 ¹⁸ cm ⁻³ ) is formed.

Next, referring to FIG. 5G, an insulating film 29 such as an oxide film is formed on the entire main surface of the semiconductor substrate 1 by, for example, a CVD method. Next, the insulating film 29 is subjected to anisotropic etching. Thereby, as shown in FIG. 5H, sidewalls are formed on the sidewalls of the gate electrode 5 and the sidewalls of the word lines 17.

Next, high concentration impurity ions (10 ¹⁹ to 10 ²¹ cm ⁻³ ) such as As partially overlap the low concentration impurity region 6 using the impurity region 20 and the sidewall formed on the side wall of the gate electrode 5 as a mask. And inject. As a result, as shown in FIG. 5I, source / drain regions 6, 7 having an LDD structure are obtained.

Next, a nitride film is formed on the entire main surface side of the semiconductor substrate 1 by a low pressure CVD method, and the nitride film is patterned into a predetermined shape using a photolithography method and an etching method. As a result, a nitride film 14 is formed on the gate electrode 5, the word line 17, and the gate electrode 3a for transistor isolation.

Next, referring to FIG. 5J, a polycrystalline silicon film is formed on the entire main surface side of the semiconductor substrate 1 by using a reduced pressure CVD method, and the polycrystalline silicon film is formed by photolithography and etching by a predetermined method. Is patterned. As a result, a pad 30 connected to the source / drain regions 6, 7 between the gate electrode 5 and the word line 17 and a pad 15 connected to the source / drain regions 6, 7 between the gate electrode 5 are formed. . Pads 30 and 15 are shaped such that both ends thereof ride on nitride film 14.

Next, referring to FIG. 5K, a thick and flat insulating film 32 is formed on the entire main surface side of semiconductor substrate 1 by using the CVD method. The thickness of the insulating film 32 defines the height of the standing wall portion 81 of the capacitor charge storage electrode formed in a subsequent step. Next, an opening 33 is formed in the insulating film 32 on the pad 30 by using a photolithography method and an etching method. Next, using a low pressure CVD method, the polycrystalline silicon film 34 is
2 and on the inside of the opening 33.

Next, referring to FIG. 5L, the polycrystalline silicon film 34 is selectively removed by anisotropic etching to leave the polycrystalline silicon film 34 only inside the opening 33. By this step, a standing wall portion 81 integrated with the capacitor charge storage electrode 8 or the pad 30 is formed. Next, using the nitride film 14 as a mask, the insulating film 32 is entirely removed. The nitride film 14 protects the gate electrode 5 and the insulating film on the word line 17 from being etched.

Next, referring to FIG. 5M, impurities are implanted into capacitor charge storage electrode 8 having upright wall portion 81 by oblique rotation.

Next, referring to FIG. 5N, a nitride film is formed on the entire main surface of the semiconductor substrate 1 by using a low pressure CVD method, and thereafter, the semiconductor substrate 1 is subjected to a heat treatment in an oxygen atmosphere to form a nitride film. Partially oxidize. Thus, a capacitor insulating film 9 composed of a composite film of a nitride film and an oxide film is obtained. This capacitor insulating film 9 is formed so as to completely cover the surface of the capacitor charge storage electrode 8 and extend on the nitride film 14. Thereafter, a polycrystalline silicon film 10 serving as a capacitor counter electrode (cell plate) is formed on the capacitor insulating film 9 by using a low pressure CVD method. Next, referring to FIG. 50, a thick and flat interlayer insulating film 12 is formed on the entire main surface of the semiconductor substrate 1 by the CVD method. Next, a photoresist film 35 is formed on the interlayer insulating film 12. Next, an opening 36 is formed in a portion of the resist film 35 located on one of the source / drain regions 6 and 7.
Is formed, and a part of the surface of the interlayer insulating film 12 is exposed. Next, using the resist film 35 as a mask, the interlayer insulating film 12 located below the opening 36 is removed by anisotropic etching. At this time, the pad 15 prevents the sidewalls of the source / drain regions 6, 7 and the gate electrode 5 from being etched.

Next, a plug 16 made of, for example, tungsten is formed in the opening 36 so as to connect to the source / drain regions 6 and 7, and then a bit line 13 is formed on the interlayer insulating film 12 so as to connect to the plug 16. Form. By such a process, the third
A memory cell having the structure shown in the figure is obtained.

6A to 6F are views for explaining the steps of forming the buried-substrate transistor isolation structure shown in FIGS. 2 and 4. FIG. Next, with reference to FIGS. 6A to 6F, a method of manufacturing the buried-substrate transistor isolation structure will be described.

Referring to FIG. 6A, an insulating film is formed on the entire main surface of semiconductor substrate 1.
41 is formed, and a photoresist film 42 is applied on the insulating film 41. Next, the photoresist film 42 is patterned into a predetermined shape, anisotropic etching is performed using the photoresist film 42 as a mask, and insulating films other than the insulating film 41 below the photoresist film 42 are removed.

Next, referring to FIG. 6B, anisotropic etching is performed on semiconductor substrate 1 using insulating film 41 as a mask to form groove 43 on the surface of semiconductor substrate 1. Next, an insulating film 44 is formed in the groove 43 of the semiconductor substrate 1, and then a polycrystalline silicon film 45 is formed on the entire main surface of the semiconductor substrate 1.
A resist film 46 is provided on 45 so that the surface becomes flat.

Next, referring to FIG. 6D, the resist film 46 and the polycrystalline silicon film 45 are simultaneously etched back using an etchant such that each has the same etching rate, and the polycrystalline silicon film 45 having a flat surface is formed. To form This polycrystalline silicon film 45 becomes a gate electrode for transistor isolation. Next, the insulating film 41 formed on the surface of the semiconductor substrate 1 other than the groove 43 is removed.

Next, referring to FIG. 6E, an insulating film 47 is formed on the entire main surface side of the semiconductor substrate 1. At this time, the polycrystalline silicon film 45
Is projected from the main surface of the semiconductor substrate 1, the insulating film 47
Is formed so as to cover the protruding portion. Next, the insulating film 47 formed on the main surface of the semiconductor substrate 1 is removed using a photolithography method and an etching method.
In this way, as shown in FIG. 6F, the embedded portion 1b of the substrate
In this case, a gate insulating film 2b for transistor isolation and a gate electrode 3b for transistor isolation are formed. In the method for manufacturing the memory cell shown in FIG. 4, the steps after FIG.
Since the method is the same as that shown in FIGS. 5E to 50, the description will be omitted.

FIG. 7 is a diagram showing a modification of the third embodiment shown in FIG. 3, and FIG. 8 is a diagram showing a modification of the fourth embodiment shown in FIG. In the memory cell shown in FIGS. 7 and 8, unlike the memory cells shown in FIGS. 3 and 4, the nitride film 14 is set up on the pads 30 and 15 forming a part of the capacitor charge storage electrode. It is formed. This structure is obtained by patterning pads 15 and 30 before nitride film 14, that is, by reversing the steps shown in FIGS. 5I and 5J.

In each of the above embodiments, a polycrystalline silicon film is used for each of the gate electrode for transistor isolation, the gate electrode for the active transistor, the capacitor charge storage electrode (storage node), the capacitor counter electrode (cell plate), and the bit line. However, instead of this, a silicide film or a silicide film and a polycrystalline silicon film are used.
A layer film may be used.

In addition, although the LDD structure is adopted as the active transistor, any other transistor that can function as a switching element such as a single transistor, a DDD transistor, or a gate overlap transistor can be used. A similar effect can be obtained.

Further, in the above embodiment, a p-type silicon semiconductor substrate is used as the semiconductor substrate, but an n-type silicon semiconductor substrate may be used. Further, as the substrate, any semiconductor such as a semiconductor other than silicon or a compound semiconductor can be used.

[Effects of the Invention] As described above, according to the present invention, in a memory cell using a transistor isolation including a switching element and a charge storage region in an active region surrounded by the transistor isolation on a semiconductor substrate, According to the first aspect of the present invention, a tapered inclined surface is formed on an end side surface of the gate electrode and the second insulating film on the switching element side so as to gradually rise from the semiconductor substrate side by combining anisotropic etching and isotropic etching. Since the side wall insulating film was formed in a self-aligned manner only on the tapered inclined surface, the step at the switching separation end was effectively reduced,
The formation of the gate electrode in the active transistor section as a switching element can be facilitated. According to the second aspect of the present invention, at least a part of the gate electrode for transistor isolation is buried in the portion dug into the transistor isolation side of the semiconductor substrate. Here again, the formation of the gate electrode in the active transistor as a switching element can be facilitated here, just as in the case of the reduction of the thickness. As a result, inconveniences such as a short circuit between the gate electrodes of the active transistors between adjacent regions do not occur, the occurrence rate of defects can be effectively suppressed, and the structure is relatively simple and easy. It has excellent features such as practicability.

[Brief description of the drawings]

FIG. 1 is a sectional view schematically showing a schematic configuration of a memory cell according to a first embodiment of the present invention. FIG. 2 is a sectional view schematically showing a schematic configuration of a memory cell according to a second embodiment of the present invention. FIG. 3 is a sectional view schematically showing a schematic configuration of a memory cell according to a third embodiment of the present invention. FIG. 4 is a sectional view schematically showing a schematic configuration of a memory cell according to a fourth embodiment of the present invention. 5A to 5O are sectional views showing steps of a method for manufacturing the memory cell according to the third embodiment of the present invention shown in FIG. 6A to 6F are cross-sectional views showing steps of a method for manufacturing the buried transistor isolation gate electrode shown in FIGS. 2 and 4. FIG. 7 is a sectional view showing a modification of the third embodiment of the present invention shown in FIG. FIG. 8 is a sectional view showing a modification of the fourth embodiment of the present invention shown in FIG. FIG. 9 is a sectional view schematically showing a schematic configuration of a conventional stacked memory cell. In the figure, 1 is a p-type silicon semiconductor substrate, 1b is a dug portion of the substrate, 2a is a gate insulating film for transistor isolation, 2b is a gate insulating film for transistor isolation embedded, 3a is a gate electrode for transistor isolation, 3b Is the gate electrode of the buried transistor isolation, 31 is the tapered end of the gate electrode,
4 is a gate insulating film of the active transistor, 5 is a gate electrode of the active transistor, 6 is an n ⁻ type source / drain region of the active transistor, 7 is an n ⁺ type source / drain region of the active transistor, and 8 is a capacitor charge storage electrode ( Storage node), 9 is a capacitor insulating film, 10 is a capacitor counter electrode (cell plate), 11 and 12 are interlayer insulating films, and 13 is a bit line. In the drawings, the same reference numerals indicate the same or corresponding parts.

Continued on the front page. (72) Inventor Wataru Wakamiya 4-1-1 Mizuhara, Itami-shi, Hyogo Mitsubishi Electric Machinery Co., Ltd. LSI Research Institute (72) Inventor Shinichi Sato 4-1-1 Mizuhara, Itami-shi, Hyogo Mitsubishi Electric (56) References JP-A-62-171267 (JP, A) JP-A-57-106063 (JP, A) (58) Fields investigated (Int. Cl. ⁶ , (DB name) H01L 27/108 H01L 21/8242

Claims (2)

(57) [Claims] 1. A stacked type memory cell using transistor isolation, wherein a switching element and a charge storage region are provided in an active region surrounded by transistor isolation on a semiconductor substrate, wherein a first insulating film is provided on the semiconductor substrate. And a second insulating film formed on the gate electrode, wherein an end surface of the gate electrode and the second insulating film on the switching element side has an anisotropic shape. By combining the isotropic etching and the isotropic etching, a tapered inclined surface is formed so as to gradually rise from the semiconductor substrate side, and only on the tapered inclined surface, a sidewall insulating film is formed in a self-aligned manner. , Semiconductor devices. 2. A stacked memory cell using transistor isolation in which a switching element and a charge storage region are provided in an active region surrounded by transistor isolation on a semiconductor substrate, wherein the transistor side of the semiconductor substrate is trenched. And at least a part of the gate electrode of the transistor isolation is buried in the dug substrate, so that a step difference between the transistor isolation side and the switching element side is made as small as possible. , Semiconductor devices.