TWI283805B - Switching control circuit for discontinuous mode PFC converters - Google Patents

Abstract

A switching control circuit having a detection terminal, an input terminal, a ramp generator, a programmable terminal, an error amplifier, a mixing circuit, and a delay circuit for generating a switching signal for power factor control is provided. The detection terminal generates a detection signal in response to the discharge of an inductor. An input terminal is connected for detecting a switching current signal in accordance with the switching current of the inductor. The programmable terminal determines the slew rate of the ramp signal and the maximum on-time of the switching signal. An error amplifier generates an error signal for regulating an output of the PFC converter. The mixing circuit generates a mixing signal proportional to the ramp signal and the switching current signal. The switching signal is turned on in response to the detection signal, and is turned off once the mixing signal is higher than the error signal. The slew rate of the mixing signal is increased in response to the increment of the input voltage. The on-time of the switching signal is increased inversely proportional to the input voltage. Therefore, input current harmonic can be reduced.

Description

1283805 IX. Description of Invention: [Invention Name]: Switching Control Circuit for Discontinuous Mode Power Factor Control Converter [Technical Field] The present invention relates to power factor control, and more particularly to a power factor control in a discontinuous mode Control circuit.

[Prior Art] Most power factor correction techniques use a boost topology (B〇〇st T〇p〇1〇gy) that operates in continuous or non-continuous inductor current mode with fixed or variable switching. Frequency operation. Due to the peak value of the continuous Μ current given at a fixed switching frequency, (10) its higher application. For the low-powered, non-continuous inductor current mode, which often changes the switching frequency, it has several advantages, including: smaller (four) ❹ size, lower cost, simple material, simple, and zero current switching (ZCS) ). Figure 1 illustrates a conventional power factor control converter in which the _switching signal evg is consuming a transistor κ) to switch - the inductor control - the input current Iin. An input current IAe0ffij of the power factor control converter is spread to achieve lower electrical_wave distortion. Fig. 2A and Fig. _ illustrate the waveforms of the input L and ^ according to the input voltage ~ and ViN. The pulse width of the power factor (four) is controlled by the power a error A|§, which is generated by comparing the control waveform with the generated texture waveform. The pulse width varies with power and load conditions, but it should be = electrical: a constant in the cycle. Therefore, the voltage error amplifier must have a lower frequency and lower frequency. There are several advantages to zero current switching. For example, the inductor current is equal in magnitude: the peak release is zero, resulting in higher switching efficiency. Because the inductor current changes 2: and the inductor current starts at zero and returns to zero at each switching cycle, the shape of the electrical r·flow waveform is a triangle whose average value is equal to the peak current current switching just in the continuous (four) continuous current mode. _ edge up 5

1283805 » I Switching frequency is variable. Low Band Width Pulse Width Modulation (PWM) combined with zero current switching provides natural power factor correction for the input current. Figure 3 illustrates the input current Iin waveform of a conventional power factor control converter which is increased as the switching signal VG is enabled. The on-time τ ΟΝ and the wear-on time T0FF represent the charging and discharging periods of the inductor 2 分别, respectively. 4A, 4B, and 4C illustrate three controls P ί and Τ ι - T3, respectively, of a conventional power factor control converter. When the transistor 10 is turned on, the inductor 2 is charged. Once the transistor 1 is turned off, the energy of the inductor 20 is released to the capacitor 50 through the rectifier 30. The output voltage V〇 of the power factor control converter is typically designed to be a higher voltage, such as 4 〇〇V, for better power factor control. Therefore, during discharge of the inductor 20, the parasitic capacitor 15 of the transistor 10 will be charged to a higher output voltage V?. As shown in Fig. 4C, the energy stored in the parasitic capacitor 15 is released to the capacitor 16 (or a parasitic capacitor) after the inductor 20 is completely discharged and before the transistor 10 is turned on. Therefore, a voltage is generated across the capacitor 16.

Vos. Therefore, during the lower input voltage vAC, the voltage vos inhibits the input current Iac flowing through the bridge rectifier 4〇. Figures 5A and 5B illustrate the input current distortion caused by the voltage Vos. Recently, a variety of power factor controlled non-continuous current power factor control controllers have been developed, such as the ST6561 of ST-Microelectrcmics in France and the TDA4862 of Siemens in Germany. Figure 6A illustrates a schematic diagram of an application circuit of the conventional power factor controller 6〇 mentioned above. A multiplier terminal senses the input waveform V1N through the resistors 21 and 22. As shown in the 6th figure, the voltage vM induced at the multiplier end is used to modulate the on-time TGN. The modulated on-time Tgn will lower the voltage v〇s and improve the waveform of the input current. However, the disadvantage of the above method is that the power loss of the resistor 21 is high and the control circuit system is complicated. In addition, the other drawback of the above-mentioned control is the lack of excessive voltage protection, which causes the power factor control converter to be overloaded under excessive voltage conditions. 6 1283805 SUMMARY OF THE INVENTION The purpose of the present invention is to provide a switching control circuit that uses the power factor control of the gods to turn =, which requires the input voltage detection and multiplication H to reduce current micro-distortion. Another object is to provide a method for limiting the maximum output power of the power factor control converter to perform excessive voltage protection. In addition, a maximum switching delay circuit for limiting the switching signal is provided, which reduces the power. The number controls the power loss of the converter at light loads. The switching control circuit includes a detecting end, which is input to the inductor, and generates a shape number input according to the discharge of the inductor, and is used for detecting a switching current signal according to the switching current of the inductor. A ramp generator ' generates a ramp signal depending on the enabling action of the switching signal. - The regulation terminal is connected to the ramp generator to determine the slew rate of the ramp signal and to determine the maximum on-time of the switching signal. A erroneous amplifier is lightly coupled to an output of the power factor control converter to generate an error signal to stabilize the regulation power due to the output of the digital (four) converter. - A hybrid circuit that produces a mixed signal proportional to the ramp signal and the switching current signal. Therefore, the switching signal is enabled in accordance with the detection signal, and when the mixed signal is higher than the error signal, the switching signal is deactivated. The conversion rate of the mixed signal increases as the input power house increases. Therefore, the activation time of the switching signal is proportionally increased as the input voltage is lowered. The input current spectrum is thus reduced. Further, the switching control circuit includes a delay circuit, and the forbidden signal is generated in accordance with the deactivation of the switching signal. The forbidden signal includes a delay time for delaying the activation of the switching signal and limiting the maximum switching of the signal. This delay time increases as the error signal decreases. The error signal is proportionally reduced as the load decreases. Therefore, the power loss of the power factor control converter at light loads is reduced. The above description is only an overview of the present invention. For a better understanding of the technical means of the present invention, and in accordance with the description, the following description of the preferred embodiment of the present invention with reference to the accompanying drawings is as follows: 0 7 1283805 [ Embodiment FIG. 7 is a schematic diagram of a power factor control converter operating in a discontinuous mode in accordance with an embodiment of the present invention. An AC power input is converted to a DC output voltage v〇 via a power factor control converter, which is achieved by the transistor 10 transmitting the energy of the input voltage V1N through the inductor 25, the rectifier 30 and the capacitor 50. The purpose of power factor control is to control the current waveform of the AC power input to a sinusoidal waveform and maintain its phase at the same phase as the power supply input voltage Vac. Through the rectification of the bridge rectifier, the input voltage VIN is always at a positive voltage level relative to the ground of the power factor control converter.

Vin (0 = Vpsin(iyt)

Where Vp=a/JxVin(_ ; input current IIN is also expressed as follows: where Ip =71x1—; The power is determined by the input of the CNC, and the input is the following: Pin = VP XIP/2 〇 If the effect is When considering the towel, the P 神 P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P

!p =(2xP0)/(Vp χη) - twice as large as the zero current switching, as shown in the following equation............................. ...(2) The peak inductor current (lLp) of sensor 25 is the average inductor current

Il'p = (4xP〇) / (Vp .................. The following formula is used to describe the current sense ^ lL (0 = (4 XP〇) ) sin(0Jt) / (VP χ ^_____ (3) The on-time of solving the inductor current. lit{charge the inductor.................... ..(4) lon =1 required to reach the peak current of, for example, I=L(di/dt)

LP :L/VP. (5) 8 1283805 I « T〇n = (4 x P〇χ L) / (Vp x η)------------------- -------------------- T〇FF = (Il-P XL) / (V〇- Vp) T〇ff = (4 x P〇x L) / [(η x Vp) x (V〇~Vp)].....................(7) T=TON ........... ................................................ Output Power P〇 can be expressed by the following equation (6): P〇 = [Vp2 Xη/(4x L)]........................... .................

According to equation (9), the output power p〇 is controlled by the on-time t〇n. Especially for over-voltage protection, limiting the maximum on-time limits the maximum output power. Q. When the AC power is applied to the power factor control converter, it will pass through the inductor 25 and the rectifier 30 to generate a DC output voltage on the capacitor 50. . A switching control circuit 1 is coupled to the output of the power factor control converter through resistors 51 and 52 to receive a feedback signal Vfb. Capacitor 96 is coupled to the COM terminal of switching control circuit 100 to provide frequency compensation for lower bandwidths below the power supply frequency. The switching control circuit 100 outputs a switching signal VG to drive the transistor 10. When the switching signal Vg is enabled, the electromorph 10 is thus driven to conduct, and the inductor 25 is then charged by the conduction of the transistor 1〇. The inductor current is coupled to resistor 90 to produce a switching current signal Vs. Next, the switching current signal Vs is coupled to the VS terminal of the switching control circuit 100. Once the switching current signal vs is higher than a threshold voltage trip, the switching signal ¥(; will be deactivated to make a periodic current limit on the switching action. When the switching signal VG is deactivated, the transistor 1〇 is turned off, the inductor The energy stored in 25 is discharged as a DC output voltage 透过 through the rectifier 30. Once the discharge current of the inductor 25 drops to zero, the auxiliary coil of the inductor 25 detects a zero voltage. The detection terminal VD of the switching control circuit 100 The auxiliary coil is connected to the auxiliary coil through the resistor 23 for detecting a zero current state. A detection signal is generated after detecting the zero current state, so that the switching control circuit 100 can start the next switching cycle. FIG. 8 illustrates a first switching cycle according to the present invention. A schematic diagram of the switching control circuit 1A of the embodiment. A ramp generator 300 generates a ramp signal RMP and a maximum duty cycle signal MD according to the switching signal VG. A MOT terminal is coupled to the ramp generator 300 to determine the ramp signal. The slope of the RMP and the maximum on-time of the switching signal Vg. Figure 7 illustrates the switching from the MOT terminal connected to the ground of the switching control circuit 100 to determine the switching. The maximum on-time number of the VG. Maximum on-time of the switching signal VG in turn limits the minimum switching frequency of the switching signal Vg, so as to avoid the switching frequency falls within the audio band. Negative terminal of an error amplifier 120 9

1283805 1 · The output coupled to the power factor control converter receives the feedback signal VFB, and the positive terminal of the error amplifier 120 is coupled to a reference voltage VR to generate an error signal at the output of the error amplifier 120 for stabilization. Adjust the output of the power factor control converter. The error amplifier 120 is a trans-conductance error amplifier. The output of error amplifier 120 is in turn coupled to the COM terminal of switching control circuit 100 and an input of a delay circuit 200. The mixing circuit 350 produces a mixed signal Vw that is proportional to the ramp signal RMP and the switching current signal Vs. Comparator 115 has a negative input and a positive input coupled to the output of error amplifier 120 and mixed signal Vw, respectively. The output of comparator 115 produces a first reset signal and is coupled to a first input of an OR gate 135. Comparator 116 generates a second reset signal and is coupled to OR gate 135 - the second input. A third input of the OR gate 135 is coupled to the maximum duty cycle signal MD. The threshold voltage VR2 and the switching current signal Vs are coupled to the two inputs of the comparator 116, respectively, for achieving periodic current limiting. An output of the OR gate 135 is used to reset the flip-flop 140. The flip-flop 140 is used to generate the switching signal VG. The sense terminal VD and the threshold voltage VR1 are coupled to the two inputs of the comparator 110, respectively. Therefore, once the voltage VD of the detecting terminal VD is lower than the threshold voltage VR1, a detection signal is generated. The detection signal is passed through an input of the AND gate 130 to enable the flip-flop 140. Therefore, the switching signal VG is turned on in accordance with the detection signal, and once the mixed signal Vw is higher than the error signal, the switching signal VG is turned off. Further, the delay circuit 200 generates a disable signal INH in accordance with the deactivation of the switching signal VG. The disable signal INH is coupled through an inverter 131 to the other input of the AND gate 130. The inhibit signal INH includes a delay time for delaying the turn-on of the switching signal VG and limiting the highest switching frequency of the switching signal VG. Fig. 9 is a circuit diagram showing a delay circuit 2A according to an embodiment of the present invention, in which a charging current Ic and a capacitor 260 determine the delay time of the delay circuit 200. An operational amplifier 210 is coupled to the COM terminal to receive the error signal. Another operational amplifier 215 is supplied by the threshold voltage VR3. The operational amplifiers 210, 215, the resistors 205, and the transistors 220, 230, 231 generate a current 1231. Current 1231 and current source 250 determine the charging current Ic. Current source 250 provides a minimum charging current. The current 1231 is generated proportionally with the error signal, and thus the delay time increases as the error signal decreases. The error signal decreases proportionally as the load decreases. The threshold voltage VR3 determines the range of the error signal under light load conditions. When the switching signal VG is turned on, the transistor 270 discharges the capacitor 260. The capacitor 260 is charged in accordance with the deactivation of the switching signal VG. An inverter 280 is coupled to capacitor 260 to generate a disable signal INH. 10 (10) - (11)

1283805

I I In accordance with the zero current switching and discontinuous mode power factor control conversion of the present invention, the next switching cycle begins at the boundary of the zero inductor current state. The energy £ can be expressed as: 6* = Lx I2 /2........................... Power factor control conversion The output power p〇 supplied by the device is expressed as: ρο =[νρ2χηχΤΟΝ2 /(4xLxT)]........................ where T = T〇n + T〇ff 0 When the load of the power factor control converter is reduced under light load conditions, the delay time Td is relatively increased and inserted before the start of the next switching cycle. Therefore, the switching period of the switching signal is extended to: T - Ding on + T0FF + Td------------------------------- ----------------------- (12) Thus, under light load and no load conditions, the switching frequency of the switching signal is reduced. The power loss of the power factor control converter is thus reduced. FIG. 10 illustrates a ramp generator 300 in which an operational amplifier 310 includes a reference voltage Vr4. The operational amplifier 310, the transistors 315, 316, 317 are combined with the resistor 95 of Fig. 7 to generate a current Ian. Current Ian is used to charge a capacitor 319. A ramp signal RMP is generated on capacitor 319. The current Isn determines the slope of the ramp signal RMP. A reverse gate 320 is coupled to transistor 318, a first input receiving a switching signal VG and discharging capacitor 319 when switching signal VG is deactivated. Further, once the voltage of the capacitor 319 is higher than the threshold voltage vRS, the capacitor 319 is discharged to limit the maximum on-time of the switching signal vG. The output of comparator 325 is used to reset flip flop 330. Inverter 331 is coupled to the output of comparator 325 to produce a maximum duty cycle signal MD. The flip-flop 330 is set by the switching signal VG. The output of the flip-flop 330 is coupled to a second input of the AND gate 32A. Therefore, the current Im7, the capacitor 319, and the threshold voltage VRS determine the maximum width of the ramp signal RMP, and in turn determine the maximum on-time of the switching signal \^. Figure 11 is a circuit diagram of a hybrid circuit 350 in accordance with an embodiment of the present invention. The operational amplifier 361, the resistor 391 and the transistors 373, 374, 375 form a voltage to current converter. A ramp signal RMP is coupled to the voltage to current converter to convert the ramp signal RMP to a current 1375. The switching current signal Vs is coupled to the buffer amplifier 362. Current 1375 is coupled through resistor 392 to a buffer amplifier 362. Therefore, a mixed signal Vw is generated on the resistor 392, which is proportional to the ramp signal RMP and the switching current signal Vs. The slew rate of the switching current signal vs increases as the input voltage of the power factor control converter 11 1283805 increases. In contrast, the slope of the mixed signal is increased as the input voltage Vw increases. Therefore, the on-time of switching the fg number VG increases and is inversely proportional to the input voltage ViN. By modulating the on-time of the switching signal VG, the input current harmonics are thus reduced. The above is only a preferred embodiment of the present invention, and is not intended to limit the present invention in any way. Although the invention has been disclosed as a preferred embodiment, it is not intended to be a A person skilled in the art, in the technical scope of the present invention, may smatter the equivalent structure of the structure and technical content disclosed above to be modified into a scale change, without departing from the technical content of the present invention. Any simple modification, manufacturing change, and repair made by the essence of the invention should be within the technical scope of the present invention. [Circular Brief Description] The drawings are intended to further understand the present invention and are inseparable from the description and are part of the specification. The drawings illustrate the embodiments of the invention, and are intended to illustrate the principles of the invention. Figure 1 is a schematic diagram of a conventional power factor control converter. 2A and 2B1I illustrate the input current waveforms generated by the conventional power factor control conversion test input voltage. Figure 3 illustrates the input current waveform generated from the switching signal. Figures 4A, 4B and 4C illustrate three control stages of a conventional power factor control converter. 5A and 5B illustrate waveform distortion of a conventional power factor control converter input current. Figure 6A is a circuit diagram of a conventional power factor control converter in which the control H of the power factor control converter includes a multiplier for improving the Wei distortion of the input current. Figure 6B illustrates the modulated on-time controlled by the multiplier. Figure 7 is a schematic illustration of a power factor control converter in accordance with an embodiment of the present invention. Figure 8 is a schematic diagram of a switching control circuit in accordance with an embodiment of the present invention. Figure 9 is a circuit diagram of a delay circuit in accordance with an embodiment of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a circuit diagram of a ramp generator in accordance with an embodiment of the present invention. 12

1283805 Figure 11 is a circuit diagram of a hybrid circuit in accordance with an embodiment of the present invention. [Description of main component symbols] 10, 230, 231, 270, 315, 316, 317, 318, 373, 374, 375: transistors 20, 25: inductors 21, 22, 23, 51, 52, 90, 95, 205, 391, 392: Resistor 30. Rectifier 40: Bridge Rectifier 50, 96, 260, 319: Capacitor 60: Conventional Power Factor Controller 100: Switching Control Circuits 110, 115, 116, 325: Comparator 120 : Error amplifier 130: AND gates 131, 280, 331: inverter 135: or gates 140, 330: flip-flops 200: delay circuits 210, 215, 310, 361: operational amplifier 250: current source 300: ramp generator 320: NAND gate 350: hybrid circuit 362: buffer amplifier 13 1283805

Iac, IlN: Input current INH: Forbidden signal MD: Maximum duty cycle signal RMP: Ramp signal TON: On time T〇ff: Off time VAC, VIN: Input voltage VD: Voltage

VFB: feedback signal VG: switching signal V〇s: voltage VR: reference voltage VR1: threshold voltage VR2: threshold voltage

Vs: switching current signal

Vw: mixed signal

14

Claims (1)

12838Q5 --- '' - —.: — : 一—_十—一一1”-.η:,.:-Λ ΐ 9α 2;t)i! X. Patent scope: 1 for one power a switching control circuit of the factor control converter generates a switching signal for switching an inductor for power factor control, comprising: a detection terminal coupled to the inductor, generating a signal according to the discharge of the inductor Detecting a signal; an input terminal is configured to detect a switching current signal according to a switching current of the inductor; a ramp generator generates a ramp signal according to the switching signal; and an adjustment terminal 'coupled to the slope generator a method for determining a conversion rate of the ramp signal and determining a maximum on time of the switching signal; an error amplifier coupled to an output of the power factor control converter for generating an error signal to stably adjust the An output of the power factor control converter; and a hybrid circuit 'generating a mixed signal, the mixed signal being proportional to the ramp signal and the switching current signal; wherein the switching signal is based on the detection signal And when the mixed signal is higher than the error signal, the switching signal is deactivated. 2. The switching control circuit described in the scope of the patent application, further comprising a delay circuit, according to the deactivation of the switching signal And generating a forbidden signal, wherein the forbidden signal includes a delay time for delaying the enabling action of the switching signal and for limiting the highest switching frequency of the switching signal. 3. The switching control circuit of claim 2, wherein the delay time increases as the error signal decreases, and the error signal decreases proportionally with a decrease in load. 4. The switching control circuit of claim 1, wherein the switching rate of the switching current signal is increased in accordance with an increase in an input voltage of the power factor control converter. 5. A switching control circuit for a power factor control converter, generating a switching number for switching an inductor for power factor control, wherein the switching control circuit comprises: a detection terminal coupled to The inductor generates a detection signal according to the discharge of the inductor; 15 128,3 8Q5 ^ - Year Month M. gH) 1------ - Oblique, generate $, generated according to the switching money - ramp signal; one tone is the end 'its __ ramp generator, The wire determines the slope (four)_change rate and determines the maximum on-time of the switching signal; and, the amplification amplifies the output terminal of the power factor control converter of the dragon, and the wire generates an error signal to adjust the coefficient (four) conversion Off-output; , ', the switch is enabled according to the detection signal; and the switching signal is deactivated according to the comparison of the ramp signal with the error signal. 6. The switching control circuit of claim 5, further comprising a delay circuit for generating a disable signal according to a deactivation action of the lion, wherein the forbidden signal comprises a delay time to The activation action of the switching signal is delayed, and the highest switching frequency of the switching signal is limited. 7. The switching control circuit according to item 6 of the scope of the patent, wherein the delay time of the towel increases as the load decreases. 8. The switching control circuit of claim 5, wherein the switching rate of the switching current signal increases as the input voltage of the power factor control converter increases. 9. A switch-controlled weave H-switching signal for switching to an inductor for power factor control, comprising: a detecting terminal 'lighting-inductor, according to the inductor The discharge generates a detection signal; the _ input terminal is used to detect-switch the current signal according to the switching current of the inductor; - the ramp generator generates a ramp signal according to the switching signal; and an error amplifier coupled And an output of the power factor control converter is configured to generate an error signal for controlling the output of the power factor converter; and the circuit generates a mixed signal proportional to the ramp signal and the switching current signal; The switching signal is enabled according to the detection signal; and the switching signal is deactivated according to the comparison of the mixed signal and the error signal. 16 128.3805 \ 11 Iiui 仪修修 (more) replacement page.. '· 0 1 _ 10 · The switching control circuit according to claim 9 of the patent application, further comprising a delay circuit according to the switching The signal is turned off to generate a forbidden signal, wherein the forbidden signal includes a delay time for delaying the enabling action of the switching signal and for limiting the highest switching frequency of the switching signal. 11. The switching control circuit of claim 10, wherein the delay time increases as the load decreases. /2. The switching control circuit of claim 9, wherein the switching rate of the switching current signal is increased in accordance with an increase in an input voltage of the power factor control converter. 17