JP2007037297A - Power factor improvement circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a power factor improvement circuit that is of simple construction and capable of improving a power factor. <P>SOLUTION: The power factor improvement circuit includes: a rectifier D1 that rectifies alternating-current input voltage and outputs it as input voltage; a circuit, connected between the rectifier and an output end, in which a reactor L and a switching element Q1 are connected in series; a circuit, connected across the switching element, in which a backflow preventing diode D2 and an output smoothing capacitor C1 are connected in series; and a control circuit 10 to 15, CP2, FF1 that controls turn-on/off of the switching element. The power factor improvement circuit obtains direct-current output voltage from both ends of the output smoothing capacitor. The control circuit operates as follows: when the switching element is on, it determines the on period of the switching element based on output voltage; when the switching element is off, it detects that the reactor current passed through the reactor has become equal to a value determined based on the input voltage outputted from the rectifier, thereby determines an off period. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a step-up chopper type power factor correction circuit for improving the power factor of an AC input in a power supply device that converts an AC input voltage into a DC voltage.

  2. Description of the Related Art Conventionally, there is known a power supply device that obtains a DC voltage by rectifying an AC input voltage using a diode and then smoothing the AC input voltage using a smoothing capacitor. In this power supply device, current flows only when the instantaneous value of the AC input voltage is higher than the voltage of the smoothing capacitor. Therefore, there is a problem that the input current does not have a waveform proportional to the input voltage, the power factor is deteriorated, and a harmonic current is generated. Therefore, in order to improve the power factor and harmonic current, a step-up chopper type power factor correction circuit is provided before the smoothing capacitor, and the waveform is shaped so that the input current waveform is proportional to the input voltage waveform. Yes.

  As the operation of such a power factor correction circuit, there are a reactor current discontinuous mode in which the reactor current flowing through the reactor becomes zero once in each switching cycle and a reactor current continuous mode in which the reactor current continuously flows, which are required. Depending on the output power to be used. In general, the reactor current discontinuous mode in which the diode loss due to the diode recovery current is small when the output power is relatively small, and the reactor current continuous mode in which the effective value of the switching current can be lowered in the case of a large output is used.

  FIG. 10 is a diagram showing an example of a conventional boost chopper type power factor correction circuit. The power factor correction circuit operates in the reactor current continuous mode, and controls the average value of the reactor current so as to be proportional to the input voltage.

  That is, first, the multiplier 50 outputs a signal from the error amplifier A1 that amplifies an error between a voltage obtained by dividing the output voltage by the output dividing resistor R1 and the output dividing resistor R2 and a predetermined reference voltage Vref, and the rectifier D1. Is multiplied by the voltage from the input voltage detection unit 12 that detects the input voltage of the current to generate a target value of the reactor current. Current error amplifier 51 compares the target value with the average value of the reactor current from reactor current detection unit 13.

  Then, the PWM comparator 54 compares the comparison result output from the current error amplifier 51 with the output of the sawtooth wave oscillation circuit 53. The switching element driving circuit 15 controls on / off of the switching element Q1 by the output of the PWM comparator 54, and controls so that an input current proportional to both the input voltage and the control signal from the error amplifier A1 is obtained.

  As a related technique, Patent Document 1 discloses a power factor correction circuit used for a switching power supply circuit or the like. This power factor improvement circuit uses a PWM control IC for power factor improvement in a circuit having a boost chopper circuit, applies a reference voltage Vref to the inverting input terminal of the non-inverting error amplifier, Add output voltage signal. To match these phases, capacitors are combined to delay the change in voltage so that they are in the same phase.

Further, in order to make the input current a waveform similar to the input voltage waveform, a minute signal inverted with respect to the input voltage is injected into the inverting input terminal of the non-inverting error amplifier. The output of the non-inverting error amplifier and the triangular wave signal of the oscillator are compared by a comparator to obtain a pulse output, which is directly used as the gate signal of the switching element, and the boost chopper circuit operates. In this manner, the PWM control IC can be used to control only the input current waveform and the output voltage.
Japanese Patent Laid-Open No. 5-111246

  However, in the above-described conventional power factor correction circuit, two control systems such as a control system using the error amplifier A1 of the output voltage and a control system for causing the average value of the reactor current to become the target value, and the target value Therefore, an analog multiplier 50 is required to create the control circuit, which complicates the control circuit. In addition, the multiplier 50 has a problem that it is difficult to control in a wide voltage range because the input voltage range is limited.

  In addition, in the technique for simplifying the control circuit as disclosed in Patent Document 1, fine conditions are necessary for setting and adjusting circuit constants for bringing the input current waveform close to the similar waveform of the input voltage waveform. is there. Therefore, there are problems that it is difficult to design and adjust, and that it is easily affected by variations and variations in constants.

  An object of the present invention is to provide a power factor correction circuit having a simple configuration and capable of improving the power factor.

  The present invention has the following configuration in order to solve the above-described problems. According to a first aspect of the present invention, there is provided a rectifier that rectifies an AC input voltage and outputs the rectifier as an input voltage, a first series circuit connected between an output terminal of the rectifier and a reactor and a switching element connected in series, and the switching A second series circuit connected between both ends of the element, in which a backflow prevention diode and an output smoothing capacitor are connected in series, and a control circuit for controlling on / off of the switching element, and outputs a direct current from both ends of the output smoothing capacitor In the power factor correction circuit for obtaining a voltage, the control circuit determines an on period of the switching element based on the output voltage when the switching element is on, and flows to the reactor when the switching element is off. Detects that the reactor current has reached a value determined based on the input voltage output from the rectifier And determining the off period Te.

  According to a second aspect of the present invention, in the first aspect of the present invention, the control circuit includes an error amplifier that amplifies an error voltage between the output voltage and the first reference voltage, and the error amplifier when the switching element is on. Is output from the rectifier, and an ON period control unit that ends the ON period of the switching element and initializes the integration result when the integration result becomes larger than the second reference voltage. An input voltage detection unit that detects an input voltage; an integration circuit that integrates an output of the input voltage detection unit during an on period of the switching element; and an integration circuit that retains an integration result during an off period of the switching element; and a reactor that flows through the reactor Reactor current detection unit for detecting current, the output of the reactor current detection unit and the output of the integration circuit are compared, and the reactor current detection When the output of the is determined that becomes smaller than the output of the integration circuit, to turn on the switching element, and is characterized in that the integration result of the integrating circuit and a comparator circuit to be initialized.

  According to a third aspect of the present invention, in the invention of the second aspect, the reactor includes an auxiliary winding, and the input voltage detection unit detects a voltage generated in the auxiliary winding when the switching element is on. It is characterized by that.

  According to a fourth aspect of the invention, there is provided a voltage holding circuit for holding the output of the integrating circuit when the switching element is turned off. The integrating circuit receives the output of the input voltage detecting unit. And the comparator circuit compares the output of the reactor current detector with the output of the voltage holding circuit when the switching element is off, and the output of the reactor current detector is the output of the voltage holding circuit. When it is determined that the voltage has become smaller, the switching element is turned on, and the integration result in the integration circuit and the voltage held in the voltage holding circuit are initialized.

  The invention according to claim 5 is the invention according to claim 2, further comprising a second comparison circuit that compares the output of the integration circuit with a predetermined voltage, wherein the output of the integration circuit exceeds a predetermined voltage. The switching element is turned off when judged by the second comparison circuit.

  According to the first and second aspects of the present invention, the ON width of the switching element is determined according to the output voltage, and the OFF period is determined by detecting that the reactor current has reached a value determined based on the input voltage. As a result, the output voltage is stabilized and the input current is similar to the input voltage. In addition, since the multiplier often used in the conventional power factor correction circuit is not used, the circuit is simplified and integration is facilitated.

  According to the invention of claim 3, since the voltage of the auxiliary winding of the reactor is used for detecting the input voltage, the loss can be reduced as compared with the case where the input voltage is directly detected by the resistance. Further, since the voltage of the auxiliary winding is generated in the reverse direction when the switching element is off, a configuration for integrating only when the switching element is on can be realized with a simple circuit.

  According to the invention of claim 4, the integration circuit always integrates the output of the input voltage detection unit, and the output of the integration circuit is held in the voltage holding circuit (sample hold circuit) simultaneously with the switching element being turned off, Simultaneously with the turning on of the element, the integration circuit and the voltage holding circuit are initialized. Therefore, the configuration for stopping the integration and holding the integration result is not required in the integration circuit, so that the circuit can be simplified.

  According to the invention of claim 5, since the switching element is turned off when the output of the integrating circuit reaches a predetermined voltage, the ON width of the switching element is limited and functions as overcurrent protection. When the input voltage is high, the output of the integration circuit quickly becomes a predetermined voltage, and when the input voltage is low, the predetermined voltage is late. Therefore, when the input voltage is high, the ON width of the switching element becomes short. Therefore, even if there is a change in the input voltage, a correction is made for the limitation of the output current, and the detection of the overcurrent protection does not vary depending on the input voltage.

  Hereinafter, a power factor correction circuit according to an embodiment of the present invention will be described in detail with reference to the drawings.

  FIG. 1 is a diagram showing a configuration of a power factor correction circuit according to Embodiment 1 of the present invention. The power factor correction circuit includes a rectifier D1, a reactor L, a switching element Q1, a backflow blocking diode D2, an output smoothing capacitor C1, an output dividing resistor R1, an output dividing resistor R2, an error amplifying unit 10, an on period control unit 11, an input voltage. The detection unit 12 includes a reactor current detection unit 13, an integration circuit 14, a comparison circuit CP 2, a flip-flop FF 1, and a switching element drive circuit 15.

  Between the output terminal of the rectifier D1 for full-wave rectification of the AC input voltage from the AC power supply Vac, a reactor L, a switching element Q1 composed of a MOSFET and the like, and a current detection resistor R7 constituting a part of the reactor current detection unit 13 A series circuit is connected. A series circuit composed of a backflow blocking diode D2 and an output smoothing capacitor C1 is connected to both ends (between the drain and source) of the switching element Q1 to constitute a rectifying and smoothing circuit. A series circuit composed of an output dividing resistor R1 and an output dividing resistor R2 is connected to both ends of the output smoothing capacitor C1. The load LD is connected between both ends of the output smoothing capacitor C1.

  A switching element drive circuit 15 is connected to a control terminal (gate) of the switching element Q1. The switching element driving circuit 15 generates a driving signal in accordance with a signal output from the output terminal (indicated by Q) of the flip-flop FF1, and controls on / off of the switching element Q1 by the driving signal. The set input terminal (S) of the flip-flop FF 1 is connected to the output terminal of the comparison circuit CP 2, and the reset input terminal (R) is connected to the output terminal of the comparator CP 1 constituting the on-period control unit 11. Further, the inverting output terminal (indicated by the Q bar) of the flip-flop FF1 is connected to the on-period control unit 11 and the integration circuit 14.

  The inverting input terminal (−) of the comparison circuit CP2 is connected to the reactor current detection unit 13, and the non-inverting input terminal (+) is connected to the integration circuit 14. The output terminal of the comparison circuit CP2 is connected to the flip-flop FF1 and to the integration circuit 14.

  The error amplifying unit 10 is connected to a connection point between the output dividing resistor R1 and the output dividing resistor R2, and includes an error amplifier A1, a voltage source that generates a reference voltage Vref, and a capacitor C2. The error amplifier A1 includes a voltage input to the non-inverting terminal (+) (a voltage obtained by dividing the output voltage by the output dividing resistor R1 and the output dividing resistor R2), and a reference voltage Vref input to the inverting terminal (−). And output the error. Further, a capacitor C2 is provided between the output terminal and the non-inverting terminal (+) of the error amplifier A1, and the phase is corrected by the capacitor C2. The error amplifier is used in a general boost chopper type power factor correction circuit. Similarly to the above, it is set so as not to respond to the half cycle of the input AC voltage. The error voltage output from the error amplifier A1 is sent to the on period control unit 11.

  The on period control unit 11 generates a signal for controlling the on period of the switching element Q1 based on the output of the error amplification unit 10 and the output of the flip-flop FF1, and sends the signal to the flip-flop FF1. Specifically, the on-period control unit 11 includes a voltage-current converter (hereinafter referred to as a VI converter) 11a, a transistor Q2, an integration capacitor C3, a comparator CP1, and a voltage source that generates a voltage Von. .

  The VI converter 11a converts the error voltage from the error amplifier A1 into a current. The output terminal of the VI converter 11a is connected to the drain of the transistor Q2, one end of the integrating capacitor C3, and the non-inverting terminal (+) of the comparator CP1. The gate of the transistor Q2 is connected to the inverting output terminal of the flip-flop FF1, and the source is connected to the ground line. The other end of the integrating capacitor C3 is connected to the ground line. The negative electrode of the voltage source that generates the voltage Von is connected to the ground line, and the positive electrode is connected to the inverting terminal (−) of the comparator CP1. The output terminal of the comparator CP1 is connected to the reset input terminal (R) of the flip-flop FF1.

  The on-period controller 11 configured as described above operates as follows. That is, since the flip-flop FF1 is reset during the OFF period of the switching element Q1, the signal output from the inverting output terminal of the flip-flop FF1 becomes a high level (hereinafter referred to as “H level”), and the transistor Q2 Turn on. As a result, the voltage of the integrating capacitor C3 is kept at zero.

  When the flip-flop FF1 is set and the switching element Q1 is turned on, the signal output from the inverting output terminal of the flip-flop FF1 becomes low level (hereinafter referred to as “L level”), and the transistor Q2 is turned off. As a result, the integrating capacitor C3 is charged with a current obtained by converting the error voltage from the error amplifying unit 10 by the VI converter 11a. When the voltage of the integrating capacitor C3 reaches the voltage Von, the output of the comparator CP1 becomes H level, the flip-flop FF1 is reset, and the switching element Q1 is turned off. With the above operation, the on period control unit 11 controls the period from when the switching element Q1 is turned on to when it is turned off according to the error signal from the error amplifying unit 10.

  The input voltage detection unit 12 is configured by a resistor R4 provided between the output terminal on the positive electrode side of the rectifier D1 and the integration circuit 14. Generally, an input voltage obtained by rectifying an AC input voltage is sufficiently higher than a voltage handled by an internal control circuit. Therefore, the input voltage is detected as a current substantially proportional to the input voltage by the resistor R4.

  The reactor current detection unit 13 includes a resistor R5, a resistor R6, a current detection resistor R7, and an operational amplifier A2. The current detection resistor R7 is connected between the ground line and the output terminal on the negative side of the rectifier D1. The non-inverting terminal (+) of the operational amplifier A2 is connected to the ground line, and the inverting terminal (−) is connected to the output terminal on the negative side of the rectifier D1 through the resistor R6. The output terminal of the operational amplifier A2 is connected to the inverting terminal (−) via the resistor R5 and to the inverting terminal (−) of the comparison circuit CP2.

  In the reactor current detection unit 13 configured as described above, the current flowing through the reactor L is detected as a voltage drop by the current detection resistor R7. The voltage detected by the current detection resistor R7 is inverted and amplified by an inverting amplifier circuit composed of the resistor R5, the resistor R6, and the operational amplifier A2, and is applied to the inverting terminal (−) of the comparison circuit CP2 as a voltage proportional to the reactor current. Sent.

  The integration circuit 14 includes a transistor Q3, a diode D3, a transistor Q4, and an integration capacitor C4. The drain of the transistor Q3 is connected to the input voltage detector 12 (resistor R4), the gate is connected to the inverting output terminal of the flip-flop FF1, and the source is connected to the ground line. The anode of the diode D3 is connected to the input voltage detector 12 (resistor R4), and the cathode is connected to one end of the integrating capacitor C4. The other end of the integrating capacitor C4 is connected to the ground line. The drain of the transistor Q4 is connected to the non-inverting terminal (+) of the comparison circuit CP2 and the cathode of the diode D3, the gate is connected to the output terminal of the comparison circuit CP2, and the source is connected to the ground line.

  The integrating circuit 14 configured as described above operates as follows. The transistor Q3 functions as a switch that determines the integration period. When the transistor Q3 is on, the current from the resistor R4 flows through the transistor Q3 and the integrating capacitor C4 is not charged. Further, since the discharge of the integration capacitor C4 is also blocked by the diode D3, the voltage across the integration capacitor C4 does not change. On the other hand, when the transistor Q3 is turned off, the integrating capacitor C4 is charged with a current proportional to the input voltage through the resistor R4 and the diode D3.

  The comparison circuit CP2 compares the voltage detected by the reactor current detection unit 13 with the voltage of the integration capacitor C4, and sets the flip-flop FF1 when the voltage detected by the reactor current detection unit 13 falls below the voltage of the integration capacitor C4. Then, the switching element Q1 is turned on. At the same time, the transistor Q4 is turned on to discharge the integrating capacitor C4. Thereby, the integrating capacitor C4 is initialized.

  Next, the operation of the power factor correction circuit according to Embodiment 1 of the present invention configured as described above will be described with reference to the timing chart shown in FIG.

  Now, as shown in FIG. 2C, when the output of the comparison circuit CP2 becomes H level at time t1, the transistor Q4 of the integration circuit 14 is turned on, and the integration capacitor C4 is discharged, and FIG. As shown, the voltage of the integrating capacitor C4 becomes zero. That is, the integration circuit 14 is initialized. When the voltage of the integrating capacitor C4 becomes zero, the output of the comparison circuit CP2 becomes L level, and the transistor Q4 is turned off.

  Further, when the output of the comparison circuit CP2 becomes H level, the flip-flop FF1 is set. As shown in FIG. 2B, the output of the flip-flop FF1 is applied to the gate of the switching element Q1 via the switching element driving circuit 15, and the switching element Q1 is turned on. Thereby, as shown to Fig.2 (a), a reactor current begins to increase.

  When the flip-flop FF1 is set, the transistor Q2 of the on period control unit 11 is turned off, and the error voltage output from the error amplification unit 10 is converted into a current by the VI converter 11a and supplied to the integration capacitor C3. The As a result, charging of the integrating capacitor C3 is started, and the voltage of the integrating capacitor C3 starts to rise as shown in FIG. 2 (g).

  When the flip-flop FF1 is set, the transistor Q3 is turned off. As shown in FIG. 2E, charging of the integrating capacitor C4 is started with a current proportional to the input voltage through the resistor R4 and the diode D3. Is done.

  In this state, as shown in FIG. 2 (f), when the voltage of the integrating capacitor C3 reaches the voltage Von at time t2, the output of the comparator CP1 of the on period control unit 11 becomes H level, and the flip-flop FF1 is reset. As shown in FIG. 2B, the output of the flip-flop FF1 is applied to the gate of the switching element Q1 via the switching element driving circuit 15, and the switching element Q1 is turned off. As a result, the ON period of the switching element Q1 ends, and the reactor current starts to decrease as shown in FIG.

  Further, when the flip-flop FF1 is reset, the transistor Q2 is turned on, the integration capacitor C3 of the on period control unit 11 is discharged, and the voltage of the integration capacitor C3 becomes zero as shown in FIG. 2 (g). It is initialized. At the same time, since the transistor Q3 is turned on, the current from the input voltage detection unit 12 flows to the transistor Q3. Thereby, the charging of the integrating capacitor C4 is stopped, and as shown in FIG. 2E, the voltage across the integrating capacitor C4 remains the voltage at the time when the switching element Q1 is turned off.

  When the switching element Q1 is turned off, the current flowing through the reactor L is reduced, the voltage drop of the current detection resistor R7 is reduced, and the output voltage of the reactor current detection unit 13 is also lowered as shown in FIG.

  When the output voltage of the reactor current detection unit 13 reaches the voltage across the integration capacitor C4 at time t3, the output of the comparison circuit CP2 becomes H level, the flip-flop FF1 is set, the switching element Q1 is turned on again, and the transistor Q3 is turned on. Turn off. By repeating the above operation, switching of the switching element Q1 is continued.

  As a whole, the operation as shown in FIG. 3 is performed by the above operation. That is, the error amplifying unit 10 is set so as not to respond in the period of the input AC voltage by the phase correction by the capacitor C2. Therefore, in the half cycle of the input AC voltage, as shown in FIG. 3, the time from when the output of the comparison circuit CP2 is generated until the output of the comparator CP1 in the on-period control unit 11 is almost changed. However, the ON period of the switching element Q1 is substantially constant in the half cycle of the AC input voltage.

  Then, by integrating the current proportional to the input voltage by the integrating capacitor C4 only during the ON period of the switching element Q1, a voltage proportional to both the ON period and the input voltage is obtained in the integrating capacitor C4 after the ON period ends.

  Since the integration capacitor C4 stops charging after the ON period of the switching element Q1 ends, the integration capacitor C4 maintains the voltage after the ON period ends. The comparison circuit CP2 compares the voltage of the integrating capacitor C4 with the output voltage of the reactor current detection unit 13, and continues to turn off the switching element Q1 until both voltages match. When both voltages match, the switching element CP2 Turn on Q1. Thus, the reactor current at the moment when the switching element Q1 is turned on is proportional to both the on period and the input voltage. Therefore, the envelope of the valley of the reactor current shown in FIG. 3 is proportional to both the input voltage and the on period.

  Also, the current ΔI that rises during the on period of the switching element Q1 from the valley point of the reactor current shown in FIG. 3 is proportional to both the on period and the input voltage because the inductance of the reactor L is constant. . As a result, the peak envelope of the reactor current is also proportional to both the input voltage and the on period.

  Since the reactor current is a triangular wave, the average value thereof is also proportional to both the on period and the input voltage, and the input current of the power factor correction circuit according to the first embodiment is proportional to both the input voltage and the on period. For this reason, when the ON period of the switching element Q1 is controlled so that the output voltage becomes the target value by the circuit configuration described above, the input current becomes a waveform proportional to the input voltage, and the improvement of the power factor and the suppression of the input harmonics are prevented. It becomes possible.

  Here, the operation when the capacitance value of the integrating capacitor C4 fluctuates low will be described. Assuming that the capacitance of the integrating capacitor C4 fluctuates low, the integration period and the integration current remain unchanged, and the integrated voltage rises according to the fluctuation of the capacitance value. As the integrated voltage increases, the initial value of the switching current of the switching element Q1 determined thereby increases.

  If the ON period of the switching element Q1 is kept as it is, the switching current increases and the output voltage rises. Then, the ON width of the switching element Q1 is reduced by the functions of the error amplifier 10 and the ON period controller 11 that control the output voltage to a constant value. As a result, the integration time of the integrating capacitor C4 is also reduced, so that the integrated value is also reduced and controlled to an appropriate value. Even when the integration capacitor C4 increases and when the resistance value of the resistor R4 fluctuates, the integration value is controlled appropriately in the same manner.

  As described above, according to the power factor correction circuit according to Embodiment 1 of the present invention, there is an advantage that the operation of obtaining the input current proportional to the input instantaneous voltage is hardly affected by variations in constants and fluctuations.

  The power factor correction circuit according to the second embodiment of the present invention winds the auxiliary winding Ns around the reactor L in the power factor correction circuit according to the first embodiment, and detects the input voltage using the forward voltage of the auxiliary winding Ns. To do.

  FIG. 4 is a diagram showing a configuration of a power factor correction circuit according to Embodiment 2 of the present invention. In the following, the same or corresponding parts as those in the configuration of the power factor correction circuit according to the first embodiment are denoted by the same reference numerals as those in the first embodiment, and description thereof is omitted or simplified.

  The reactor L1 includes a main winding Np and an auxiliary winding Ns wound around the main winding Np. The main winding Np corresponds to the reactor L of the power factor correction circuit according to the first embodiment. One end of the auxiliary winding Ns is connected to the ground line, and the other end is connected to the resistor R4. The input voltage detection unit 12 includes the auxiliary winding Ns of the reactor L1 and the resistor R4. The integration circuit 14 is configured by removing the transistor Q3 from the integration circuit of the power factor correction circuit according to the first embodiment.

  Next, the operation of the power factor correction circuit according to Embodiment 2 of the present invention configured as described above will be described. While the switching element Q1 is on, the input voltage is applied across the main winding Np of the reactor L1, and a voltage Ns / Np times the input voltage is generated in the auxiliary winding Ns. A current proportional to the voltage generated in the auxiliary winding Ns is obtained by the diode D3 and the resistor R4, and the integration capacitor C4 is charged by the current. Thereby, at the end of the ON period of the switching element Q1, the integrating capacitor C4 is charged with a voltage proportional to both the ON period and the input voltage.

  When the comparator circuit CP2 detects that the output voltage of the operational amplifier A2 in the reactor current detector 13 has reached the voltage of the integrating capacitor C4, the flip-flop FF1 is set and the switching element Q1 is turned on. The transistor Q4 is turned on and the integrating capacitor C4 is discharged. As a result, the current at the valley point of the reactor current can be proportional to both the ON period of the switching element Q1 and the input voltage, and the same effect as in the first embodiment can be obtained.

  Since the forward voltage of the auxiliary winding Ns is generated only during the on period of the switching element Q1, the integration of the forward voltage is performed only during the on period. Therefore, the circuit for controlling the integration period of the integration capacitor C4, that is, the transistor Q3 in the first embodiment is not necessary, and the configuration of the integration circuit 14 can be simplified.

  The power factor correction circuit according to the third embodiment of the present invention is the power factor correction circuit according to the first embodiment, wherein the output of the integration circuit 14 when the switching element Q1 is turned off is held by the sample and hold circuit. 14, the output of the input voltage detector 12 is integrated for one switching period.

  FIG. 5 is a diagram showing a configuration of a power factor correction circuit according to Embodiment 3 of the present invention. In the following, the same or corresponding parts as those in the configuration of the power factor correction circuit according to the first embodiment are denoted by the same reference numerals as those in the first embodiment, and description thereof is omitted or simplified.

  In the power factor correction circuit according to the third embodiment, a sample and hold (S & H) circuit 16 is added between the integration circuit 14 of the power factor correction circuit according to the first embodiment and the non-inverting terminal (+) of the comparison circuit CP2. Has been configured.

  When the output of the flip-flop FF1 changes to L level, in other words, when the output of the comparator CP1 of the on-period control unit 11 becomes H level, the sample and hold circuit 16 integrates in the integration circuit 14. While holding the voltage of the capacitor C4, it is cleared when the output of the comparison circuit CP2 becomes H level. The voltage held in the sample and hold circuit 16 is sent to the non-inverting input terminal (+) of the comparison circuit CP2. Further, the integration circuit 14 is configured by removing the transistor Q3 from the integration circuit of the power factor correction circuit according to the first embodiment.

  Next, the operation of the power factor correction circuit according to Embodiment 3 of the present invention configured as described above will be described with reference to the timing chart shown in FIG.

  Now, as shown in FIG. 6C, when the output of the comparison circuit CP2 becomes H level at time t1, the transistor Q4 of the integration circuit 14 is turned on, and the integration capacitor C4 is discharged, and FIG. 6 (e2) As shown, the voltage of the integrating capacitor C4 becomes zero. That is, the integration circuit 14 is initialized.

  When the output of the comparison circuit CP2 becomes H level, the output of the sample and hold circuit 16 becomes zero, so that the output of the comparison circuit CP2 becomes L level and the transistor Q4 is turned off. Thereby, as shown in FIG. 6 (e2), charging of the integrating capacitor C4 is started with a current proportional to the input voltage through the resistor R4 and the diode D3.

  Further, when the output of the comparison circuit CP2 becomes H level, the flip-flop FF1 is set. As shown in FIG. 6B, the output of the flip-flop FF1 is applied to the gate of the switching element Q1 via the switching element driving circuit 15, and the switching element Q1 is turned on. Thereby, as shown to Fig.6 (a), a reactor current begins to increase.

  When the flip-flop FF1 is set, the transistor Q2 of the on period control unit 11 is turned off, and the error voltage output from the error amplification unit 10 is converted into a current by the VI converter 11a and supplied to the integration capacitor C3. The As a result, charging of the integrating capacitor C3 is started, and the voltage of the integrating capacitor C3 starts to rise as shown in FIG. 6 (g).

  In this state, as shown in FIG. 6F, when the voltage of the integrating capacitor C3 reaches the voltage Von at time t2, the output of the comparator CP1 of the on period control unit 11 becomes H level, and the flip-flop FF1 is reset. Then, as shown in FIG. 6B, the output of the flip-flop FF1 is applied to the gate of the switching element Q1 via the switching element driving circuit 15, and the switching element Q1 is turned off. As a result, the ON period of the switching element Q1 ends, and the reactor current starts to decrease as shown in FIG.

  Further, when the output of the comparator CP1 becomes H level, the voltage of the integrating capacitor C4 of the integrating circuit 14 is held in the sample and hold circuit 16 as shown in FIG. 6 (e1). That is, the output voltage of the sample and hold circuit 16 remains the voltage at the time when the switching element Q1 is turned off. On the other hand, the charging to the integrating capacitor C4 is continuously performed as shown in FIG. 6 (e2).

  Further, when the flip-flop FF1 is reset, the transistor Q2 is turned on, the integration capacitor C3 of the on period control unit 11 is discharged, and the voltage of the integration capacitor C3 becomes zero as shown in FIG. 6 (g). It is initialized.

  When the switching element Q1 is turned off, the current flowing through the reactor L decreases, the voltage drop of the current detection resistor R7 decreases, and the output voltage of the reactor current detection unit 13 also decreases as shown in FIG. 6 (d). When the output voltage of the reactor current detection unit 13 reaches the voltage across the integration capacitor C4 at time t3, the output of the comparison circuit CP2 becomes H level, the flip-flop FF1 is set, and the switching element Q1 is turned on again. Switching is continued by repeating the above operation.

  As described above, the output voltage of the sample and hold circuit 16 and the output voltage of the reactor current detection unit 13 are compared, and when the output voltage of the sample and hold circuit 16 reaches the output voltage of the reactor current detection unit 13 Since the flip-flop FF1 is set and the switching element Q1 is turned on, the current at the valley point of the reactor current can be proportional to both the ON period of the switching element Q1 and the input voltage. Therefore, the same effects as those of the power factor correction circuits according to the first and second embodiments described above can be obtained.

  The power factor correction circuit according to the third embodiment of the present invention is obtained by adding overcurrent protection means for the switching element Q1 to the power factor correction circuit according to the first embodiment.

  FIG. 7 is a diagram illustrating a configuration of a power factor correction circuit according to Embodiment 4 of the present invention. In the following, the same or corresponding parts as those in the configuration of the power factor correction circuit according to the first embodiment are denoted by the same reference numerals as those in the first embodiment, and description thereof is omitted or simplified.

  The power factor correction circuit according to the fourth embodiment is configured by adding a second comparison circuit CP3, a voltage source for generating a voltage Voi, and an OR gate U1 to the power factor correction circuit according to the first embodiment. The voltage Voi is an upper limit value of the voltage output from the integrating circuit 14.

  The non-inverting terminal (+) of the second comparison circuit CP3 is connected to the output (integrating capacitor C4) of the integrating circuit 14, and the voltage Voi is applied to the inverting terminal (−). The output of the second comparison circuit CP3 is connected to the input terminal of the OR gate U1, and the other input terminal of the OR gate U1 is connected to the output terminal of the comparator CP1 of the on period control unit 11. The output terminal of the OR gate U1 is connected to the reset input terminal (R) of the flip-flop FF1.

  The second comparison circuit CP3 compares the output of the integration circuit 14 with the voltage Voi. When the output of the integration circuit 14 exceeds the voltage Voi, that is, the upper limit value, the second comparison circuit CP3 becomes H level and is flip-flopped via the OR gate U1. It is supplied to the reset input terminal (R) of FF1. As a result, the flip-flop FF1 is reset.

  Next, the operation of the power factor correction circuit according to Embodiment 3 of the present invention configured as described above will be described with reference to the timing chart shown in FIG. Since the basic operation is the same as the operation of the power factor correction circuit according to the first embodiment, only the characteristic part of the fourth embodiment will be described below.

  As the load current increases, the ON period of the switching element Q1 increases due to the action of the error amplifying unit 10 and the ON period control unit 11, and as shown at time t6 in FIG. 8B and FIG. When the output of the integration circuit 14 reaches Voi before the period ends, the output of the second comparison circuit CP3 becomes H level as shown in FIG. 8 (h). As a result, the flip-flop FF1 is reset. As a result, the switching element Q1 is turned off, the integration of the integration circuit 14 is stopped, and the voltage of the integration capacitor C4 does not increase.

  While the switching element Q1 is turned off, as shown in FIG. 8D, when the output of the reactor current detection unit 13 drops to the voltage of the integration capacitor C4, the comparison circuit CP2 generates an output and the integration capacitor C4. , The flip-flop FF1 is set, and the switching element Q1 is turned on again.

  The time for the voltage of the integrating capacitor C4 to reach Voi is shortened in inverse proportion to the input voltage. At the same time, the ON period of the switching element Q1 is also shortened in inverse proportion to the input voltage. Therefore, it is limited to a constant value, and the current of the switching element Q1 can be suppressed.

  FIG. 9 shows a case where a method of detecting the upper limit of the reactor current and turning off the switching element Q3, which is a generally performed overcurrent protection method, is applied to the power factor correction circuit according to the first embodiment shown in FIG. It is a figure which shows the timing chart which shows operation | movement.

  If the initial value of the reactor current at the moment when the switching element Q1 is turned on at time t1 is high, the reactor current quickly reaches the upper limit as shown in FIG. As shown, the ON period (from time t1 to time t2) is shortened. When the ON period is shortened, the charging period of the integrating capacitor C4 is also shortened, and as shown in FIG. 9E, the charging voltage of the integrating capacitor C4 is lowered. Therefore, the initial value of the reactor current in the next switching cycle (time t3). Becomes lower.

  When the initial value of the reactor current is lowered, it takes time to reach the upper limit of the reactor current, so that the ON period of the switching element Q1 (from time t3 to time t4) becomes longer, and at the same time, the charging period of the integrating capacitor C4 becomes longer. As a result, the voltage of the integrating capacitor C4 increases. As a result, the initial value of the reactor current in the next switching period is increased. By repeating the above operation, in the overcurrent protection method that directly limits the upper limit of the reactor current, in the case of the power factor correction circuit according to the first embodiment, the reactor current may be unstable.

  On the other hand, according to the power factor correction circuit according to the fourth embodiment, since the charging voltage of the integrating capacitor C4 is limited to a constant value, the initial value of the reactor current in the next switching cycle is the operation of the previous switching cycle. Stable overcurrent protection operation can be realized without depending on

  As described above, according to the power factor correction circuits according to the first to fourth embodiments of the present invention, the circuit configuration is simpler than the control circuit of the conventional general reactor current continuous mode power factor correction circuit. It is possible to control the reactor current continuous mode.

  In addition, the operation that makes the input current proportional to the input instantaneous voltage is not easily affected by variations or fluctuations in the constant, and adjustment of the constant for the purpose of making the input current proportional to the input instantaneous voltage is basically unnecessary. . Further, it does not include an analog multiplier circuit with a limited operating range, and has an advantage that it is easy to control a wide input voltage fluctuation range and a load fluctuation range as compared with the prior art.

  The present invention is applicable to an AC-DC conversion type power supply circuit.

It is a figure which shows the structure of the power factor improvement circuit which concerns on Example 1 of this invention. It is a timing chart which shows operation | movement of the power factor improvement circuit which concerns on Example 1 of this invention. It is a timing chart which shows the operation | movement of the whole power factor improvement circuit which concerns on Example 1 of this invention. It is a figure which shows the structure of the power factor improvement circuit which concerns on Example 2 of this invention. It is a figure which shows the structure of the power factor improvement circuit which concerns on Example 3 of this invention. It is a timing chart which shows operation | movement of the power factor improvement circuit which concerns on Example 3 of this invention. It is a figure which shows the structure of the power factor improvement circuit which concerns on Example 4 of this invention. It is a timing chart which shows operation | movement of the power factor improvement circuit which concerns on Example 4 of this invention. 3 is a timing chart illustrating an operation when a generally performed overcurrent protection method is applied to the power factor correction circuit according to the first embodiment. It is a figure which shows an example of the conventional boost chopper type power factor improvement circuit.

Explanation of symbols

Vac AC power supply D1 Rectifier 10 Error amplifier 11 On period controller 11a VI converter 12 Input voltage detector 13 Reactor current detector 14 Integral circuit 15 Switching element drive circuit 16 Sample and hold circuit Q1 Switching elements Q2, Q3, Q4 Transistors D2 Backflow prevention diode D3 Diode L, L1 Reactor Np Main winding Ns Auxiliary winding R1, R2 Output split resistors R4, R5, R6 Resistor R7 Current detection resistor C1 Output smoothing capacitor C2 Capacitor C3, C4 Integration capacitor A1 Error amplifier A2 Operation Amplifier CP1 Comparator CP2 Comparison circuit CP3 Second comparison circuit FF1 Flip-flop U1 OR gate LD Load

Claims (5)

A rectifier that rectifies an AC input voltage and outputs the input voltage;
A first series circuit connected between the output ends of the rectifier, in which a reactor and a switching element are connected in series;
A second series circuit connected between both ends of the switching element, wherein a backflow prevention diode and an output smoothing capacitor are connected in series;
In a power factor improvement circuit comprising a control circuit for controlling on / off of the switching element, and obtaining a DC output voltage from both ends of the output smoothing capacitor,
The control circuit includes:
When the switching element is on, the on-period of the switching element is determined based on the output voltage. When the switching element is off, the reactor current flowing through the reactor is based on the input voltage output from the rectifier. A power factor correction circuit characterized in that an off period is determined by detecting that a predetermined value has been reached. The control circuit includes:
An error amplifier for amplifying an error voltage between the output voltage and the first reference voltage;
An ON period in which the output of the error amplifier is integrated when the switching element is ON, and the ON period of the switching element is ended and the integration result is initialized when the integration result becomes larger than the second reference voltage. A control unit;
An input voltage detector for detecting an input voltage output from the rectifier;
An integration circuit that integrates the output of the input voltage detection unit in the on period of the switching element, and holds an integration result in the off period of the switching element;
A reactor current detector that detects a reactor current flowing through the reactor; and
When comparing the output of the reactor current detection unit and the output of the integration circuit, and determining that the output of the reactor current detection unit is smaller than the output of the integration circuit, and turning on the switching element, and A comparison circuit for initializing an integration result in the integration circuit;
The power factor correction circuit according to claim 1, further comprising: The reactor includes an auxiliary winding,
3. The power factor correction circuit according to claim 2, wherein the input voltage detector detects a voltage generated in the auxiliary winding when the switching element is on. A voltage holding circuit for holding the output of the integrating circuit when the switching element is turned off;
The integration circuit integrates the output of the input voltage detection unit,
The comparison circuit compares the output of the reactor current detection unit with the output of the voltage holding circuit when the switching element is off, and the output of the reactor current detection unit is smaller than the output of the voltage holding circuit. 3. The power factor correction circuit according to claim 2, wherein when the determination is made, the switching element is turned on, and the integration result in the integration circuit and the voltage held in the voltage holding circuit are initialized. . A second comparison circuit for comparing the output of the integration circuit with a predetermined voltage;
3. The power factor correction circuit according to claim 2, wherein the switching element is turned off when the second comparison circuit determines that the output of the integration circuit exceeds a predetermined voltage.

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