TWI282607B - Semiconductor package and molding device thereof - Google Patents

Semiconductor package and molding device thereof Download PDF

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Publication number
TWI282607B
TWI282607B TW091135604A TW91135604A TWI282607B TW I282607 B TWI282607 B TW I282607B TW 091135604 A TW091135604 A TW 091135604A TW 91135604 A TW91135604 A TW 91135604A TW I282607 B TWI282607 B TW I282607B
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TW
Taiwan
Prior art keywords
semiconductor package
substrate
package structure
sealing device
fixture body
Prior art date
Application number
TW091135604A
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Chinese (zh)
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TW200410383A (en
Inventor
Wei-Chun Kung
Liang-Cheng Chang
Yu-Fang Tsai
Original Assignee
Advanced Semiconductor Eng
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Priority to TW091135604A priority Critical patent/TWI282607B/en
Publication of TW200410383A publication Critical patent/TW200410383A/en
Application granted granted Critical
Publication of TWI282607B publication Critical patent/TWI282607B/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape

Landscapes

  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

A semiconductor package includes a substrate, a chip, and a molding compound. In this case, the chip is mounted on and electrically connected to the substrate. The molding compound covers the chip and a surface of the substrate. The molding compound includes a plurality of bulges. Furthermore, this invention also discloses a molding device for packaging the semiconductor package. The molding device includes a first molding body and a second molding body. The first molding body has a supporting portion. The second molding body is provided over the first molding body, so that the first and second bodies construct a space for the semiconductor package. A surface of the second molding body, which opposites to the first molding body, has a plurality of caves.

Description

1282607 五、發明說明（l) (一）、【發明所屬之技術領域】 本發明係關於一種半導體封裝姓 別關於-種呈辦強4献„ = 裝、、、ϋ構及其封膠裝置，特 其封膠裝置。 牛導體封裝結構及 (二）、【先前技術】 身又而σ在半導體封裝結構的使用過鞋十 用時間的增長半導體封裝結構中的晶片會二隨著使1282607 V. INSTRUCTION DESCRIPTION (1) (I) Technical Field of the Invention The present invention relates to a semiconductor package name, a type of device, a device, a device, and a sealing device. Special sealing device. Cattle conductor packaging structure and (b), [previous technology] body and σ in the semiconductor package structure used in the use of shoes for a ten-time increase in the semiconductor package structure will be

J;，若所產生的熱量持續累積於晶二J::的 去日ί ’常會導致半導體封裝結構無法發揮正；地散 短其使用壽命，此為半導體封裝結構使用時；見：J 構中:==胃，熟知該項技術者係於半導體封裝結 請參照圖1所示，習知的半導體封裝結構1包括— 11、一晶片12、一封膠體13、複數條導電線14以及埶 片（heat Pad)15。其中，晶片12設置於基板u上；封膠體 13係形成於基板上並包覆晶片12、該等導電線"及散埶片 15的底部和側面；該等導電線14接合基板丨丨與晶片12了而 散熱片1 5係設置於封膠體1 3上。 此外，雖然在半導體封裝結構丨所設置之散熱片i 5發 揮了 一定程度的散熱功能，但是其效能仍有改善空間，所 以為了加強散熱片1 5的散熱效能，熟知該項技術者係以具 有複數個散熱鰭部151的散熱片15,取代散熱片15，如圖2 第6頁 1282607 五、發明說明（2) 所示，由於在習知的半導體封裝結構2中，散熱片15，上具 有複數個散熱縛部1 51 ’其增加了散熱片1 5，的表面積，因 此能夠增加散熱片1 5’的散熱效能。 然而，雖然可以利用散熱鰭部1 5 1來增加散熱表面 積，以達到更佳的散熱效能，但是，此方法必須事先將散 熱片1 5加工以形成散熱鰭部1 5 1，所以會增加產品製作上 加工的步驟與成本。 因此，如何提供一種能夠有效地將晶片所產生之熱量 導出並節省其製作成本的半導體封裝結構，正是當前半導 體封裝技術的重要課題之一。 、三）、【發明内容】 針對上述問題，本發明之目的為提供一種能夠有效地 將晶片所產生之熱量導出的半導體封裝結構及其封膠裝 另外本發明之另一目的為提供一種能夠節省製作成 本的半導體封裝結構及其封膠裝置。 為達上述目的，依本發明之半導體封裝結構包括一基 ==片以及—封膠體。在本發明中，日日日片電性連接地 體具有複數個突起（bulges)。 4 ,、中封膠 置，ί:括本’Γ月亦提供一種半導體封裝結構用之封膠裝 ㊁，=包括一第一治具本體及一第二治具本體。在本發明 ，口具本體具有-承載部；第二治具本體係位於第 1282607J;, if the generated heat continues to accumulate in the crystal two J:: go to the day ί ' often results in the semiconductor package structure can not play positive; ground dissipation its service life, this is the use of semiconductor package structure; see: J structure :== Stomach, the person skilled in the art is attached to the semiconductor package. Referring to FIG. 1 , the conventional semiconductor package structure 1 includes - 11, a wafer 12, a gel 13, a plurality of conductive lines 14 and a cymbal. (heat Pad) 15. The wafer 12 is disposed on the substrate u. The encapsulant 13 is formed on the substrate and covers the wafer 12, the conductive lines, and the bottom and sides of the diffusion sheet 15; the conductive lines 14 are bonded to the substrate and The wafer 12 is disposed and the heat sink 15 is disposed on the encapsulant 13. In addition, although the heat sink i 5 provided in the semiconductor package structure exerts a certain degree of heat dissipation function, there is still room for improvement in performance. Therefore, in order to enhance the heat dissipation performance of the heat sink 15, the person skilled in the art has The fins 15 of the plurality of heat dissipating fins 151 are replaced by the fins 15, as shown in FIG. 2, page 6, 1282607, and the invention description (2), since in the conventional semiconductor package structure 2, the fins 15 have A plurality of heat dissipating portions 1 51 ' increase the surface area of the fins 15 and thus increase the heat dissipation performance of the fins 15 5 '. However, although the heat dissipating fins 151 can be utilized to increase the heat dissipating surface area for better heat dissipation performance, the method must first process the fins 15 to form the heat dissipating fins 153, thus increasing product manufacturing. The steps and costs of processing. Therefore, how to provide a semiconductor package structure that can effectively derive the heat generated by the wafer and save its manufacturing cost is one of the important topics of the current semiconductor package technology. SUMMARY OF THE INVENTION In view of the above problems, an object of the present invention is to provide a semiconductor package structure capable of efficiently deriving heat generated by a wafer and a seal assembly thereof. Another object of the present invention is to provide an energy saving. The cost of the semiconductor package structure and its sealing device. To achieve the above object, a semiconductor package structure according to the present invention includes a base == sheet and a sealant. In the present invention, the day-to-day electric connection body has a plurality of bulges. 4, the middle seal, ί: Included in this month, also provides a sealing package for the semiconductor package structure 2, including a first fixture body and a second fixture body. In the present invention, the mouth body has a bearing portion; the second jig system is located at 1282607

五、發明說明（3) 一治具本體上#’以便與第-治具本體形成—容置半導體 封裝結構之空間，而且第二治具太駚命够 冉 ^ 口丹本體與第一治具本體相對 之一側面形成有複數個凹部。 综上所述，由於本發明係形成具有複數個突起的封膠 體，以便增加封膠體的表面積，所以依本發明之半導體封 裝結構能夠在不增加製作加工的步驟與成本的前提下，達 到更佳的散熱效能。 (四）、【實施方式】 以下將參照相關圖式，說明依本發明較佳實施例之半❶ 導體封裝結構，其中相同的元件將以相同的參照符號加以 說明。 請參照圖3所示，依本發明之半導體封裝結構3包括一 基板31、一晶片32、一封膠體33以及複數條導電線34。 在本貫施例中’基板3 1可以是任意一種能夠用來承載 晶片的基板’例如是BT基板、RF-4基板、或是導線架。此 外’基板3 1背向晶片3 2的一側面上更形成有複數個錫球 (solder bal 1 ) 311，其係用以電性連接基板31與外界電 路，以便溝通晶片3 2與外界電路。 晶片3 2設置於基板3 1上。在本實施例中，晶片3 2係利 用習知的黏晶製程來黏置於基板3丨上。其中，晶片32係依 據需要而可以是透過導電膠或是非導電膠來黏置於基板31 該#導電線3 4接合基板3 1與晶片3 2。在本實施例中V. Description of the invention (3) The body of the fixture is formed on the body to form a space for the semiconductor package structure, and the second fixture is too long enough to be used. A plurality of recesses are formed on one side of the body. In summary, since the present invention forms a sealant having a plurality of protrusions in order to increase the surface area of the sealant, the semiconductor package structure according to the present invention can be better without increasing the steps and costs of fabrication and processing. Cooling performance. (4) [Embodiment] Hereinafter, a semiconductor package structure according to a preferred embodiment of the present invention will be described with reference to the accompanying drawings, wherein the same elements will be described with the same reference numerals. Referring to FIG. 3, the semiconductor package structure 3 according to the present invention comprises a substrate 31, a wafer 32, a gel 33, and a plurality of conductive lines 34. In the present embodiment, the substrate 31 may be any substrate that can be used to carry a wafer, such as a BT substrate, an RF-4 substrate, or a lead frame. Further, a plurality of solder balls 1 311 are formed on one side of the substrate 31 facing away from the wafer 3 2 for electrically connecting the substrate 31 and the external circuit to communicate the wafer 32 and the external circuit. The wafer 3 2 is disposed on the substrate 31. In the present embodiment, the wafer 32 is adhered to the substrate 3 by a conventional die bonding process. The wafer 32 may be adhered to the substrate 31 through a conductive paste or a non-conductive paste as needed. The conductive wire 34 is bonded to the substrate 31 and the wafer 32. In this embodiment

12826071282607

方式來接合基板31之 該等導電線34係利用習知的打線接合 銲墊（pad )與晶片32之銲墊。 ° 片於基板31上，以包覆基板31表面、晶 片2及該專導電線34,而且封膠體^具有複數個 331。在本實施例中，由於封膠體 所以封膠體33的表面積能夠大幅地捭/、該等突起331， 體33係利用一特定之封=加此= = 33時，能夠直接形成該等突起此，在形成封膠體The conductive lines 34 that bond the substrate 31 in a manner are bonded to the pads of the wafer 32 using conventional bonding pads. The film is coated on the substrate 31 to cover the surface of the substrate 31, the wafer 2, and the specific conductive line 34, and the sealing body has a plurality of 331. In this embodiment, the surface area of the sealant 33 can be substantially 捭/, the protrusions 331 due to the sealant, and the body 33 can form the protrusions directly by using a specific seal = plus == 33. Forming a sealant

二外’請參照圖4所示’依本發明另一較佳實施例之 =導體封裝結構4包括-基板31、—晶片32、一封膠體 33、複數條導電線34以及一散熱片35。Referring to FIG. 4, a conductor package structure 4 includes a substrate 31, a wafer 32, a gel 33, a plurality of conductive wires 34, and a heat sink 35, in accordance with another preferred embodiment of the present invention.

在本實施例中，散熱片35係披覆於整個封膠體3 2。其中，散熱片35可以是於封膠之前先之 、疋的封膝裝置中，而且散熱片35的形狀係配合封膠裝置 之凹部而設計，亦即散熱片35乃是高低起伏的幾何形狀 ^如圖4所示），接著注入封膠物質以形成封膠體33，此 日守封膠體33會形成於基板31與散熱片35之間，因此形成如 圖4所示之半導體封裝結構4 ;另外，散熱片”亦可以是於 形成封膠體33之後才設置於封膠體33上。 ^ 此外，封膠體的形狀可以依據廠商需要而有所變化； σ月參fc、圖5所示，依本發明又一較佳實施例之半導體封裝 結構5包括一基板31、一晶片32、一封膠體33、複數條導 電線34以及一散熱片35，。在本實施例中，封膠體33具有In the present embodiment, the heat sink 35 is coated over the entire encapsulant 32. Wherein, the heat sink 35 may be in the knee sealing device before the sealing, and the shape of the heat sink 35 is designed to match the concave portion of the sealing device, that is, the heat sink 35 is a high and low undulating geometry^ As shown in FIG. 4, the encapsulant is then injected to form the encapsulant 33. The sealing compound 33 is formed between the substrate 31 and the heat sink 35, thereby forming the semiconductor package structure 4 as shown in FIG. The heat sink may be disposed on the sealant 33 after forming the sealant 33. ^ In addition, the shape of the sealant may vary according to the needs of the manufacturer; σ月参fc, as shown in Fig. 5, according to the present invention The semiconductor package structure 5 of another preferred embodiment comprises a substrate 31, a wafer 32, a glue 33, a plurality of conductive lines 34 and a heat sink 35. In the embodiment, the seal body 33 has

第9頁 1282607 五、發明說明（5) 複數個突起331以及一平坦部332，該等突起331係圍繞平 坦部3 3 2設置，而散熱片3 5 ’係形成於封膠體3 3的平坦部 332上。此時，散熱片35,上還可以依據製造廠商的需要而 刻上特定的圖案，如製造廠商的商標、或是產品型號等 (圖中未顯示）。需注意者，散熱片35，形成於封膠體” 上的方式係如前所述，故此不再闡述。 請參照圖6所示，依本發明較佳實施例之半導體封 結構用之封膠裝置6包括一第一治具本體61、及一第二治 具本體62。在本實施例中，第一治具本體具有一承載σ 611 ’·第二治具本體62與承載部611相對之一側面形 數個凹部621 ;而當第二治具本體62設置於第一治具本 η:第二治具本體62與第一治具本體61係形成-空 間63、，其係用以容置前述之半導體封裝結構。 F二使^發明更容易理解’以下以形成前述之半導體封 ^了構3為例，說明利用封膠裝置6來進行封膠製程的過 某』ί 示’ #先將形成有晶片32及導電線34的 :产呈本體62 =治具本體61之承載部6U上，接著將第 治具本體61蓋合以構成空間63，此時 基板31係谷置於空間6 3中。 此$ 德，圖几所示，將封膠體33注入空間63中。之 另外，在利用封膠裝置6來進行前述之半導體封裝吐 1282607 五、發明說明（6) 構4之封膠製程的過程中，首先，如圖8 A所示，將形成有 晶片32及導電線34的基板31置放於第一治具本體6丨之承載 部6 11上；其次，將散熱片3 5設置於第二治具本體6 2形成 有複數個凹部621之一側面上；接著，將第二治具本體62 與第一治具本體61蓋合以構成空間63，此時基板31係 於空間6 3中。 y然後，如圖8B所示，將封膠體33注入空間63中。之 ί mf:封膠體33的固化、並進行切割，如此便能夠製得 如圖4所示的半導體封裝結構4。 μ φ、二i所述，由於在本發明較佳實施例之半導體封裝& 構中的封膠體係具有複數 體上設置散執片目的。另夕卜’於封膠 熱功能。 又计更加強了整個半導體封裝結構的散 以上所述僅為舉例性，而非為 本發明之精神與範_，而對=性者。任何未脫離 應包含於後附之申請專利範圍中:之4效修改或變更，均Page 9 1282607 V. DESCRIPTION OF THE INVENTION (5) A plurality of protrusions 331 and a flat portion 332 which are disposed around the flat portion 3 3 2 and the heat sink 3 5 ' is formed on the flat portion of the seal body 33 332. At this time, the heat sink 35 can also be engraved with a specific pattern according to the needs of the manufacturer, such as the manufacturer's trademark, or the product model (not shown). It should be noted that the way in which the heat sink 35 is formed on the encapsulant is as described above, and therefore will not be described. Referring to FIG. 6 , the sealing device for the semiconductor sealing structure according to the preferred embodiment of the present invention. 6 includes a first jig body 61 and a second jig body 62. In this embodiment, the first jig body has a bearing σ 611 '· the second jig body 62 is opposite to the carrying portion 611 The second fixture body 62 is disposed on the first fixture body η: the second fixture body 62 and the first fixture body 61 form a space 63, which is used for accommodating The above-mentioned semiconductor package structure. F2 makes the invention easier to understand. 'The following is an example of forming the semiconductor package structure 3 described above, and illustrates that the sealing device 6 is used to perform the sealing process. The wafer 32 and the conductive wire 34 are formed: the main body 62 is formed on the bearing portion 6U of the jig body 61, and then the jig main body 61 is covered to form a space 63. At this time, the substrate 31 is placed in the space 63. This $de, shown in the figure, injects the encapsulant 33 into the space 63. In addition, in the use of the seal In the process of performing the sealing process of the semiconductor package spout 1282607, and the invention (6) structure 4, first, as shown in FIG. 8A, the substrate 31 on which the wafer 32 and the conductive line 34 are formed is placed. On the carrying portion 6 11 of the first jig body 6丨; secondly, the heat sink 35 is disposed on the side surface of the second jig body 62 formed on one of the plurality of concave portions 621; then, the second jig body is 62 is capped with the first jig body 61 to form a space 63, at which time the substrate 31 is attached to the space 63. y Then, as shown in Fig. 8B, the encapsulant 33 is injected into the space 63. ί mf: sealant The curing of 33 and cutting is performed, so that the semiconductor package structure 4 as shown in Fig. 4 can be obtained. As described in μ φ, ii, the sealing material in the semiconductor package & structure of the preferred embodiment of the present invention The system has the purpose of setting up a loose film on a complex body. In addition, it is used to encapsulate the thermal function. It is also to strengthen the dispersion of the entire semiconductor package structure. The above is only an example, not the spirit and scope of the present invention. And for the sexes. Any application that has not been removed should be included in the attached patent application. In: 4 effect of modifications or changes are

第11頁 1282607 圖式簡單說明 (五）、【圖式簡單說明】 圖1為一示音IS! θ _ 圖。 思圖，顯示習知的半導體封裝結構之示意 圖2為一示奋m e +立® ^ ^愚圖，顯示另一習知的半導體封裝結構之 不思圖’其一包括有散熱縛部。 封裝Γ構為的一示示意意圖'，顯示依本發明較佳實施例之半導體 圖4肩；一*土 導體封裝結構的$干圖立=示依本發明另—較佳實施例之半 面。 思圖’其中散熱片係披覆於封膠體的表 圖5為一示音闾 導體封裝結構的〜、-立，不依本發明另一較佳實施例之半 部表面上。 不忍圖’其中散熱片係披覆於封膠體的局 圖6為一示咅圖 封裝結構用之/颂不依本發明較佳實施例之半導體 圖職為二裝/的局部示意圖。 進行封膠製程以电Γ〜圖，顯不利用如圖6所示之封裝裝置來 圖。 传如圖3所示之半導體封裝結構的示意 圖8A〜8B為示咅m _ 進行封膠製程以制1回，顯不利用如圖6所示之封裝裝置來 圖。 表得如圖4所示之半導體封裝結構的示意 元件符號說明： [ 半導體封裳結構Page 11 1282607 Simple description of the diagram (5), [Simple description of the diagram] Figure 1 shows a sound IS! θ _ diagram. FIG. 2 is a schematic diagram showing a conventional semiconductor package structure. FIG. 2 is a diagram showing another conventional semiconductor package structure, which includes a heat-dissipating portion. The package is shown schematically as a schematic view showing a semiconductor in accordance with a preferred embodiment of the present invention. FIG. 4 is a shoulder view of a preferred embodiment of the present invention. Figure 5 shows a heat sink applied to the sealant. Figure 5 is a schematic representation of a conductor package structure on a half surface of a preferred embodiment of the present invention. The figure in which the heat sink is applied to the sealant is shown in Fig. 6. Fig. 6 is a partial schematic view of the semiconductor package according to the preferred embodiment of the present invention. The encapsulation process is performed by electro-mechanical-to-figure, and the package device shown in Fig. 6 is not used. FIG. 8A to FIG. 8B show the semiconductor package structure shown in FIG. 3, and the encapsulation process is performed for one time, and the package device shown in FIG. 6 is not used. The schematic representation of the semiconductor package structure shown in Figure 4 is a symbolic description of the device: [Semiconductor Sealing Structure

1282607 圖式簡單說明 11 基板 12 晶片 13 封膠體 14 導電線 15 散熱片 15， 散熱片 151 散熱鰭部 2 半導體封裝結構 3 半導體封裝結構 31 基板 311 錫球 32 晶片 33 封膠體 331 突起 332 平坦部 34 導電線 35 散熱片 35， 散熱片 4 半導體封裝結構 5 半導體封裝結構 6 封膠裝置 61 第一治具本體 611 承載部 62 第二治具本體1282607 Schematic description 11 substrate 12 wafer 13 encapsulant 14 conductive wire 15 heat sink 15, heat sink 151 heat sink fin 2 semiconductor package structure 3 semiconductor package structure 31 substrate 311 solder ball 32 wafer 33 sealant 331 protrusion 332 flat portion 34 Conductor 35 Heat sink 35, heat sink 4 Semiconductor package structure 5 Semiconductor package structure 6 Sealing device 61 First fixture body 611 Bearing portion 62 Second fixture body

1282607 圖式簡單說明 621 凹部 63 空間 第14頁1282607 Schematic description of the figure 621 recess 63 space page 14

Claims (1)

1282607 、申請專利範圍 〖、一種半導體封裝結構，包含： 一基板； 曰曰片’其係電性連接地設置於該基板上；以及 一封膠體’其係包覆該基板表面及該晶片，該封膠體具有 複數個突起（bulges)。 、如申請專利範圍第1項所述之半導體封裝結構，更包 含： 複數條導電線，其係接合該基板與該晶片。 、如申請專利範圍第1項所述之半導體封裝結構，更包 含： 複數個錫球（solder bai 1 )，其係設置於該基板之一側 面上。 、如申請專利範圍第1項所述之半導體封裝結構，其中該 基板為一 B T基板。 〕、如申請專利範圍第1項所述之半導體封裝結構，其中唁 基板為一RF-4基板。 人 導體封裝結構，其中該 〕、如申請專利範圍第1項所述之半 基板為一導線架。1282607, the scope of the patent application 〖, a semiconductor package structure, comprising: a substrate; the cymbal sheet is electrically connected to the substrate; and a gel body that covers the surface of the substrate and the wafer, The sealant has a plurality of bulges. The semiconductor package structure of claim 1, further comprising: a plurality of conductive lines that bond the substrate to the wafer. The semiconductor package structure of claim 1, further comprising: a plurality of solder balls (solder bai 1 ) disposed on one side of the substrate. The semiconductor package structure of claim 1, wherein the substrate is a B T substrate. The semiconductor package structure of claim 1, wherein the 基板 substrate is an RF-4 substrate. The human conductor package structure, wherein the half substrate as described in claim 1 is a lead frame. 第15頁 !282607 六、申請專利範圍 7、如申請專利範圍第1項所述之半導體封裝結構，更包 含： 上 熱片，其係設置於該封膠鱧 t、如申請專利範圍第7項所述之半導體封裝結構，其中該 政熱片係位於該等突起上。 9、 如申請專利範圍第7項所述之半導體封裝結構，其中該 封膠體更具有一平坦部，該等突起係圍繞該平坦部設置， 而該散熱片係設置於該平坦部上。 10、 一種半導體封裝結構用之封膠裝置，包含： 一第一治具本體，其具有一承載部；以及 一第二治具本體，其係位於該第一治具本體上方，且該第 =治具本體與該承載部相對之一側面形成有複數個凹 邛該第一治具本體與該第〆治具本體係形成一容置該 半導體封裝結構之空間。 專利範圍第1 〇項所述之半導體封裝結構用之封 ，裝置’“該承載部係用以承載一具有一晶片之基板。 膠裝置1中該基板之-側面上更設置有複；;: 12、如申請專利範圍第u項所 膠锭罢，朴丄…u丨一、 &lt; 午導體封裝結構用之封 錫球Page 15 282607 VI. Patent Application No. 7. The semiconductor package structure as described in claim 1 of the patent application, further comprising: an upper heat sheet which is disposed in the sealant 、t, as in the scope of claim 7 The semiconductor package structure, wherein the political heat film is located on the protrusions. 9. The semiconductor package structure of claim 7, wherein the encapsulant further has a flat portion, the protrusions are disposed around the flat portion, and the heat sink is disposed on the flat portion. 10 . A sealing device for a semiconductor package structure, comprising: a first fixture body having a bearing portion; and a second fixture body located above the first fixture body, and the first A plurality of recesses are formed on a side of the fixture body opposite to the bearing portion. The first fixture body and the second fixture body form a space for accommodating the semiconductor package structure. The device for mounting a semiconductor package structure according to the first aspect of the invention, wherein the device is configured to carry a substrate having a wafer. The glue device 1 is further provided with a side surface of the substrate; 12. If the rubber ingot is applied in the scope of the patent application, the 丄 丄 丄 丄 & & & & & & 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 第16胃 1282607 六、申請專利範圍 、如申請專利範圍第u項所述之半導體封裝結構用之封 膠裝置，其中該基板為一BT基板。 ^、如申請專利範圍第丨丨項所述之半導體封裝結構用之封 膠裝置’其中該基板為一 RJ? - 4基板。 1 5、如申請專利範圍第丨丨項所述之半導體封裝結構用之封 膠裝置，其中該基板為一導線架。The invention relates to a sealing device for a semiconductor package structure according to the invention of claim 5, wherein the substrate is a BT substrate. The sealing device for a semiconductor package structure as described in claim </ RTI> wherein the substrate is an RJ?-4 substrate. The sealing device for a semiconductor package structure according to the invention of claim 2, wherein the substrate is a lead frame. 1 6、如申請專利範圍第丨丨項所述之半導體封裝結構用之封 膠裝置，其中一封膠體係形成於該基板與該第二治具本體 形成有該等凹部之該侧面，該封膠體係包覆該基板表面及 該晶片’且該封膠體具有複數個分別容置於該等凹部之突 起。 1 7、如申請專利範圍第1 6項所述之半導體封裝結構用之封 膠裝置，其中該封膠體與該第二治具本體形成有該等凹部 之該側面間係設置有一散熱片。 1 8、如申請專利範圍第1 7項所述之半導體封裝結構用之封 膠裝置，其中該散熱片係位於該等突起上。 1 9、如申請專利範圍第1 7項所述之半導體封裝結構用之封 膠裝置，其中該封膠體更具有/平坦部’该等突起係圍繞The sealing device for a semiconductor package structure according to the above aspect of the invention, wherein an adhesive system is formed on the side surface of the substrate and the second fixture body having the concave portions, the seal The glue system covers the surface of the substrate and the wafer 'and the encapsulant has a plurality of protrusions respectively received in the recesses. The sealing device for a semiconductor package structure according to claim 16, wherein the sealing body and the side of the second fixture body having the recesses are provided with a heat dissipating fin. The sealing device for a semiconductor package structure according to claim 17, wherein the heat sink is located on the protrusions. The sealing device for a semiconductor package structure according to claim 17, wherein the encapsulant further has a flat portion 第17頁 1282607 六、申請專利範圍 該平坦部設置，而該散熱片係設置於該平坦部上。 ί ί 11 第18頁Page 17 1282607 VI. Patent Application Range The flat portion is disposed, and the heat sink is disposed on the flat portion. ί ί 11 page 18
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