TWI282606B - Method for packaging optical chip and packaging structure thereof - Google Patents
Method for packaging optical chip and packaging structure thereof Download PDFInfo
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- TWI282606B TWI282606B TW094142663A TW94142663A TWI282606B TW I282606 B TWI282606 B TW I282606B TW 094142663 A TW094142663 A TW 094142663A TW 94142663 A TW94142663 A TW 94142663A TW I282606 B TWI282606 B TW I282606B
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- 230000003287 optical effect Effects 0.000 title claims abstract description 42
- 238000000034 method Methods 0.000 title claims abstract description 22
- 238000004806 packaging method and process Methods 0.000 title claims abstract description 16
- 239000000758 substrate Substances 0.000 claims abstract description 91
- 125000006850 spacer group Chemical group 0.000 claims abstract description 56
- 239000011521 glass Substances 0.000 claims abstract description 44
- 229920002120 photoresistant polymer Polymers 0.000 claims description 4
- 238000005538 encapsulation Methods 0.000 claims 2
- 238000000059 patterning Methods 0.000 claims 1
- 238000003825 pressing Methods 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- 239000004973 liquid crystal related substance Substances 0.000 description 2
- PEDCQBHIVMGVHV-UHFFFAOYSA-N Glycerine Chemical compound OCC(O)CO PEDCQBHIVMGVHV-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 230000018109 developmental process Effects 0.000 description 1
- 230000012447 hatching Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000012858 packaging process Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
- B81C1/00015—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
- B81C1/00261—Processes for packaging MEMS devices
- B81C1/00333—Aspects relating to packaging of MEMS devices, not covered by groups B81C1/00269 - B81C1/00325
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C3/00—Assembling of devices or systems from individually processed components
- B81C3/002—Aligning microparts
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
- H01L23/10—Containers; Seals characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14618—Containers
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C2203/00—Forming microstructural systems
- B81C2203/01—Packaging MEMS
- B81C2203/0118—Bonding a wafer on the substrate, i.e. where the cap consists of another wafer
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C2203/00—Forming microstructural systems
- B81C2203/05—Aligning components to be assembled
- B81C2203/051—Active alignment, e.g. using internal or external actuators, magnets, sensors, marks or marks detectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0652—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next and on each other, i.e. mixed assemblies
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16195—Flat cap [not enclosing an internal cavity]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/166—Material
- H01L2924/16786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
- H01L2924/16788—Glasses, e.g. amorphous oxides, nitrides or fluorides
Description
1282606
三達編號TW2273PA 九、發明說明: 【發明所屬之技術領域】 本發明是有關於-種封裝方法及封裝結構,且特別是有關 於一種光學元件的封裝方法以及結構。 【先前技術】 投影機產業發展至今,技術從映像管(CRT)、非晶矽(a_si)、 多晶矽(Ρ-Si)至所謂的數位微鏡元件(Dighal Micr〇mim>r
Device,DMD)與 LC0S(Liquid Crystal 〇n smc〇n)反射式液晶投 影。以市場觀點來看,隨著投影機技術的進步,投影機產品因 為體積小、重量輕、攜帶方便,加上筆記型電腦性能不斷提升 與銷售量日漸擴增和普及’ it而也帶動多媒體簡報風行,使得 原本只是以辦公室自動化(0A)市場為主的投影機產品,未來除 了在消費性電子市場發展之外’亦將切入所謂的pc市場。投 影技術日新月$,在所有的光學元件中,以投影晶片為最關二 的零組件。 第1圖是投影晶片之封裝結構圖。請參照第丨圖,投与曰 片11必須係封裝於間隔才才12在基材10與玻璃基板 生的間隙中,則光線可穿透玻璃基板13進出投影晶片11,a 可達到保護投影晶片U的功效。在封裝時,先將投影曰= 設置於基板10上,在投影晶片n周圍設置間隔材12\曰9 玻璃基板13。一旦經過對位之後,即可壓合完成封裝。人 然而,基材1Θ、間隔材12與玻璃基板13三者無法 、, 位。在傳統封裝製程中,對位製程通常利用電荷耦合、元件行對 (Charge Coupled Device,CCD)。由於在投影晶片 u 之 中,基材10與玻璃基板13之間的間隙過大, 結構 5 电何耦合元件無 1282606
〜途編號TV/2273PA 對2:;:基:;卜。與—坡璃基板13上的對位點’造成無法精確 法控制,嚴重影響後續==:_製程亦無 【發明内容】 有鏗於此,本發明的目的就是在 方法及結構,可改盖彳L 喱九子兀件的封裝 發明係在門… 無法利用感光元件對位的問題。本 的圖宰。二:—Γΐ貫孔’並於玻璃基板與基材上形成對應 有的機台進行封裝。 有更机口用原 根據:發明的目的’提出一種光學元件之封 =小二基材’其表面設置複數個光學元件,該基材具 個開二X:至案:(b)提供;間隔材,該間隔材具有複數 作對/…/—貝孔,⑷利用該些第—對位圖案及該些貫孔 座,亥些開口對應於該些光學元件,並據以接合該基材 ^亥間隔材;(d)提供-玻璃基板,具有至少二第二對 =及⑷利㈣些第二對位圖案及該些貫孔作對位 接人 該間隔材與該玻璃基板。 I艨以接口 -根據本發明的目的,再提出光學封裝件,包括基材、光學 兀件、間隔材以及玻璃基板。基材具有第-對位圖帛,光學元 件係設置於基材上。間隔材係塵合於基材上,間隔材且有一開 :以及-貫孔,開口對應於光學元件,第一對位圖案係對應於 2。玻璃基板係Μ合於間隔材上,玻璃基板具有第二對 案對應於貫孔。 為讓本發明之上述目的、特徵、和優點能更明顯易懂,下 I282606
二達編號TW2273PA '文特舉一較佳實施例,並配合所附圖式,作詳細說明如下: . 【實施方式】 从第2A〜犯圖,其纷示依照本發明一較佳實施例之光學元 件的封裝流程圖。本實施例之光學元件的封裝方法包括下列步 風首先如第2A圖所不,提供基材1〇〇,其表面設置數個光 干兀件11〇,基材100具有至少二第一對位圖帛⑻及ι〇4。基 材⑽較佳的是CMOS晶圓。同時,如第2β圖所示,提供間 隔材120,間隔材120具有數個開口 125以及至少二貫孔122 及124。間隔材120較佳的是利用晶圓银刻而成,其詳細形成 步驟如下所述。在製作間隔材的過程中,提供晶圓,並形成圖 案化光阻層於晶圓上,最後再依據圖案光阻層’將晶圓钱刻出 複數個開口 125以及至少二貫孔i22及i24。 之後’利用數個第一對拉圖案1〇2及1〇4及數個貫孔122 及124作對位,將數個開口⑵對應於數個光學元件11〇,如 弟2 C圖所示’並據以接合基材工〇 〇與間隔材i 2 〇。更詳細地說, 百先將感光元件聚焦於基材1〇〇與間隔材12〇之交界處,感光 元件例如是電荷_合元件(Charge c〇upled以心,cc,之 後,調整基材100與間隔材12〇之相對位置,將數個開口 i25 分別對應於數個光學元件11〇。請參照第2D圖,其緣示依照第 2C圖中之剖面線2D_2D’的剖面圖。間隔材12()之開口 ^係 朝向光學元件110,使得光學元件11〇位於間隔材12〇與基材 100所形成的凹槽中。然後,微調間隔材120與基材1〇〇之間 的相對位置,並且利用感光元件感測以將數個第-對位圖案二2 及104對應於數個貫孔122及124中,如第%圖所示。也就是 說,當感光元件透過貫孔122可以偵測到第—對位圖案M2, 1282606
三達編號TW2273PA 透過貫孔124可以偵測到第一對位圖# 12“寺,即完成對位。 '在對位完成之後,最後才壓合基材100與間隔材120。 . 再者,提供玻璃基板BO,具有至少二第二對位圖案132 及134,如H 2E圖所示。玻璃基板13〇較佳的是玻璃晶圓。接 者’利用數個第二對位圖f 132及134及數個貫孔122及124 作對位,亚據以接合間隔材12〇與玻璃基板,如第汗圖所 不。在操作上’首先將感光元件聚焦於間隔材12〇與玻璃基板 • U〇之交界處,然後調整間隔材120與玻璃基板130之相對位 置。同時’利用感光兀件感測以將二第二對位圖帛132及工Μ 對應於二貫孔122及124中,如第2F圖所示。也就是說,當感 光兀件穿透玻璃基板13〇可以偵測到第二對位圖案132位於貫 孔122中,第二對位圖案134位於貫孔124中時,即表示對位。 經對位完成之後,最後才壓合間隔材12〇與玻璃基板13〇。請 麥照第2G圖,其繪示依照第2F圖中之封裝件沿著剖面線 2G-2G’之剖面圖。於此步驟完成之後,間隔材12〇係壓合於基 材100上,間隔材12〇之開口 125對應於光學元件11〇,且玻 • 璃基板13 0係壓合於間隔材i 2〇上。 #進一步地說,本發明亦可以將基材、間隔材以及玻璃基板 重疊在一起之後,再進行對位。只要將感光元件聚焦於基材與 、間隔材之間,或是間隔材與玻璃基板之間,就可以分別對位, 表後也將達到相同的功效。 最後,本實施例之光學元件的封裝方法較佳的是包括步 驟:切割已接合之基材、間隔材以及玻璃基板,並據以形成複 數個光學封裝件,第2H圖所示。藉此,完成光學元件的封裝, 而利用上述方法封裝而成的其中之一個光學封裝件包括基材 1〇〇、光學元件110、間隔材12〇以及玻璃基板13〇。基材1〇〇 8 1282606
Ξ達編號TW2273PA 具有第一對位圖案102,光學元件110係設置於基材1〇〇上。 間隔材120係壓合於基材1〇〇上,間隔材12〇具有開口 125以 及貫孔122,開口 125對應於光學元件110,第一對位圖案1〇2 係對應於貫孔125。玻璃基板130係壓合於間隔材12〇上,玻 璃基板130具有第二對位圖案132對應於貫孔122。如此一來, 光學元件no例如是DMD晶片,便可將透過玻璃基板13〇入 射的光線進一步地反射或者折射。
一此外,基材100較佳的是CMOS晶圓(CMOS wafer),間 Μ才m #父佳的是利用晶圓韻刻而成,玻璃基板較佳的是 :璃晶圓(glass wafer)。如此一來,從擺置基材、韻刻間隔材、 擺置玻璃基板到對位皆可於舊有的封裝機台上完成。 。、赍明上述實施例所揭露之光學元件的封裝方法及結構, ^善傳統上無法利用感光元件對位的問題。由於光學元件的 ^時必須加人間隔材,讓基材與玻璃基板之間撐開-段距 敷使件。而傳統的封裝時對位所採用的方法已不 上以在間㈣巾形成貫孔,並於賴基板與基材 及圖案:如此一來,感光元件可以透過玻璃基板以 可以沿用:右動?對位製各’既不需要添賭新的廠房設備,更 精確ΐ位之後的^台進行封裝。再者,光學元件經過上述方法 =之後,可以準確控制後續製程,並提高製程良率。 並非用eUt然本發明已以—較佳實施例揭露如上,然其 精神和範_,t ^者在不脫離本發明之 範圍當視後附之卜”更動舁潤飾,因此本發明之保護 灸附之申#專利範圍所界定者為準。 9 1282606
三達編號TW2273PA 【圖式簡單說明】 第1圖是投影晶片之封裝結構圖。 • 第2A〜2H圖繪示依照本發明一較佳實施例之光學元件的 • · 封裝流程圖。 【主要元件符號說明】 10 :基材 11 :投影晶片 12 :間隔材 % 13 :玻璃基板 20 :投影晶片的封裝件 100 :基材 102、104 :第一對位圖案 110 :投影晶片 120 :間隔材 122、124 :貫孔 130 :玻璃基板 132、134 :第二對位圖案 200 :光學元件的封裝件 10
Claims (1)
1282606 三達編號TW2273PA 十、申請專利範圍: 1 · 一種光學元件之封裝方法,包括步驟·· j供—基材’其表面設置複數個光學㈣,該基材具有至 ^'一第一對位圖案; 提供一間隔材,該間隔材具有複數個開口以及至少二貫孔; 利用該些第一對位圖案及該些貫孔作對位,將該些開口對 應於料光學元件,並據以接合該基材與該間隔材;
提供一玻璃基板’具有至少二第二對位目案;以及 利用該些第二對位圖案及該些貫孔作對位,並據以接合該 間隔材與該玻璃基板。 2·如中請專利範圍第“請述之封裝方法,其中提供該間 隔材之步驟更包括: 提供一晶圓; 形成一圖案化光阻層於該晶圓上;以及 依據該圖案化光阻層,將該晶圓钱刻出複數個開口以及至 3.如申請專利範圍第i項所述之封裝方法,其中接合該基 材與該間隔材之步驟更包括·· 土 將感光兀件聚焦於該基材與該間隔材之交界處; 调整該基材與該間隔材之相對位置,將該些開口分 於該些光學元件; 4 利用4感光兀件感測以將該些第一對位圖案對應於該些 孔中;以及 一、 壓合該基材與該間隔材。 11 ^ 1282606 三達編號 TW2273(061103)CRF
日修漫)正替換頁
' 4·如中請專利範圍第i項所述之封裝方法,其中接合該間 隔材與该玻璃基板之步驟更包括·· • 豸該感光元件聚焦於該間隔材與該麵基板之交界處; 調整該間隔材與該玻璃基板之相對位置; 利用該感光元件感測以將該些第二對位圖案對應於該些貫 孔中;以及 壓合該間隔材與該玻璃基板。 5·如申請專利範圍第3或4項所述之封裝方法,其中該感 光元件係一電荷耦合元件(Charge Coupled Device,CCD)。 6·如申請專利範圍第1項所述之封裝方法,更包括步驟: 切割已接合之該基材、該間隔材以及該玻璃基板,並據以 形成複數個光學封裝件。 7· —種光學封裝件,包括: 一基材,具有一第一對位圖案; 一光學元件,係設置於該基材上; 一間隔材,係壓合於該基材上,該間隔材具有一開口以及 貝孔’該開口對應於該光學元件,該第一對位圖案係對應於 該貫孔;以及 一玻璃基板,係壓合於該間隔材上,該玻璃基板具有一第 二對位圖案對應於該貫孔。 12 Ί282606 三達編號 TW2273(061103)CRF 月修(费)正替换頁 8.如申請專利範圍第7項所述之光學封裝件,其中該間隔 材係一晶圓蝕刻而成。
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TW094142663A TWI282606B (en) | 2005-12-02 | 2005-12-02 | Method for packaging optical chip and packaging structure thereof |
US11/606,085 US7855424B2 (en) | 2005-12-02 | 2006-11-30 | Method for packaging semiconductor device and package structure thereof |
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TW094142663A TWI282606B (en) | 2005-12-02 | 2005-12-02 | Method for packaging optical chip and packaging structure thereof |
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TWI282606B true TWI282606B (en) | 2007-06-11 |
TW200723460A TW200723460A (en) | 2007-06-16 |
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CN107180843B (zh) * | 2017-05-17 | 2020-02-18 | 京东方科技集团股份有限公司 | 一种封装面板、器件封装结构及其制备方法 |
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US6441481B1 (en) * | 2000-04-10 | 2002-08-27 | Analog Devices, Inc. | Hermetically sealed microstructure package |
JP2004047561A (ja) * | 2002-07-09 | 2004-02-12 | Olympus Corp | 光導電スイッチモジュールおよびその製造方法 |
US6929974B2 (en) * | 2002-10-18 | 2005-08-16 | Motorola, Inc. | Feedthrough design and method for a hermetically sealed microdevice |
JP2005056998A (ja) * | 2003-08-01 | 2005-03-03 | Fuji Photo Film Co Ltd | 固体撮像装置およびその製造方法 |
US7632713B2 (en) * | 2004-04-27 | 2009-12-15 | Aptina Imaging Corporation | Methods of packaging microelectronic imaging devices |
US7429494B2 (en) * | 2004-08-24 | 2008-09-30 | Micron Technology, Inc. | Microelectronic imagers with optical devices having integral reference features and methods for manufacturing such microelectronic imagers |
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