1281842 九、發明說明： 【發明所屬之技術領域】 纟發明是有關於-種多電路元件晶片之製造方法，特 別是指-種具凸出端電極多電路^件晶片之製造方法。 【先前技術】 夕電路7L件晶片係於單一晶片内並列設置數個電路元 件，例如多電阻晶片、多電容晶[這些電路元件相互間1281842 IX. Description of the Invention: [Technical Field of the Invention] The present invention relates to a method for manufacturing a multi-circuit device wafer, and more particularly to a method for manufacturing a multi-circuit wafer having a projecting terminal electrode. [Prior Art] 7L pieces of chips are arranged in a single wafer in parallel with a plurality of circuit elements, such as a multi-resistance chip, a multi-capacitor crystal [these circuit elements are mutually
並未電性連接而各自擁有用以導接外界的兩電極，使多電 路70件晶片具有多數電極。 如圖1與圖2’習用多電阻晶片係形成於一陶究基板】 上。陶i基板1規劃有複數條縱向分割線u與橫向分割線 12’以區隔成多數個矩陣排列之陶瓷基體13。各陶瓷基板 13上表面設有數組分置於兩側之導電區塊，每組導電區塊 為兩個上電極m’及複數橋接對應組内的兩上電極i3i之 電阻膜132。另外，習时法於陶竞基板丨上更會貫穿設置 夕數個穿孔133 ’各穿孔133係位於相鄰上電極ΐ3ι間，以 確保兩相鄰上電極131間保持間距。又，在㈣基板i 之下表面形成有複數個下電㉟131，，其位置分別與各陶究 基體13之各上電極131對應。 而後，如圖3，在電阻膜132上形成一保㈣134。緊 接著，如圖4,先把陶隸板！沿縱向分割線u分割成複 數條’再於各條陶究基板i之兩端沾銀膠，如圖5，以兩側 面形成複數個導接上、下電極m、i31，之側面電極135。 在沾銀膠過程中，銀膠除形成於_基體13的上、下電極 5 1281842 131、131’間的側面外 盥穿孔133东m丨 日復盍邛刀上、下電極131、131， ，、牙 ^近側面電極135的部分壁面上。 此後’再把各條陶細反 顆之陶兗基體13後，如R “ 丄線12刀割成早 莫上、下雪杯”與圖7’執行電鍍，以形成覆 现上下電極13 1、13 1，盒侧面雷托！以人人 作為導接m予 ，、側面電極135的端電極136,來 作為導接至诸如電路板之類的其他電子裝置的電極。 述二電鑛時，金屬會於導電面上沉積。然而，如前所 電阻晶片係以沾轉來形成側面電極135,使沾 銀膠範圍無法作精密有效的控制，而會形成於穿孔133鄰 近側面電極13 5 όθ立β八后奈二1 的邛刀壁面上，致使端電極136電鍍過程 中，金屬除沉積於上、下雷托m ^ 上下電極131、131，與側面電極135外 ’更會沉積於穿孔133的壁面上，使得端電極136的形狀 ㈣向朝穿孔133部分延伸㈣成類似㈣頭狀。如此， 端電極136亦會成長於穿133的壁面上，致使相鄰端電 極~136間的間隔距離縮小，於兩相鄰端電極136間傳輸資 料容易發生串音（cross talk)情況，而無法正常工作。又，隨 著電子元件的微小化趨勢，諸如多電阻晶片之類的多電路 凡件晶片亦不可避免的體積微小化，使得多電路元件晶片 上的各構件的體積亦隨之縮小，兩端電極136間的穿孔133 尺寸亦隨之縮小至逼近絕緣距離，指不會產生串音的絕緣 距離。然而，習用多電阻晶片的端電極136形成過程中， 金屬層又會側向朝穿孔133部分延伸，有限穿孔133間距 又縮小，導致不良品的發生機率又提高。 【發明内容】 1281842 由替方… …穿孔内壁面形成絕緣層並改 由歲鍍方式形成側面電極於±、 面電極的形成位置，進而踮&。 以有效控制側 的距離不Λ 冤鍍柃，兩端電極間 離不j病電極的㈣而下降，以解決前述問題。 本發明之一目的，為担祝 八種可提高產品良率呈 出端電極多電路元件晶片之製造方法。 /、 本發明之又一目的，Λ袒处 # , 在鐽供—種保持兩電極間的距離They are not electrically connected and each has two electrodes for guiding the outside, so that the multi-circuit 70 wafers have a plurality of electrodes. As shown in Fig. 1 and Fig. 2', a multi-resistance chip is formed on a ceramic substrate. The ceramic substrate 1 is patterned with a plurality of longitudinal dividing lines u and lateral dividing lines 12' to partition the ceramic substrate 13 into a plurality of matrixes. The upper surface of each ceramic substrate 13 is provided with a plurality of conductive blocks disposed on both sides, and each set of conductive blocks is two upper electrodes m' and a plurality of resistive films 132 bridging the upper electrodes i3i in the corresponding groups. In addition, the chronological method is further disposed on the terracotta substrate, and a plurality of perforations 133 ′ are disposed between the adjacent upper electrodes ΐ31 to ensure a spacing between the adjacent upper electrodes 131. Further, a plurality of power-offs 35131 are formed on the lower surface of the (4) substrate i, and their positions correspond to the respective upper electrodes 131 of the respective ceramic substrates 13. Then, as shown in FIG. 3, a protective film (four) 134 is formed on the resistive film 132. Next, as shown in Figure 4, first put the pottery board! The longitudinal dividing line u is divided into a plurality of strips ′ and silver paste is applied to both ends of each of the ceramic substrates i. As shown in Fig. 5, a plurality of side electrodes 135 for guiding the upper and lower electrodes m and i31 are formed on both sides. In the process of sticking silver paste, the silver glue is formed on the side of the upper and lower electrodes 5 1281842 131, 131' of the base 13 and the perforation 133 of the upper and lower electrodes 131, 131, The teeth are on the wall surface of the side surface electrode 135. Thereafter, after each of the ceramics and the ceramic substrate 13 is further polished, the plating is performed as shown in Fig. 7', and the upper and lower electrodes 13 1 are formed. 13 1, box side Leito! The terminal electrode 136 of the side electrode 135 is used as a guide for connection to an electrode of another electronic device such as a circuit board. When the second ore is described, the metal is deposited on the conductive surface. However, if the former resistive wafer is formed by the dip to form the side electrode 135, the range of the silver paste can not be precisely and effectively controlled, and it is formed on the side of the through hole 133 adjacent to the side electrode 13 5 όθ立β八后奈二1 On the wall surface of the knife, during the electroplating process of the terminal electrode 136, the metal is deposited on the upper and lower Leito m ^ upper and lower electrodes 131, 131, and the outer surface of the side electrode 135 is deposited on the wall surface of the through hole 133, so that the end electrode 136 The shape (4) extends toward the perforation 133 portion (four) into a similar (four) head shape. In this way, the terminal electrode 136 also grows on the wall surface of the 133, so that the distance between the adjacent terminal electrodes 136 is reduced, and the transmission of data between the two adjacent terminal electrodes 136 is prone to cross talk, and cannot be performed. normal work. Moreover, with the trend of miniaturization of electronic components, multi-circuit wafers such as multi-resistive wafers are inevitably miniaturized, and the volume of each component on the multi-circuit component wafer is also reduced. The size of the 136 perforations 133 is also reduced to approach the insulation distance, referring to the insulation distance that does not produce crosstalk. However, during the formation of the terminal electrode 136 of the conventional multi-resistance wafer, the metal layer will extend laterally toward the perforation 133 portion, and the pitch of the limited perforation 133 is further reduced, resulting in an increase in the probability of occurrence of defective products. SUMMARY OF THE INVENTION 1281842 is formed by forming an insulating layer on the inner wall surface of the perforation, and forming a side electrode on the surface of the ± surface electrode by the ageing plating method, and then 踮 & The distance between the effective control side is not 冤 冤, and the electrodes at both ends are separated from the (4) electrode of the diseased electrode to solve the above problem. SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a terminal electrode multi-circuit component wafer which can improve the yield of the product. /, another object of the present invention, the #where # , in the 鐽 supply - kind of maintaining the distance between the two electrodes
八凸出知電極多電路元件晶片之製造方法。 、本發明之再一目的，在提供一種有效避免短路盘串音 兔生之^凸出端電極多電路元件晶片之製造方法。 、於疋，本發明具凸出端電極多電路元件晶片之製造方 法’係包含以下步驟： 、 (Α)提供-基板’該基板界定複數條橫向線與複數條 縱向線以區隔成多數個呈矩陣排列之基體，各該基體之上 表面由左而右並列間隔地延伸數條導電區塊，且各該基體 分別於各該導電區塊中兩相鄰導電區塊中的間隔區域的左 、右兩端設置一貫穿該基體之上、下表面之穿孔，該等穿 孔更位於該對應縱向線上； (B)形成-覆蓋該基板之上表面、了表面與該等穿孔 内壁面之絕緣層； (C ) /σ 5亥等縱向線分割該基板成複數個條狀體； (D)濺鍍於該條狀體之左、右側壁面中未形成該絕緣 層的剩餘壁面上，以形成複數個導接對應的導電區塊的左 、右端的側面電極； 1281842 (E)沿該等橫向線分割該等條狀體成該等獨立基體； 及 (F)電鍍該等基體，以於各該側面電極上形成一端電 極。 【實施方式】 有關本發明之前述及其他技術内容、特點與功效，在 以下配合參考圖式之一個較佳實施例的詳細說明中，將可 清楚的呈現。 為避免習知問題，本發明具凸出端電極多電路元件晶 片之製造方法係先以絕緣材質遮蔽穿孔的内壁面，以於濺 鍍形成側面電極時，兩電極間的穿孔壁面未裸露，自無法 於後續電鑛端電極時沉積金屬，進而可確保電極間之絕緣 距離。 在下文中’配合圖8來說明本實施例中製造多電路元 件晶片的方法。 首先’在步驟21中提供一基板3。如圖9與圖ι〇，基 板3之上表面延伸複數條縱向預刻痕31(指縱向線）與複數條 與縱向預刻痕31正交之橫向預刻痕32(指橫向線），以分隔 成複數個呈矩陣排列之基體4。又，為便於後續製程中分割 基板3 立基體，本實施例制痕3卜32係於基板3形 成一如V型之刻痕，但亦可為其他形狀的刻痕，如平底凹乂 槽亦可。然而，熟習該項技藝者當知，係可省略預刻痕Μ 、32而於後續製程中直接分割基板3。 各基體4之上表面並列佈設複數個導電區塊，各導電 8 1281842 區塊含兩個間隔地位於基體4之上表面兩端之上電極4i、 -橋接兩上電極41之導電薄膜42與一覆蓋這些導電薄膜 42與該等上電極41中鄰近對應的導電薄膜42的部分之保 護層4 3。本例中基板3係—㈣基板，而導電薄膜4 2係電 阻膜X ’各基體4之下表面與上電極41相對之位置亦形 成有下電極44,以使多電路元件晶片可以表面黏著（smt)方 式導接至其他電子裝置上。再者，陶莞基板3上亦貫穿設 有夕數牙孔33，各穿孔33係位於兩相鄰上電極41間。本 例中保遵層43的作用為絕緣及防焊，其材質為環氧樹脂 (Epoxy)，如 Epoxy M〇lding c〇mp〇unds(Fused 川㈣。 萝“'、後纟先鍍形成側面電極前’先於步驟22中形成一 後盍基板3之上表面、下表面與穿孔33内壁面之絕緣層。 詳細來說，如圖11與圖12 ’先於基板3之上表面以印 職印刷複數條縱向絕緣條45，各上縱向絕緣條β係於兩 相部的縱向預刻痕31間延伸而覆蓋對應的保護層Μ盘上 =極Λ中鄰近保護層43的部分，仍使這些上電極41遠離 電薄膜42之部分裸露，即各上縱向絕緣條^的縱向側 縱向預刻痕31間保持-段距離但仍覆蓋各穿孔33的 護層43的部分。本實施例中上縱向絕緣條μ的材 貝為玻璃糊且其印刷厚度㈣·m。當玻璃糊印刷至基 之初破璃糊會接近液態，本實施先將基板 二台面’由上往下吸真空，使玻璃糊溢流至穿孔33 的内：面’而後再經爐子進行烘乾程序。 '、 ^ 13與圖14 ’再於基板3之下表面以印刷機 9 1281842 印刷複數條下縱向絕緣條46，各下縱向絕緣條46的位置八 別與對應的上縱向絕緣條45相對，且下縱向絕緣條 縱向側邊亦與縱向預刻痕31保持一定距離且覆蓋 鄰近保護…部分，以覆蓋各下電…近中央的:: 刀並使其通離中央的部分裸露。而後，本實施例之下縱向 絕緣條46之材質亦為玻璃糊，製造時，亦先將基板3下： 面朝上地置放吸真空台面後，由上往下吸真空糊 溢流至穿孔33内辟而你 $ y 禹糊 土面後，再經爐子進行烘乾程序。如此， 如圖15’各穿孔33内壁面亦佈滿玻璃糊而為絕緣條45、 46的K申因而，絕緣層具有上縱向絕緣 緣條46與穿孔33内壁面上的供乾玻璃糊。 向絶 在形成絕緣層後，執行步驟23,如圖^ 刻痕31分割基板3成複數條狀體34,其後，如圖17 : 堆豐"些條狀體34，使各條狀體34的左、右側面朝外。 在㈣24，於各條狀體34的左、右側 =屬，以於各條狀體34未有絕緣層的裸露壁面沉積金屬 左、=H19 ’側面電極47會形成於條狀體34的 工 的裸路壁面（指兩相鄰穿孔33間的側壁面）上 ;電極41的裸露部分與下電“的裸露部分上，以確 =電極47係電性導接至上、下電極…料。本例中確 l = H於上條狀體34的左、右壁面的厚度約為咖入 及方；基板3之上、下雷搞划八 及_材質為鎳鉻合金：可::厚^ 及銅中的任一種。 了為鎳銅合金、鈦鎢合金 10A method of manufacturing an eight-bumped electrode multi-circuit device chip. Still another object of the present invention is to provide a method of manufacturing a multi-circuit element wafer which is effective for avoiding short-circuiting of a cross-talk. In the present invention, the method for manufacturing a multi-circuit component wafer with a protruding terminal electrode includes the following steps: (providing) providing a substrate - the substrate defining a plurality of transverse lines and a plurality of longitudinal lines to be divided into a plurality of a matrix arranged in a matrix, each of the upper surfaces of the substrate extending from the left and the right by a plurality of conductive blocks, and each of the substrates is respectively disposed on the left of the spaced regions of the two adjacent conductive blocks in each of the conductive blocks The right end is provided with a through hole penetrating the upper surface and the lower surface of the substrate, and the through holes are located on the corresponding longitudinal line; (B) forming an insulating layer covering the upper surface of the substrate, the surface and the inner wall surface of the perforations (C) / σ 5 hai and other longitudinal lines divide the substrate into a plurality of strips; (D) sputtered on the left and right side walls of the strip without forming the remaining wall surface of the insulating layer to form a plurality Leading the left and right side side electrodes of the corresponding conductive block; 1281842 (E) dividing the strips into the independent bases along the transverse lines; and (F) plating the substrates for each One end electrode is formed on the side electrode. The above and other technical contents, features, and advantages of the present invention will be apparent from the following detailed description of the preferred embodiments. In order to avoid the conventional problem, the method for manufacturing a multi-circuit element wafer with a protruding end electrode is to first cover the inner wall surface of the perforation with an insulating material, so that when the side electrode is formed by sputtering, the perforated wall surface between the two electrodes is not exposed, since It is impossible to deposit metal at the subsequent electrode end electrode, thereby ensuring the insulation distance between the electrodes. A method of manufacturing a multi-circuit element wafer in this embodiment will be described hereinafter with reference to Fig. 8. First, a substrate 3 is provided in step 21. As shown in FIG. 9 and FIG. 9 , the upper surface of the substrate 3 extends a plurality of longitudinal pre-scratches 31 (referring to longitudinal lines) and a plurality of transverse pre-scratches 32 (referring to transverse lines) orthogonal to the longitudinal pre-scratches 31 to Separated into a plurality of substrates 4 arranged in a matrix. Moreover, in order to facilitate the division of the substrate 3 in the subsequent process, the mark 3 32 is formed on the substrate 3 to form a V-shaped score, but may also be a mark of other shapes, such as a flat bottom groove. can. However, those skilled in the art will recognize that the pre-notch Μ, 32 can be omitted and the substrate 3 can be directly divided in subsequent processes. A plurality of conductive blocks are arranged side by side on the upper surface of each of the base bodies 4. Each of the conductive 8 1281842 blocks includes two electrodes 4i spaced apart from each other on the upper surface of the upper surface of the base 4, and a conductive film 42 that bridges the upper electrodes 41 and one The protective layer 43 of the conductive film 42 and a portion of the upper electrode 41 adjacent to the corresponding conductive film 42 is covered. In this example, the substrate 3 is a (four) substrate, and the conductive film 42 is a resistive film X'. The lower surface of each substrate 4 is also formed with a lower electrode 44 at a position opposite to the upper electrode 41, so that the multi-circuit component wafer can be surface-attached ( The smt) method is connected to other electronic devices. Further, the porphyron substrate 3 is also provided with a plurality of occlusion holes 33, and each of the perforations 33 is located between the adjacent upper electrodes 41. In this example, the function of the protective layer 43 is insulation and solderproofing, and the material thereof is epoxy resin (Epoxy), such as Epoxy M〇lding c〇mp〇unds (Fused Chuan (4). Before the electrode, an insulating layer is formed on the upper surface of the rear substrate 3 and the lower surface and the inner wall surface of the through hole 33 in step 22. In detail, as shown in Fig. 11 and Fig. 12, the upper surface of the substrate 3 is printed. Printing a plurality of longitudinal insulating strips 45, each of which extends between the longitudinal pre-scorings 31 of the two-phase portion to cover the portion of the corresponding protective layer of the crucible disk adjacent to the protective layer 43 in the poles, still making these The portion of the upper electrode 41 away from the electric film 42 is exposed, that is, the portion of the longitudinally longitudinal pre-scratch 31 of each upper longitudinal insulating strip maintains a segment distance but still covers the portion of the sheath 43 of each of the perforations 33. In the present embodiment, the upper longitudinal direction The material of the insulating strip μ is glass paste and its printing thickness is (4)·m. When the glass paste is printed to the base, the glass paste will be close to the liquid state. In this embodiment, the two substrates of the substrate are vacuumed from top to bottom to make the glass paste. Overflow to the inside of the perforation 33: the surface 'and then through the furnace for the drying process. ', ^ 13 and FIG. 14' further printed a plurality of lower longitudinal insulating strips 46 on the lower surface of the substrate 3 by a printing machine 9 1281842, the position of each of the lower longitudinal insulating strips 46 being opposite to the corresponding upper longitudinal insulating strip 45, and the lower longitudinal insulating layer The longitudinal side edges of the strip are also kept at a certain distance from the longitudinal pre-scratch 31 and cover the adjacent protective portion to cover the respective lower... near the center: the knife and the portion which is open from the center is exposed. Then, under the present embodiment The material of the longitudinal insulating strip 46 is also a glass paste. When manufacturing, the substrate 3 is also placed first: after placing the vacuum chucking surface face up, the vacuum paste overflows from the top to the bottom to the inside of the perforation 33 and you $ y After pasting the soil surface, the drying process is carried out through the furnace. Thus, as shown in Fig. 15', the inner wall surface of each of the perforations 33 is also covered with a glass paste to be the insulating strips 45, 46, and the insulating layer has an upper longitudinal insulating strip. 46 and the dry glass paste on the inner wall surface of the perforation 33. After the insulating layer is formed, step 23 is performed, as shown in Fig. 2, the substrate 31 is divided into a plurality of strips 34, and thereafter, as shown in Fig. 17 "Some strips 34 such that the left and right sides of each strip 34 face outward. (4) 24, in the left and right sides of each strip 34 = genus, so that each strip body 34 has no insulating layer on the exposed wall surface deposited metal left, = H19 'side electrode 47 will be formed in the strip body 34 naked The wall surface (refers to the side wall surface between the two adjacent perforations 33); the bare portion of the electrode 41 and the bare portion of the "powered" portion are electrically connected to the upper and lower electrodes of the electrode 47. In this example, It is true that the thickness of the left and right walls of the upper strip 34 is about the coffee and the square; the top of the substrate 3, the lower mine is drawn and the material is nickel-chromium alloy: can be: thick ^ and copper Any one. Nickel-copper alloy, titanium-tungsten alloy 10
1281842 在側面電極47形成後，於步驟 不再需要之昭@ s 中，如圖20 ,移除 33:辟 (指上、下縱向絕緣條45、4"各穿孔 内壁面的部分絕緣層）。本實施例中技收 ^ 泊於盖、丨、未攸& j中，係將條狀體34浸 、、々克隆中並施加超音波來清除絕緣層。 緊接著，在步驟26中，在沪护 狀_ M m 1 杈向預割痕32分割各條 :成如圖21的獨立基體4。此刻，各基體4左、右側 33 中、、·邑緣層的覆蓋與_後步驟25移除絕緣層的步H 自不會有因形成側面電極步驟24所沉積之金屬膜。 因而，最後，在步驟27，以諸如滾鑛方式電鑛各基體 金屬會沉積於各基體4之側面電才亟47、上電極41、下 電極44的裸露部分上，以形成端…。如此，端電極 48於電錢過程中除於上、下電極41、44上沉積金屬外，僅 曰於側面電極47上沉積金屬，使兩側面電極47間的穿孔 33内壁面裸露而未沉積金屬，致使端電極48成為凸出端電 極。本例中端電極48電錄過程中，錢㈣錄再電鍵錫， 而為兩層之金屬結構。 據前所述，本發明係先以絕緣層覆蓋基板3的上、下 表面與各穿孔33的内壁面，始以濺鍍形成側面電極竹，而 後再將絕緣層移除，以確保僅於基體4左右側壁面中與穿 孔33位置錯開的壁面形成金屬膜，以有效限制側面電極们 的形成位置’進而確保兩側面電極47間的穿孔33壁面不 會有任何金屬，因而電鍍端電極48自不會於兩側面電極〇 間的壁面 >儿積金屬，以確保端電極48成長時不會縱向（指沿 11 1281842 白刀口j線之方向）發展，使得兩相 M而電極48間的距離不 曰酼知電極48的形成而改變，以達 之跖龃μ 1 違j可維持兩相鄰電極間 產口沾白方 日一紐路情況發生，以提升 -的良率。同時’由於兩相鄰端電極 會隨製造過程而縮小，於設計時，“間隔距離不 f桩了令兩者間的間隔距離 更接近絶緣距離，甚至等於絕緣距離， ，以符合產品微小化之趨勢。 吏传產-更可縮小 =者’雖前述實施例以同時製造多個多電路元件晶片 然而熟習該項技藝者當知，本發明亦可僅製 '夕電路兀件晶片’並不應受限於本實施例所揭露。1281842 After the side electrode 47 is formed, in the step s@s, which is no longer needed in the step, as shown in Fig. 20, the 33: s (refers to the upper and lower longitudinal insulating strips 45, 4" a part of the insulating layer on the inner wall surface of each perforation). In the embodiment, the cover is immersed in the cover, the cymbal, the untwisted & j, and the strip 34 is immersed, cloned, and ultrasonically applied to remove the insulating layer. Next, in step 26, the strips are split into the pre-cuts 32 in the hull _M m 1 : : into the independent base 4 of Fig. 21. At this moment, the covering of the left and right sides of each of the substrates 4, the covering of the rim layer, and the step H of removing the insulating layer in the subsequent step 25 do not have the metal film deposited by the side electrode forming step 24. Thus, finally, in step 27, each of the base metals in the ore-like manner is deposited on the bare portions of the side electrodes 47, the upper electrode 41, and the lower electrode 44 of each of the substrates 4 to form ends. In this manner, the terminal electrode 48 deposits metal on the side electrode 47 only in the process of the money, except that the metal is deposited on the upper and lower electrodes 41, 44, so that the inner wall surface of the through hole 33 between the two side electrodes 47 is exposed without depositing metal. The terminal electrode 48 is caused to be a convex terminal electrode. In this example, in the process of recording the terminal electrode 48, the money (4) is recorded as a second metal structure. According to the foregoing, the present invention first covers the upper and lower surfaces of the substrate 3 and the inner wall surface of each of the through holes 33 with an insulating layer, and initially forms a side electrode bamboo by sputtering, and then removes the insulating layer to ensure that only the substrate is provided. 4, the wall surface of the left and right side wall faces which are offset from the position of the perforation 33 forms a metal film to effectively limit the formation position of the side electrodes, thereby ensuring that the wall surface of the perforation 33 between the side electrodes 47 does not have any metal, and thus the plated electrode 48 is not Metal will accumulate on the wall between the two side electrodes to ensure that the terminal electrode 48 does not grow longitudinally (in the direction of the 11 1281842 white blade j line), so that the distance between the two phases M and the electrode 48 is not It is known that the formation of the electrode 48 is changed, so that the 跖龃μ 1 violation j can maintain the occurrence of a white-to-nale relationship between the two adjacent electrodes to improve the yield. At the same time 'because the two adjacent end electrodes will shrink with the manufacturing process, in the design, "the spacing distance is not so the distance between the two is closer to the insulation distance, or even equal to the insulation distance, in order to meet the miniaturization of the product. Trends. 吏 产 - 更 更 更 更 者 者 者 ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' It is limited by the embodiment.
At、以上所述者，僅為本發明之較佳實施例而已’當不 月匕以此限定本發明實施之範圍，即大 田 範圍及發明說明内容所作之簡單的等效,m請專利 屬本發明專利涵蓋之範圍内。〜化與修飾’皆仍At least, the above is only a preferred embodiment of the present invention and has been used to limit the scope of the implementation of the present invention, that is, the simple equivalent of the field scope and the description of the invention. Within the scope of the invention patent. 〜化和装修’ are still
12 1281842 【圖式簡單說明】 圖！〜圖7是-種習用多電阻晶片之製造流程 、圖8是本發明具凸出端電極多電路元件晶片:圓、， 去的較佳實施例的流程圖； ^造方 圖9是本實施例的基板的局部示意圖； 圖10是沿圖9的剖面線71_71，的剖面示意圖； 圖11是本實施例基板的上表面形成上縱向絕12 1281842 [Simple description of the map] Figure! 7 is a manufacturing flow of a conventional multi-resistance wafer, and FIG. 8 is a flow chart of a preferred embodiment of the present invention having a multi-circuit element wafer with a protruding end electrode: round, and FIG. FIG. 10 is a schematic cross-sectional view along the section line 71_71 of FIG. 9; FIG. 11 is an upper surface of the substrate of the present embodiment.
意圖； π的示 圖12是沿圖11的剖面線72-72,的剖面示意圖； 圖13是本實施例基板的下表面形成下縱向絕緣條的示 意圖； 圖14是沿圖11的剖面線73-73 ’的剖面示意圖； 圖15是沿圖11的剖面線74-74,的剖面示意圖； 圖16是本實施例的基板分割成條狀體的示意圖； 圖17是本實施例的條狀體堆疊的示意圖； 圖18是本實施例的條狀體的左、右側面經濺鍍的示意 圖19是沿圖18的剖面線75-75,的剖面示意圖； 圖20是本實施例中移除絕緣層後的剖面示意圖； 圖21是本實施例的條狀體分割成獨立基體之示意圖； 圖22是本實施的基體經電鍍端電極的示意圖；及 圖23是沿圖22的剖面線76-76’的剖面示意圖。 13 1281842 【主要元件符號說明】 21 〜27步驟 43 保 護 層 3 基板 44 下 電 極 31 縱向預刻 痕 45 上 縱 向絕緣條 32 橫向預刻 痕 46 下 縱 向絕緣條 33 穿孔 47 側 面 電極 34 條狀體 48 端 電 極 4 基體 71- .71 ? X 72-72、73-73、 41 上電極 74- •74 5、 75-75’ 、 76-76’ 剖 42 導電薄膜 面線 1412 is a schematic cross-sectional view along the section line 72-72 of FIG. 11; FIG. 13 is a schematic view showing the lower longitudinal insulating strip formed on the lower surface of the substrate of the present embodiment; FIG. 14 is a section line 73 along FIG. Figure 17 is a schematic cross-sectional view taken along line 74-74 of Figure 11; Figure 16 is a schematic view of the substrate of the present embodiment divided into strips; Figure 17 is a strip of the present embodiment; FIG. 18 is a schematic cross-sectional view along the line 75-75 of FIG. 18; FIG. 20 is a schematic view of the present embodiment. FIG. 21 is a schematic view showing the strip body of the present embodiment divided into independent substrates; FIG. 22 is a schematic view of the base electrode of the present embodiment through the plated end electrode; and FIG. 23 is a cross-sectional line 76-76 along FIG. 'The schematic diagram of the section. 13 1281842 [Description of main components] 21 to 27Step 43 Protective layer 3 Substrate 44 Lower electrode 31 Longitudinal pre-scratch 45 Upper longitudinal insulating strip 32 Transverse pre-scoring 46 Lower longitudinal insulating strip 33 Perforation 47 Side electrode 34 Strip 48 Terminal electrode 4 Base 71-.71 ? X 72-72, 73-73, 41 Upper electrode 74- • 74 5, 75-75', 76-76' Section 42 Conductive film upper thread 14