TWI281133B - System and method for checking offsets of a differential-mode signal line - Google Patents

System and method for checking offsets of a differential-mode signal line Download PDF

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TWI281133B
TWI281133B TW94144786A TW94144786A TWI281133B TW I281133 B TWI281133 B TW I281133B TW 94144786 A TW94144786 A TW 94144786A TW 94144786 A TW94144786 A TW 94144786A TW I281133 B TWI281133 B TW I281133B
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Taiwan
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differential signal
signal line
offset
segment
module
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TW94144786A
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Chinese (zh)
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TW200725495A (en
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Shou-Kuo Hsu
Cheng-Shien Li
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Hon Hai Prec Ind Co Ltd
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Publication of TW200725495A publication Critical patent/TW200725495A/en

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Abstract

The present invention relates to a system for checking offsets of a differential-mode signal line. The system includes: an input/output module for receiving a layout file of a differential-mode signal line; a dividing module for dividing the differential-mode signal line into a plurality of sections; a checking module for checking an offset of each section divided by the dividing module. A method for checking offset of a differential-mode signal line is also provided. Utilizing the system and the method can avoid working errors.

Description

1281133 九、發明說明: 【發明所屬之技術領域】 本發明涉及一種訊號線檢查系統及方法,特別是涉及一種差分訊 號線偏移量檢查系統及方法。 ° 【先前技術】 隨著PCB (Printed Circuit Board,印刷電路板)訊號線的各種佈線 技術的成熟和發展,人們爲了改進PCB訊號線的工作性能,對pcB訊 號線的排佈通常採用的是差分訊號線排佈形式。而差分訊號線傳輸的 差分訊號也因爲其精確的時序控制及更高的工作速度爲人們所熟知。 • 衆所週知,差分訊號線的排佈形式採取的是成對的訊號線並行佈 線形式,而差分訊號線的理想排佈形式是差分訊號線的兩條成對的訊 號線完全一致,且盡可能的靠近。這樣,差分訊號線上所傳輸的差分 訊號就能夠最大程度的進行耦合,且能完全的將出現的雜亂訊號消除 掉。實際上,人們不可能實現差分訊號線的理想排佈形式,差分訊號 線的兩條成對的訊號線必定有一個偏移量,這就意味著人們必須審慎 地設計差分訊號線的走勢,以盡可能的將出現的偏移量控制在一個合 理的範圍。 目前,人們對排佈的差分訊號線的偏移量的檢查方式是直接比較 差分訊號線的兩條成對的訊號線的總長度。然而,差分訊號線會經過 被動元件、過孔等可能造成阻抗不連續的部分,如果單比較總長度, 則誤差比實際要大的多。 避免不能分段比較差分訊號線的偏移量,有助於避免整體比較差 分訊號線的偏移量帶來的誤差。 【發明内容】 馨於以上内容,有必要提供一種差分訊號線偏移量檢查系統及方 法以分段比較差分訊號線的偏移量,避免整體比較差分訊號線的偏移 量帶來的誤差。 一種差分訊號線偏移量檢查系統,運行於一電腦中。該系統包括: 一輸入/輸出模組,用於導入印刷電路板差分訊號線的佈線文檔;一劃 6 1281133 分模組,用於將印刷電路板差分訊號線佈線文檔中的差分訊號線劃分 爲許多區段;一檢查模組,用於針對該劃分模組劃分的差分訊號線的 每一區段進行偏移量的檢查。 進一步地,該系統還包括:一選擇模組,用於選擇該檢查模組檢 查完成的差分訊號線區段。 進一步地,所述的輸入/輸出模組還用於在該印刷電路板差分訊號 線的佈線文檔中定位並用顏色標示選擇的差分訊號線區段,及將選擇 的差分訊號線區段檢查資訊以報表的方式導出來。 進一步地,所述的檢查模組還用於對劃分的每一區段進行偏移量 • 的合理上限值的設定並計算出各區段的實際偏移量,及逐一將各區段 偏移量的合理上限值與實際偏移量進行比對並給出比對結果。 進一步地,選擇的差分訊號線區段檢查資訊包括選擇的區段數、 選擇的各區段的實際偏移量、選擇的各區段偏移量的合理上限值及選 擇的各區段的實際偏移量與偏移量的合理上限值的比對結果。 一種利用電腦檢查差分訊號線偏移量的方法,包括如下步驟:(a) 導入印刷電路板差分訊號線的佈線文檔;(b)及將印刷電路板差分訊 號線佈線文檔中的差分訊號線劃分爲許多區段;(c)針對劃分的差分 訊號線的每一區段進行偏移量的檢查。 進一步地,該方法還包括步驟qd)選擇檢查完成的差分訊號線 區段,(e)在該印刷電路板差分訊號線的佈線文檔中定位並用顏色標 不選擇的差分訊號線區段;(f)將選擇的差分訊號線區段檢查資訊以報 表的方式導出來。 進一步地,步驟(c)包括··(cl)對劃分的每一區段進行偏移量 的合理上限值的設定,並計算出各區段的實際偏移量;(c2)逐一將各 區段偏移量的合理上限值與實際偏移量進行比對,並給出比對結果。 一相較習知技術,所述的差分訊號線偏移量檢查系統及方法,充分 考量了差分訊號線經過被動元件、過孔等造成的阻抗的不連續性 免了整體比較差分訊號線的偏移量帶來的誤差。 【實施方式】 7 1281133 參閱第一圖所示,係差分訊號線傳輸的差分訊號的示意圖。分別 於成對且等長的訊號線上傳輸的該正源差分訊號A和負源差分訊號B 相位差180度且強度值相同,而該正源差分訊號A和負源差分訊號B 中的雜亂訊號等大且同向。由於差分訊號線的工作取決於成對的兩條 訊號線上傳輸的訊號之間的強度差值,故該正源差分訊號A和負源差 分訊號B相減後,得到該平穩訊號c的強度值是該正源差分訊號A或 負源差分訊號B的強度值的兩倍。由於該正源差分訊號a和負源差分 訊號B相位差180度而相互成反向,故該正源差分訊號A和負源差分 訊號B的相減過程其實是一個訊號強度累加的過程,其原理好比是“工 —(一1) =2” ;而由於該正源差分訊號A和負源差分訊號B中的雜 亂訊號等大且同向,故雜亂訊號被抵消掉。 參閱第二圖所示,係本發明差分訊號線偏移量檢查系統較佳實施 方式的功能模組圖。該差分訊號線偏移量檢查系統1〇運行於一電腦(未 不出)中,提供一操作介面,其包括一輸入/輸出模組1〇〇、一劃分模 組102、一檢查模組1〇4及一選擇模組1〇6。 該輸入/輸出模組100,用於導入PCB (Printed Circuit Board,印刷 電路板)差分訊號線的佈線文檔,在該PCB差分訊號線的佈線文檔中 定位並用顏色標示選擇的差分訊號線區段,及將選擇的差分訊號線區 段檢查資訊以報表的方式導出來。選擇的差分訊號線區段檢查資訊包 括·選擇的區段數、選擇的各區段的實際偏移量、選擇的各區段偏移 量的合理上限值及選擇的各區段的實際偏移量與偏移量的合理上限值 的比對結果。 該劃分模組102,用於將排佈的差分訊號線劃分爲許多區段。由於 排佈的PCB差分訊號線會經過被動元件、過孔等可能造成阻抗不連續 的部分,因而排佈的PCB差分訊號線不是一個連續的整體,會有許多 不連續的區段,因而該劃分模組1〇2根據PCB差分訊號線佈線過程中 出現的阻抗不連續部分進行差分訊號線的劃分。 該檢查模組104,用於針對該劃分模組1〇2劃分的差分訊號線的每 一區段進行偏移量的檢查。具體而言,該檢查模組1〇4用於對該劃分 8 1281133 模組102劃分的每一區段進行偏移量的合理上限值的設定,根據各區 段的兩條成對的訊號線的長度計算出各區段的實際偏移量,及逐一將 各區段偏移量的合理上限值與實際偏移量進行比對並給出比對結果。 對該劃分模組102劃分的差分訊號線的各區段設定的偏移量的合理上 限值並不是統一的值,不同的區段根據其實際需要設定的偏移量的合 理上限值是不同的,例如:週邊元件擴展介面(PCIE)總線段通常偏 移量的合理上限值設定爲5mil,而串列介面(SATA)總線段通常偏移 量的合理上限值設定爲20πώ。 該選擇模組106,用於選擇該檢查模組104檢查完成的差分訊號線 區段。可以選擇所有的差分訊號線區段,亦可以選擇部分差分訊號線 區段。對於資深PCB差分訊號線佈線人員來說,其可以根據自己的經 驗來透過該選擇模組106選擇要重點查驗的區段的檢查結果。 對運用該差分訊號線偏移量檢查系統1〇以實現對差分訊號線快速 及準確的檢查的步驟,進行如下闡述。 首先’令輸入/輸出模組1〇〇導入PCB差分訊號線的佈線文檔,劃 分模組102將排佈的差分訊號線劃分爲許多區段。 接著’令檢查模組104對該劃分模組1〇2劃分的差分訊號線的每 一區段進行偏移量的檢查。 之後’令選擇模組106選擇該檢查模組104檢查完成的差分訊號 線區段,輸入/輸出模組100將選擇的差分訊號線區段檢查資訊以報表 的方式導出來。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal line inspection system and method, and more particularly to a differential signal line offset inspection system and method. ° [Prior Art] With the maturity and development of various wiring technologies for PCB (Printed Circuit Board) signal lines, in order to improve the performance of PCB signal lines, the arrangement of pcB signal lines is usually differential. The signal line is arranged in a form. Differential signals transmitted by differential signal lines are also well known for their precise timing control and higher operating speeds. • It is well known that the arrangement of differential signal lines takes the form of paired signal line parallel wiring, and the ideal arrangement of differential signal lines is that the two pairs of signal lines of the differential signal line are exactly the same, and As close as possible. In this way, the differential signals transmitted on the differential signal lines can be coupled to the maximum extent, and the disordered signals can be completely eliminated. In fact, it is impossible to realize the ideal arrangement of differential signal lines. The two pairs of signal lines of the differential signal line must have an offset, which means that people must carefully design the trend of the differential signal lines. Try to keep the offsets as much as possible within a reasonable range. At present, the way to check the offset of the arranged differential signal lines is to directly compare the total length of the two pairs of signal lines of the differential signal line. However, the differential signal line passes through passive components, vias, etc., which may cause impedance discontinuities. If the total length is compared, the error is much larger than it actually is. Avoid the inability to segment the offset of the differential signal line in stages, which helps to avoid the error caused by the overall offset of the differential signal line. SUMMARY OF THE INVENTION In the above, it is necessary to provide a differential signal line offset checking system and method for comparing the offset of the differential signal line in sections to avoid the error caused by the overall offset of the differential signal line. A differential signal line offset checking system operates in a computer. The system comprises: an input/output module for introducing a wiring document of a differential signal line of a printed circuit board; and a 61281133 sub-module for dividing the differential signal line in the differential signal wiring document of the printed circuit board into a plurality of segments; an inspection module for performing an offset check for each segment of the differential signal line divided by the dividing module. Further, the system further includes: a selection module, configured to select a differential signal line segment that is checked by the inspection module. Further, the input/output module is further configured to locate and color-select the selected differential signal line segment in the wiring document of the differential signal line of the printed circuit board, and to check the selected differential signal line segment inspection information. The way the report is exported. Further, the inspection module is further configured to set a reasonable upper limit value of the offset amount for each segment to be divided, calculate an actual offset amount of each segment, and offset each segment one by one. The reasonable upper limit of the shift is compared with the actual offset and the comparison is given. Further, the selected differential signal line segment check information includes the selected number of segments, the actual offset of the selected segments, the reasonable upper limit of the selected segment offsets, and the selected segments. The comparison of the actual offset to the reasonable upper limit of the offset. A method for checking a differential signal line offset by using a computer, comprising the steps of: (a) importing a wiring document of a printed circuit board differential signal line; (b) dividing the differential signal line in the printed circuit board differential signal line wiring document For many segments; (c) an offset check for each segment of the divided differential signal lines. Further, the method further includes the step of: qd) selecting the differential signal line segment to be checked, and (e) locating and selecting the differential signal line segment that is not selected by the color code in the wiring document of the printed circuit board differential signal line; The selected differential signal line segment check information is exported as a report. Further, the step (c) includes: (cl) setting a reasonable upper limit value of the offset for each of the divided segments, and calculating an actual offset of each segment; (c2) one by one The reasonable upper limit of the segment offset is compared with the actual offset and the comparison result is given. Compared with the prior art, the differential signal line offset checking system and method fully considers the discontinuity of the impedance caused by the differential signal line through the passive component, the via hole, etc., and avoids the partial comparison of the differential signal line. The error caused by the shift. [Embodiment] 7 1281133 Refer to the first figure, which is a schematic diagram of the differential signal transmitted by the differential signal line. The positive source differential signal A and the negative source differential signal B respectively transmitted on the paired and equal length signal lines are 180 degrees out of phase and have the same intensity value, and the chaotic signals in the positive source differential signal A and the negative source differential signal B Waiting big and in the same direction. Since the operation of the differential signal line depends on the intensity difference between the signals transmitted on the pair of two signal lines, the positive source differential signal A and the negative source differential signal B are subtracted to obtain the intensity value of the stationary signal c. It is twice the intensity value of the positive source differential signal A or the negative source differential signal B. Since the positive source differential signal a and the negative source differential signal B are 180 degrees out of phase with each other, the subtraction process of the positive source differential signal A and the negative source differential signal B is actually a process of accumulating signal intensity. The principle is like "work - (1) = 2"; and because the chaotic signals in the positive source differential signal A and the negative source differential signal B are large and in the same direction, the messy signal is cancelled. Referring to the second figure, there is shown a functional block diagram of a preferred embodiment of the differential signal line offset checking system of the present invention. The differential signal line offset checking system 1 is operated in a computer (not shown), and provides an operation interface, which includes an input/output module 1 , a dividing module 102 , and an inspection module 1 . 〇 4 and a selection module 1〇6. The input/output module 100 is configured to import a wiring document of a PCB (Printed Circuit Board) differential signal line, and locate and color-select the selected differential signal line segment in the wiring document of the PCB differential signal line. And the selected differential signal line segment check information is exported as a report. The selected differential signal line segment check information includes: the number of selected segments, the actual offset of each selected segment, the reasonable upper limit of the selected segment offset, and the actual bias of the selected segments. The result of the comparison of the shift and the reasonable upper limit of the offset. The dividing module 102 is configured to divide the arranged differential signal lines into a plurality of segments. Since the arranged PCB differential signal lines pass through passive components, vias, etc., which may cause impedance discontinuities, the arranged PCB differential signal lines are not a continuous whole, and there are many discontinuous sections, so the division The module 1〇2 divides the differential signal lines according to the discontinuous portion of the impedance that occurs during the wiring of the PCB differential signal line. The inspection module 104 is configured to perform an offset check on each segment of the differential signal line divided by the dividing module 1〇2. Specifically, the inspection module 1〇4 is configured to set a reasonable upper limit value of the offset of each segment divided by the 81281133 module 102, according to two pairs of signals of each segment. The length of the line calculates the actual offset of each segment, and compares the reasonable upper limit of each segment offset with the actual offset one by one and gives the comparison result. The reasonable upper limit of the offset set by each section of the differential signal line divided by the partitioning module 102 is not a uniform value, and the reasonable upper limit of the offset set by different sections according to actual needs is Different, for example, the Peripheral Component Expansion Interface (PCIE) bus segment typically has a reasonable upper limit of offset of 5 mils, while the serial interface (SATA) bus segment typically has a reasonable upper limit of offset of 20 π. The selection module 106 is configured to select the differential signal line segment that the inspection module 104 checks for. All differential signal line segments can be selected, or some differential signal line segments can be selected. For experienced PCB differential signal line wiring personnel, they can select the inspection result of the section to be checked by the selection module 106 according to their own experience. The steps of using the differential signal line offset checking system 1 to achieve fast and accurate inspection of the differential signal line are as follows. First, the input/output module 1 is introduced into the wiring document of the PCB differential signal line, and the division module 102 divides the arranged differential signal line into a plurality of sections. Then, the inspection module 104 performs an inspection of the offset of each segment of the differential signal line divided by the division module 1〇2. Then, the selection module 106 selects the inspection module 104 to check the completed differential signal line segment, and the input/output module 100 derives the selected differential signal line segment inspection information as a report.

參閱第三圖所示,係本發明差分訊號線偏移量檢查方法較佳實施 方式的具體實施流程圖。首先,輸入/輸出模組10〇導入PCB差分訊號 線的佈線文檔,劃分模組102根據PC]B差分訊號線佈線過程中出現的 阻抗是否連續進行差分訊號線的劃分(步驟S2〇)。然後,檢查模組1〇4 對該劃分模組102劃分的差分訊號線的每一區段進行偏移量的檢查(步 驟S22)。.之後,選擇模組1〇6選擇該檢查模組1〇4檢查完成的差分訊 號線區段(步驟S24)。輸入/輸出模組100在該PCB差分訊號線的佈 線文槽中定位並用顏色標示選擇的差分訊號線區段,即在排佈的pCB 9 1281133 差分吼號線中找出選擇模組1〇6選擇的差分訊號線區段所處的位置, 將畫面切換至該區段所處的位置,並以顏色加以標示以示區分(步驟 S26)。輸入/輸出模組1〇0將選擇的差分訊號線區段檢查資訊以報表的 方式導出來,選擇的差分訊號線區段檢查資訊包括:選擇的區段數、 選擇的各區段的實際偏移量、選擇的各區段偏移量的合理上限值及選 擇的各區段的實際偏移量與偏移量的合理上限值的比對結果(步驟 S28)。 參閱第四圖所示,係本發明針對劃分的每一區段的差分訊號線進 行偏移量檢查的流程圖。首先,檢查模組1〇4對劃分模組1〇2劃分的 每一區段進行偏移量的合理上限值的設定,並根據各區段的兩條成對 的訊號線的長度計算出各區段的實際偏移量(步驟S22〇 )。之後,檢查 模組104逐一將各區段偏移量的合理上限值與實際偏移量進行比對並 給出比對結果(步驟S222)。 參閱第五圖所示,係本發明差分訊號線偏移量檢查系統較佳實施 方式的操作介面圖。輸入/輸出模組100導入PCB差分訊號線的佈線文 檔後,産生一差分訊號線選擇區,如標示2所示;劃分模組1〇2根據 PCB差为A號線佈線過程中出現的阻抗是否連續進行差分訊號線的劃 刀後,産生一差分訊號線區段選擇區,如標示3所示;檢查模組1〇4 産生一偏移量的合理上限值設定區,如標示4所示,以對劃分模組1〇2 劃分的每一區段進行偏移量的合理上限值的設定;輸入/輸出模組1〇〇 産生一差分訊號線區段定址及標示姐,如標示5所示,以在該PCB差 分訊號線的佈線文檔中定位並用顏色標示選擇的差分訊號線區段;輸 入/輸出模組100定位並用顏色標示選擇的差分訊號線區段後,將晝面 切換至該區段所處的位置,並以顏色加以標示以示區分,如標示6所 不;檢查模組104對選擇的差分訊號線的各區段進行偏移量的檢查後, 産生k查元成的差分訊號顯不區’如標不7所不;檢查模組1〇4對 該劃分模組102劃分的差分訊號線的每一區段進行偏移量的檢查後, 輸入/輸出模組100產生一報表産生按紐,如標示8所示,以根據實際 需要導出選擇的差分訊號線區段檢查資訊或差分訊號線各區段的檢查 1281133 資訊。 本發明差分訊號線偏移量檢查系統及方法,雖以較佳實施方式揭 露如上,然其並非用以限定本發明。任何熟悉此項技藝之人士,在不 脫離本發明之精神和範圍内,當可做更動與潤飾,因此本發明之保護 範圍當視後附之申請專利範圍所界定者為準。 【圖式簡單說明】 第一圖係差分訊號線傳輸的差分訊號的示意圖。 第二圖係本發明差分訊號線偏移量檢查系統較佳實施方式的功能 模組圖。 | 第三圖係本發明差分訊號線偏移量檢查方法較佳實施方式的具體 實施流程圖。 第四圖係本發明針對劃分的每一區段的差分訊號線進行偏移量檢 查的流程圖。 第五圖係本發明差分訊號線偏移量檢查系統較佳實施方式的操作 介面圖。 【主要元件符號說明】 差分訊號線偏移量檢查系統 10 輸入/輸出模組 100 劃分模組 102 檢查模組 104 選擇模組 106 11Referring to the third figure, there is shown a specific implementation flow chart of a preferred embodiment of the differential signal line offset checking method of the present invention. First, the input/output module 10A is introduced into the wiring document of the PCB differential signal line, and the division module 102 successively divides the differential signal lines according to the impedance appearing during the wiring process of the PC]B differential signal line (step S2). Then, the inspection module 1〇4 performs an offset check on each segment of the differential signal line divided by the division module 102 (step S22). Thereafter, the selection module 1〇6 selects the inspection module 1〇4 to check the completed differential signal line segment (step S24). The input/output module 100 locates and selects the selected differential signal line segment in the routing slot of the PCB differential signal line, that is, finds the selection module 1〇6 in the arranged pCB 9 1281133 differential 吼 line. The position of the selected differential signal line segment is switched to the position where the segment is located, and is marked with a color to distinguish (step S26). The input/output module 1〇0 derives the selected differential signal line segment check information in a report manner, and the selected differential signal line segment check information includes: the selected number of segments, and the actual partiality of each selected segment. The shift amount, the reasonable upper limit value of the selected segment offset, and the comparison result of the selected actual offset of each segment and the reasonable upper limit of the offset (step S28). Referring to the fourth figure, there is shown a flow chart of the present invention for performing an offset check on the differential signal lines of each of the divided segments. First, the inspection module 1〇4 sets a reasonable upper limit value of the offset for each segment divided by the division module 1〇2, and calculates according to the length of two pairs of signal lines of each segment. The actual offset of each segment (step S22A). Thereafter, the inspection module 104 compares the reasonable upper limit value of each segment offset with the actual offset one by one and gives a comparison result (step S222). Referring to Figure 5, there is shown an operational interface diagram of a preferred embodiment of the differential signal line offset checking system of the present invention. After the input/output module 100 is introduced into the wiring document of the PCB differential signal line, a differential signal line selection area is generated, as indicated by the symbol 2; and the division module 1〇2 is the impedance generated during the wiring of the A line according to the PCB difference. After successively performing the scaling of the differential signal line, a differential signal line segment selection area is generated, as indicated by the indication 3; the inspection module 1〇4 generates a reasonable upper limit setting area of the offset, as indicated by the symbol 4 The setting of the reasonable upper limit of the offset is performed for each segment divided by the dividing module 1〇2; the input/output module 1 generates a differential signal line segment addressing and marking the sister, such as the label 5 As shown, the differential signal line segment is located and color-coded in the routing document of the PCB differential signal line; after the input/output module 100 locates and colors the selected differential signal line segment, the face is switched to The position of the section is marked with a color to distinguish it, as indicated by the flag 6; the inspection module 104 performs an offset check on each section of the selected differential signal line to generate a k-factor. The differential signal is not displayed as ' No. 7; after the inspection module 1〇4 performs an offset check on each segment of the differential signal line divided by the division module 102, the input/output module 100 generates a report generation button, such as a label. As shown in FIG. 8, the selected 1281133 information of each section of the differential signal line section inspection information or the differential signal line is derived according to actual needs. The differential signal line offset inspection system and method of the present invention are disclosed above in the preferred embodiment, but are not intended to limit the present invention. Any person skilled in the art will be able to make modifications and refinements without departing from the spirit and scope of the invention, and the scope of the invention is defined by the scope of the appended claims. [Simple diagram of the diagram] The first diagram is a schematic diagram of the differential signal transmitted by the differential signal line. The second figure is a functional block diagram of a preferred embodiment of the differential signal line offset checking system of the present invention. The third figure is a specific implementation flowchart of a preferred embodiment of the differential signal line offset checking method of the present invention. The fourth figure is a flow chart of the present invention for performing an offset check on the differential signal lines of each of the divided segments. Figure 5 is an operational interface diagram of a preferred embodiment of the differential signal line offset checking system of the present invention. [Main component symbol description] Differential signal line offset checking system 10 Input/output module 100 Partitioning module 102 Checking module 104 Selecting module 106 11

Claims (1)

1281133 十、申請專利範圍: 1· 一種差分訊號線偏移量檢查系統,運行於一電腦中,該系統包 括: 一輸入/輸出模組,用於導入印刷電路板差分訊號線的佈線文檔; 一劃分模組’用於將印刷電路板差分訊號線佈線文檔中的差分訊 號線劃分爲許多區段; 一檢查模組,用於針對該劃分模組劃分的差分訊號線的每一區段 進行偏移量的檢查。 2·如申請專利範圍第1項所述的差分訊號線偏移量檢查系統,該 I 系統還包括: 一選擇模組’用於選擇該檢查模組檢查完成的差分訊號線區段。 3·如申請專利範圍第2項所述的差分訊號線偏移量檢查系統,其 中該輸入/輸出模組還用於在該印刷電路板差分訊號線的佈線文檔中定 位並用顏色標示選擇的差分訊號線區段,及將選擇的差分訊號線區段 檢查資訊以報表的方式導出來。 4·如申請專利範圍第3項所述的差分訊號線偏移量檢查系統,其 中該檢查模組還用於對劃分的每一區段進行偏移量的合理上限值的設 定並計算出各區段的實際偏移量,及逐一將各區段偏移量的合理上限 值與貫際偏移量進行比對並給出比對結果。 • 5·如申請專利範圍第4項所述的差分訊號線偏移量檢查系統,其 中選擇的差分訊號線區段檢查資訊包括選擇的區段數、選擇的各區段 的實際偏移量、選擇的各區段偏移量的合理上限值及選擇的各區段的 實際偏移量與偏移量的合理上限值的比對結果。 6· —種利用電腦檢查差分訊號線偏移量的方法,包括如下步驟: 導入印刷電路板差分訊號線的佈線文槽; 將印刷電路板差分訊號線佈線文稽中的差分訊號線劃分爲許多區 段;. # 針對劃分的差分訊號線的每一區段進行偏移量的檢查。 7·如申請專利範圍第6項所述的差分訊號線偏移量檢查方法,該 12 1281133 方法還包括步驟: 選擇檢查完成的差分訊號線區段; 在該印刷電路板差分訊號線的佈線文檔中定位並用顏色標示選擇 的差分訊號線區段; 將選擇的差分訊號線區段檢查資訊以報表的方式導出來。 8.如申請專利範圍第6項所述的差分訊號線偏移量檢查方法,其 該針對劃分的差分訊號線的每-區段進行偏移量檢查的步驟包括: 對劃分的每-區段進行偏移频合理上限值的設定,並計算出各 的實際偏移量;1281133 X. Patent application scope: 1. A differential signal line offset checking system running in a computer, the system comprising: an input/output module for introducing a wiring document of a differential signal line of a printed circuit board; The dividing module is configured to divide the differential signal line in the printed circuit board differential signal line routing document into a plurality of sections; an inspection module is configured to bias each section of the differential signal line divided by the dividing module The inspection of the displacement. 2. The differential signal line offset checking system of claim 1, wherein the I system further comprises: a selection module </ RTI> for selecting a differential signal line segment to be checked by the inspection module. 3. The differential signal line offset checking system according to claim 2, wherein the input/output module is further configured to position and color-select the selected difference in the wiring document of the differential signal line of the printed circuit board. The signal line segment and the selected differential signal line segment check information are exported as a report. 4. The differential signal line offset checking system according to claim 3, wherein the checking module is further configured to calculate and calculate a reasonable upper limit value of the offset for each segment. The actual offset of each segment, and the reasonable upper limit of each segment offset are compared with the intersecting offset one by one and the comparison result is given. 5. The differential signal line offset checking system according to claim 4, wherein the selected differential signal line segment check information includes the selected number of segments, the actual offset of each selected segment, A reasonable upper limit of the selected segment offsets and a comparison of the actual offsets of the selected segments with a reasonable upper limit of the offset. 6. The method for checking the offset of the differential signal line by using the computer includes the following steps: importing the wiring groove of the differential signal line of the printed circuit board; dividing the differential signal line in the differential signal wiring of the printed circuit board into many Section; # # Perform an offset check for each section of the divided differential signal line. 7. The differential signal line offset checking method according to claim 6, wherein the 12 1281133 method further comprises the steps of: selecting a differential signal line segment to be inspected; routing documentation of the differential signal line on the printed circuit board The selected differential signal line segment is located and color-coded; the selected differential signal line segment check information is exported as a report. 8. The differential signal line offset checking method according to claim 6, wherein the step of performing an offset check for each segment of the divided differential signal line comprises: dividing each segment of the segment Performing the setting of the reasonable upper limit value of the offset frequency, and calculating the actual offset amount of each; ^士 ^各^段偏移量的合理上限值與實際偏移量進行比對, 出比對結果 並给^ The reasonable upper limit of the offset of each ^ segment is compared with the actual offset, and the comparison result is given 13 1281133 七、指定代表圖: ~ (一)本案指定代表圖為:第(二)圖。 (二)本代表圖之元件符號簡單說明: 差分訊號線偏移量檢查系統 10 輸入/輸出模組 100 劃分模組 102 檢查模組 104 選擇模組 10613 1281133 VII. Designated representative map: ~ (1) The representative representative of the case is: (2). (2) Brief description of the component symbols of this representative figure: Differential signal line offset checking system 10 Input/output module 100 Partitioning module 102 Checking module 104 Selecting module 106 八、本案若有化學式時,請揭示最能顯示發明特徵的化學 式:8. If there is a chemical formula in this case, please disclose the chemical formula that best shows the characteristics of the invention:
TW94144786A 2005-12-16 2005-12-16 System and method for checking offsets of a differential-mode signal line TWI281133B (en)

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