JP5321135B2 - Timing verification method and timing verification apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a timing verification method and an apparatus for the same, capable of executing timing verification on timing verification-required paths necessary for timing verification without any omission. <P>SOLUTION: The timing verification method includes: a timing verification-required path-extracting process which analyzes connection information of an integrated circuit and extracts a plurality of timing verification-required paths; a first timing analysis process which obtains signal delay-related information on the plurality of timing verification-required paths based on representative timing verification conditions including manufacturing conditions and operation conditions of the integrated circuit, and which calculates the signal delay time of the plurality of timing verification-required paths from the delay-related information to perform timing analysis of signals propagating through the plurality of timing verification-required paths; a process for inputting specific determination conditions from the plurality of timing verification-required paths; a specific path selecting process which selects some paths corresponding to the specific determination conditions as specific paths; and a second timing analysis process which performs timing analysis of signals propagating through the specific paths. <P>COPYRIGHT: (C)2010,JPO&amp;INPIT

Description

  The present invention relates to a timing verification method and timing verification apparatus for a semiconductor integrated circuit.

  Conventionally, in the development process of a semiconductor integrated circuit, in order to confirm and guarantee its operation, timing verification of a path which is a signal transmission path has been performed. In timing verification in digital circuits, static timing analysis (STA) is widely performed.

  In static timing analysis, first, a delay value (delay time) in each element (cell or wiring) constituting a logic circuit is calculated and assigned to each element. Then, the transmission delay time of the signal transmitted through the path is calculated by accumulating the assigned delay values. Further, based on the calculated transmission delay time, an analysis is performed as to whether or not the signal is transmitted at a predetermined timing.

  Also, the process of forming elements in the semiconductor integrated circuit, the power supply voltage and temperature during operation, etc. affect the delay value of each element. Therefore, these are set as analysis conditions in the calculation of the delay value of each element described above. Then, a delay value is calculated based on the analysis condition.

  Conventionally, since the timing verification of all paths of the integrated circuit is performed without exception, the range and variation of each condition are taken into consideration, and the static timing analysis is performed by changing the combination thereof. However, in this method, since analysis is performed for all paths under all conditions, the number of analysis steps increases. Therefore, first, timing verification is performed on all paths under typical conditions (hereinafter referred to as representative timing verification conditions), and conditions added only for critical paths with severe timing selected from the results ( Hereinafter, timing verification under the unique timing verification condition) is performed.

  A certain timing verification describes a method for calculating a signal delay time of a path in a logic circuit with high speed and high accuracy. First, relatively high-speed static delay calculation is performed on the paths of the logic circuit, and based on the calculation results, paths that require particularly high accuracy and paths that include elements with large errors in the calculation are extracted. Is done. Then, although it takes a relatively long time only for these extracted paths, highly accurate delay calculation is performed by circuit simulation.

  In another timing verification, first, static timing analysis is performed on a path included in a logic circuit, and a net with strict timing is extracted. Then, a delay distribution in which variation is specified for each cell of the net is calculated, and statistical timing analysis is performed based on the delay distribution.

Japanese Patent Laid-Open No. 10-63693 JP 2007-183932 JP

  However, if the timing verification is first performed under the representative timing verification conditions as in the conventional timing verification, and the timing verification under the unique timing verification conditions is performed only for the critical path with the detected timing being severe, verification failure occurs. There is a problem of doing.

  For example, a path that includes a characteristic variation cell whose delay characteristics vary greatly depending on the condition, even if there is a margin in timing in the representative timing verification condition and it is not selected as a critical path, the timing margin is specified in the specific timing verification condition May be less than the value. However, if only the timing margin obtained only with the representative timing verification condition is checked, such a critical path cannot be detected.

  Accordingly, an object of the present invention is to provide a timing verification method and apparatus capable of performing timing verification without fail for a timing verification target path that requires timing verification.

  According to one aspect, in the integrated circuit timing verification method, the computer analyzes the connection information of the integrated circuit, and includes a path having a cell and a wiring connecting the cells, and a plurality of timing verification targets The timing verification target paths are extracted, and the computer propagates a plurality of timing verification target paths to a plurality of timing verification target paths based on representative timing verification conditions including manufacturing conditions and operation conditions of the integrated circuit. The delay related information is obtained, the delay related information is associated with each timing verification target path, and the signal delay times of the plurality of timing verification target paths are obtained from the delay related information, and the signals propagating through the plurality of timing verification target paths are obtained. Performs timing analysis, and the computer selects a specific path from multiple timing verification target paths. The computer inputs a specific determination condition for selecting, and the computer selects, as the specific path, a part of paths that match the specific determination condition from a plurality of timing verification target paths associated with the delay related information. However, for a specific path, a signal delay time of the specific path is obtained based on a plurality of timing verification conditions specific to the specific path, and a timing analysis of a signal propagating through the specific path is performed.

  According to the above invention, it is possible to provide a timing verification method and apparatus capable of performing timing verification for all timing verification target paths that require timing verification.

It is a flowchart which shows the general timing verification method. It is a flowchart of static timing analysis S3. It is a flowchart which shows the timing verification method in this Embodiment. FIG. 4 is a flowchart showing input / output of information in each step S13, S36 of FIG. It is an example of a timing verification target path extracted by static timing analysis. It is an example of the timing analysis report ls1 of the data path P1. It is an example of a timing analysis report ls1 of the clock path P2. It is an example of a wiring information timing analysis report ls1. 1 is a block diagram of a timing verification device 10 in the present embodiment. It is an example of a multi-power supply circuit having a plurality of power supplies. This is a timing verification target path extracted from the multi-power supply circuit shown in FIG. It is an example of the integrated circuit which has a cell with a large slew rate value. 13 is a timing verification target path extracted from the integrated circuit shown in FIG. It is an example of the integrated circuit which has a characteristic variation cell. It is a timing verification target path extracted from the integrated circuit shown in FIG. It is an example of an integrated circuit having a path in which the number of cell stages is smaller than a predetermined number of stages. It is a timing verification target path extracted from the integrated circuit shown in FIG. It is the table | surface which showed the representative timing verification condition or the specific timing verification condition of the static timing analysis input in each specific example. It is the table | surface which showed the representative timing verification condition or the specific timing verification condition of the static timing analysis input in each specific example. It is a figure showing the range of dispersion | variation in the wiring resistance value per unit length and wiring capacitance value which are input as wiring conditions. It is a figure showing an example of the change of the delay value with respect to the change of the operating temperature of a characteristic variation cell. It is a figure concerning a variation coefficient.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. However, the technical scope of the present invention is not limited to these embodiments, but extends to the matters described in the claims and equivalents thereof.

[General timing verification method]
First, a general timing verification method will be described.

  FIG. 1 is a flowchart showing a general timing verification method. 1A and 1B in FIG. 1 are two different examples. First, the timing verification method shown in the flowchart of FIG. 1A will be described.

(Step S1)
First, in the placement and wiring processing step S1, cells and wirings that connect them are placed based on a netlist that represents the connection of the cells constituting the integrated circuit.

(Step S2)
In the wiring RC extraction step S2, the wiring resistance value and the wiring capacitance value are calculated according to the length, width, etc. of each wiring connecting the cells generated in the placement wiring processing step S1. Then, the wiring resistance value and the wiring capacitance value are stored as the wiring RC information together with the length and width of the wiring. Further, the wiring RC information may include a product of a wiring resistance value and a wiring capacitance value (hereinafter referred to as a wiring RC). In calculating the wiring resistance value and the wiring capacitance value, for example, processing such as calibration of the wiring capacitance is appropriately performed based on the capacitance parasitic on the cell.

(Step S3)
In the static timing analysis step S3, static timing analysis is performed. In static timing analysis, the delay of the signal propagated for each path that makes up the integrated circuit is calculated, and the timing is verified for each path based on the result, and critical paths and timing margins with strict timing are specified values. Paths that have become less than (hereinafter referred to as critical paths or the like) are detected. Details of the static timing analysis will be described later.

(Step S4)
It is determined whether or not the critical path detected in the static timing analysis step S3 is within the timing allowable range in circuit design. Then, if it is within the allowable range, the timing verification ends. If it exceeds the allowable range, the process proceeds to the circuit correction step S5 as necessary.

(Step S5)
In the circuit correction step S5, in order to improve the timing of a path that exceeds the allowable timing range, the net list or the like is corrected and a delay cell is added. Then, after the correction, the process is moved again to the placement and routing process step S1, and the same process is repeated thereafter.

  Next, details of static timing analysis will be described.

  FIG. 2 is a flowchart of the static timing analysis S3. In the flowchart of FIG. 2, data input / output in each step of the static timing analysis S3 is also shown.

  The verification condition j1 in FIG. 2 is a condition that is input when the static timing analysis is performed.For example, the verification condition j1 is a condition that combines manufacturing conditions (process) and operating conditions (circuit power supply voltage and operating temperature) of the integrated circuit. is there. Since each of these conditions affects the delay value of the signal propagating through the path, in the static timing analysis, a plurality of combinations taking into account changes in the actual operating environment of the integrated circuit and the like are input.

  The database db1 is input information that is appropriately read in the static timing analysis. The netlist d11 represents cells constituting the circuit and their connections. The cell characteristic library d12 records delay information of each cell. The cell delay information and the like are stored in a library according to conditions such as cell power supply voltage and operating temperature, or combinations of these conditions. In the constraint condition d14, various constraints at the time of executing the static timing analysis, such as a clock frequency, a timing analysis non-target path, a variation coefficient used for delay calculation, and the like are recorded.

  The wiring RC information d13 is data generated in the above-described wiring RC extraction step S2, and records the length, width, etc., wiring resistance value, wiring capacitance value, or wiring RC of each wiring.

  As shown in FIG. 2, the static timing analysis includes a timing verification target path extraction step S31, a timing analysis step S32, and a timing verification step S33. The path information d21, the delay related information d22, and the slack value d23 are data generated in each process.

(Step S31)
In the timing verification target path extraction step S31, all timing verification target paths to be subjected to timing verification are extracted based on the netlist d11, and path information d21 representing them is generated. That is, the path information d21 includes cell and wiring information for each extracted timing verification target path and their connection information.

(Step S32)
In the timing analysis step S32, the cell characteristic library d12 and the constraint condition d14 in the database db1 are referred to, and the delay related information d22 is calculated for each element (cell and wiring) in the timing verification target path. The delay related information d22 includes, for example, cell and wiring delay values, slew rate values, crosstalk delay values, and the like. These are associated with each element. Next, the delay value associated with each element is accumulated for each timing verification target path, and the delay time of the timing verification target path is calculated. These delay times are also associated with the corresponding timing verification target path as the delay related information d22.

(Step S33)
In the timing verification step S33, timing verification for each path is performed based on the delay time calculated in the timing analysis step S32, and a slack value d23 indicating a timing delay time is calculated. These slack values d23 are also associated with the corresponding timing verification target path as the delay related information d22. Based on this slack value, a critical path or the like is detected.

  Further, the wiring resistance value and the wiring capacitance value also affect the delay of the signal propagating through the path. Therefore, the timing verification of the signal propagating through the path may be required even when the wiring resistance value or the wiring capacitance value changes. In this case, a condition for calculating the wiring resistance value and the wiring capacitance value is given as the verification condition j1. For example, when the wiring resistance value per unit length is given as the verification condition j1, the wiring resistance value is calculated again based on the length and width of the wiring included in the wiring RC information d13.

  As described above, in the general timing verification method shown in FIG. 1A, all timing verification targets extracted in the timing verification target path extraction step S31 based on the input verification condition j1 in the static timing analysis step S3. Timing analysis is performed on the path. However, as described above, the verification condition j1 is a combination of integrated circuit manufacturing conditions, operating conditions, etc., and timing analysis based on all verification conditions j1 is performed on all timing verification target paths. Man-hours increase.

  Therefore, in order to suppress the increase in analysis man-hours, a timing verification method as shown in the flowchart of FIG. 1B has been proposed. In FIG. 1B, the same steps as those shown in FIG. 1A are denoted by the same reference numerals, and the above description will be simplified.

  In FIG. 1B, the static timing analysis is performed in the first timing analysis step S13 after the placement and routing processing step S1 and the wiring RC step S2, similarly to the processing described in FIG. 1A. Here, the difference from the static timing analysis step S3 shown in FIG. 1A is the verification condition input in the static timing analysis.

(Step S13)
In the first timing analysis step S13, timing analysis is performed on all detected timing verification target paths under verification conditions including representative conditions (representative timing conditions). The representative timing verification conditions include, for example, a combination of manufacturing conditions and operating conditions of an integrated circuit, for example, a condition that includes a combination that is assumed to be the fastest signal that propagates along the path and a combination that is assumed to be the slowest. Are referred to as boundary conditions). As manufacturing conditions and operating conditions of an integrated circuit, there are a cell operating speed, a power supply voltage, an operating temperature, a wiring RC value, and the like according to process conditions. Based on the representative timing verification condition, static timing analysis is performed to detect a critical path and the like.

  Then, similarly to FIG. 1A, it is determined whether or not the timing of the timing verification target path detected based on each of the representative timing verification conditions is within the timing allowable range in the circuit design (step S4). If it is within the allowable range, the process proceeds to the second timing analysis step S16.

(Step S16)
In the second timing analysis step S16, only the critical path determined to have a small timing margin in the first timing analysis step S13 has a verification condition (specific timing unique to each path different from the representative timing verification condition). Static timing analysis is performed based on the verification condition.

  This is because the condition input as the representative timing verification condition is generally the condition that the timing becomes stricter (hereinafter referred to as the best condition) and becomes the slowest as the boundary condition described above becomes generally faster. This is because the timing becomes severe (hereinafter referred to as the worst condition). Since these conditions are not timing verification conditions suitable for all paths, margins are small, and for paths detected as critical paths, detailed additional verification and confirmation under specific timing verification conditions are performed. is necessary. The worst condition and the best condition are a combination of the cell operating speed, the power supply voltage, the operating temperature, the wiring RC value, and the like according to the process conditions.

  Further, the timing verification target path in the second timing analysis step S16 is a critical path detected from the result of the first timing analysis step S13. Therefore, in the static timing analysis performed in the second timing analysis S16, the process in the timing verification target path extraction step S31 illustrated in FIG. 2 is not performed.

(Step S17)
As in step S4, it is determined whether or not the critical path detected in the second timing analysis step S16 is within the allowable timing range in circuit design.

  As described above, first, the first timing analysis is performed only under the representative representative timing verification conditions from the verification conditions in the static timing analysis step S3 shown in FIG. 1A. Then, the second timing analysis based on the detailed specific timing verification condition is performed only on the critical path detected as a result. Thereby, compared with the timing verification in FIG. 1A, the analysis man-hour is reduced in the timing verification in FIG. 2A.

[First embodiment]
FIG. 3 is a flowchart showing a timing verification method in the present embodiment.

  FIG. 4 is a flowchart showing input / output of information in each of steps S13 and S36 in FIG.

  In FIG. 3, the same steps as those shown in FIG. 1B are denoted by the same reference numerals. The flowchart shown in FIG. 3 differs from FIG. 1B in having step S36. Hereinafter, the timing verification method according to the present embodiment will be described with reference to FIGS.

  3 and 4, in the first timing analysis step S13, processing similar to the static timing analysis shown in FIG. 2 is performed. That is, based on the database db1 and the like, the connection information of the integrated circuit is analyzed, and all the paths to be subjected to timing verification that are the paths having the cells and the wirings that connect the cells are extracted, and these are extracted. Is generated. This timing verification target path is, for example, a data path and a clock path to a register such as a flip-flop. Then, based on the representative timing verification condition j2 which is a combination of the manufacturing conditions and operating conditions of the integrated circuit and the database db1, etc., the delay related information d22 such as the delay value and the slew rate value of the signal propagating through the timing verification target path Is generated. As described above, the delay related information d22 is associated with each timing verification target path, and the delay time of each timing verification target path is obtained based on the associated information. These delay times are also associated with the corresponding timing verification target path as the delay related information d22.

  Next, based on the calculated delay time, timing verification for each path is performed, and a slack value indicating a timing delay time is calculated. These slack values are also associated with the corresponding timing verification target path as the delay related information d22. Based on the slack value, a critical path with a small timing margin is detected.

  As described above, by performing the first timing analysis, the path information d21 and the delay related information d22 are generated and associated with each other. Specifically, for example, the path information d21 includes cell and wiring information and connection information thereof, and the delay related information d22 includes cell and wiring delay values, slew rate values, crosstalk delay values, and path delays. Time, slack value, and the like are associated with each timing verification path. In this embodiment, based on this path information d21 and delay related information d22 associated therewith (hereinafter referred to as path information d21 and delay related information d22), the identification that is the target of the second timing analysis S37. A path is selected.

  Further, the operator can output and confirm desired information from the path information d21 and the delay related information d22 stored in the computer as a timing analysis report ls1. Details of the timing analysis report ls1 will be described in a specific example of static timing analysis described later.

(Step S36)
In the specific path timing analysis step S36, the specific path determination condition j10 is input, and a part of the paths matching the specific determination condition j10 is selected as the specific path d42 from the path information d21 and the delay related information d22 described above. . For example, when the determination condition j10 is a “path including a characteristic variation cell” in which the delay value varies greatly with changes in the power supply voltage and operating temperature of the cell, the cell and wiring information included in the path information d21 described above and connection information thereof Based on the above, the path that matches the determination condition j10 is selected as the specific path d42. Similarly, for example, when the determination condition j10 is “a path including a cell having a large slew rate value”, the cell information and wiring information included in the path information d21 and the delay related information d22 described above, their connection information, and the slew rate value are used. Thus, the path that matches the determination condition j10 is selected as the specific path d42.

  Furthermore, in addition to the selection based on the path information d21 and the delay related information d22, it is also possible to select the critical path and the path whose timing margin is less than the specified value based on the slack value included in the delay related information d22. For example, in the first timing verification, it is also possible to select a path that has a timing margin that clears a specified value but is severe, as the specific path d42. Then, the detailed second timing analysis under the inherent timing analysis condition is performed on the specific path d42, and it is possible to determine whether or not the timing margin is lost.

  The determination condition j10 may be a condition in which a plurality of pieces of information included in the path information d21 and the delay related information d22 are combined.

  In the specific path timing analysis step S36, as shown in FIG. 3, first, a determination condition j10 is input (step S36a), and the above-described specific path is selected (step S36b). When the specific path d42 is detected, a timing verification condition (specific timing verification condition) specific to the specific path d42 is input (S36c), and the processing is transferred to the second timing analysis S36d for the specific path. If the specific path d42 is not detected, the timing verification ends (step S36b). Note that a corresponding unique timing verification condition may be input based on the determination condition j10. In the second timing analysis step S36d, the signal delay time of the specific path is obtained based on a plurality of timing verification conditions j3 specific to the verification of the specific path, and the static timing analysis of the signal propagating through the specific path is performed. The unique timing verification condition also has the best condition and the worst condition similarly to the above-described representative timing verification condition, but the combination of the process condition, power supply voltage, and operating temperature of these conditions is a combination specific to the specific path. For example, when the above-mentioned “path including characteristic variation cell” is selected as the specific path d42, the second timing analysis is performed under a plurality of conditions in which the power supply voltage and the operating temperature of the cell are changed as the inherent timing verification condition j3. Done. Similarly, when the above-mentioned “path including a cell having a large slew rate value” is selected as the specific path d42, the power supply voltage or operating temperature of the cell that affects the slew rate is changed as the specific timing verification condition j3. The second timing analysis is performed under a plurality of conditions.

  As described above, in the present embodiment, not only the critical path detected in the first timing analysis based on the representative conditions, but also the additional information based on the generated path information d21 and the delay related information d22. Since all the specific paths that need to be analyzed are selected, path verification leakage is avoided. Then, detailed second timing analysis is performed under conditions specific to the specific path. Therefore, it is possible to prevent a verification omission by performing timing analysis on a specific path having a timing margin that is insufficient among the verification paths for which the timing margin is determined to be sufficient according to the representative timing verification condition j2 and under a specific condition. In addition, since the number of specific paths is a small part of all the timing verification target paths, the increase in man-hours by the second timing analysis is limited.

  Next, a modification of the present embodiment will be described.

  As described above, in the present embodiment, the path information d21 and the delay related information d22 are generated by the first timing analysis. Here, the path information d21 includes cell and wiring information and their connection information. Therefore, in the specific path selection step S36b, it is possible to select the specific path d42 using only the path information d21. That is, using the cell and wiring information as the determination condition j10, it is possible to select the specific path d42 that matches the determination condition j10 from the connection information. Further, the path information d21 is generated in the timing verification target path extraction step S31 in FIG. Therefore, in the modification of the present embodiment, only the timing verification target path extraction step S31 is performed in the first timing analysis step S13.

  In this modification, since the delay related information d22 is not calculated, the information cannot be used as the determination condition j10. However, for example, from the cell and wiring information included in the path information d21, it is possible to select “a path including a specific variation cell” or the like as the determination condition j10 and to select a path that matches them as the specific path d42.

  In this case, since the timing analysis is not actually performed, it is not determined whether the timing is within the allowable range (step S4).

  As described above, in the modification of the present embodiment, for example, when a timing analysis of a path having a specific cell or wiring is required, in the first timing analysis, the path verification target path extraction step of FIG. Only S31 is performed. Then, all the paths are selected as specific paths from the path information d21 generated in the timing verification target path extraction step S31. Then, timing verification by the second timing analysis is performed only on the selected specific path.

[Specific example of static timing analysis]
Next, in order to show an example of the path information d21 and the delay related information d22 of the present embodiment, the result of concrete static timing analysis is shown below.

  In the static timing analysis, a timing verification target path is first extracted, and path information d21 indicating the path is generated.

  FIG. 5 is an example of a timing verification target path extracted by static timing analysis. This path includes flip-flops REGC and REGE, which are registers, cells I_CK1 to I_CK3, I_E0 and I_E1, wiring Clk, nck1 to nck3, and na6 to na8. A path P1 indicated by a broken line represents a data path, and a path P2 represents a clock path. Reference symbols A and Y appended to the cell represent an input terminal and an output terminal, respectively. Next, timing analysis is performed on this path, delay related information d22 is calculated, and associated with the path information d21.

  6 to 8 are diagrams in which part of the path information d21 and the delay related information d22 generated by the static timing analysis is output as the timing analysis report ls1, as shown in FIG.

  FIG. 6 is an example of the timing analysis report ls1 of the data path P1. The information output in FIG. 6 includes the fanout Fanout, the wiring capacitance Cap, the slew rate change DTrans, the slew rate Trans, the crosstalk delay Delta, and the cell corresponding to each node Point in the data path P1. The delay value Incr and the accumulated delay value Path of the path. The information in the area 6Y indicated by the broken line represents the path information d21 described above, and the information in the area 6Z represents the delay related information d22.

  Then, in the area 6Y, in accordance with the path information d21, the cell and wiring information of the node Point belonging to the data path P1 from the wiring Clk to the data input terminal D of the flip-flop REGE are described from the top in the connection order. Yes.

  “Clk (in)” represents the signal input terminal Pin of the wiring Clk. “Clk (net)” represents the wiring Clk. “I_CK1 / A (SCGFBUFCLXH1)” represents the input terminal A of the cell I_CK1, and the parenthesis represents the cell name. “REGC / CLK (SCGDFFQXH1)” represents the clock input terminal CK of the flip-flop REGC, and the parenthesis represents the register name. Others are described in the same manner.

  That is, the wiring Clk, the cell I_CK1, the wiring nck1, the flip-flop REGC, the wiring na6, the cell I_E0, the wiring na7, the cell I_E1, the wiring na8, and the flip-flop REGE, which are the nodes Point included in the data path P1 in FIG. It is described from.

  Information corresponding to each of the nodes Point is shown in the row direction. For example, the node 6h indicates the wiring Clk, and the fanout Fanout is “2” and the wiring capacitance Cap is “0.01”. Similarly, the node 6i indicates the input terminal A of the cell I_CK1, but the slew rate change DTrans related to the crosstalk there is "0", the slew rate Trans is "0.99", the crosstalk delay Delta is "0", and the cell The delay value Incr is “0.39”, and the cumulative delay value Path of the path is “0.39”.

  Thus, the path information d21 shown in the region 6Y and the delay related information d22 shown in the region 6Z are associated with each element (node Point) of the path P1. Next, the relationship between the delay value Incr for each cell and the accumulated delay value Path of the path is shown below. The signal is input from the terminal Pin of FIG. 5, where the accumulated delay value 6j is “0”. The delay value 6k “0.39” at the input terminal A of the cell I_Ck1 corresponds to the delay time of the signal propagating through the wiring Clk. The cumulative delay value 6l “0.39” is a value obtained by adding the delay value 6k “0.39” to the previous cumulative delay value 6j “0”. Further, the delay value 6m “53.91” at the output terminal of the cell I_Ck1 corresponds to a delay value unique to the cell I_CK1. The cumulative delay value 6n “54.30” is a value obtained by adding the delay value 6m “53.91” to the previous cumulative delay value 6l “0.39”. Hereinafter, similarly, the delay value Incr and the accumulated delay value Path are described in the connection order of each element of the path P1, and the accumulated delay value 6p “266.12” is the data of the flip-flop REGE from the input terminal Pin via the data path P1. It represents the propagation time of the data signal to the input terminal D.

  FIG. 7 is an example of the timing analysis report ls1 of the clock path P2. FIG. 7 shows the same information as FIG. The accumulated delay value 7a “153.64” represents the propagation time of the clock signal from the input terminal Pin to the clock input terminal CK of the flip-flop REGE via the clock path P2.

  In a region 7R indicated by a broken line in FIG. 7, the result of the timing verification based on the above-described propagation time of the data signal and the propagation time of the clock signal is shown. In this specific example, the timing verification was performed by defining the hold time for latching the preceding data signal as “0.75”. That is, after the clock signal rises, it was verified that the subsequent data signal rises with a delay of at least “0.75”.

  The delay value 7b “0.75” in FIG. 7 is a specified hold time. As the time required for latching the preceding data signal, the accumulated delay value 7a “153.64” which is the propagation time of the clock signal described above is used. Subtracted. The accumulated delay value 7c “152.89” is a subtraction value thereof, and the same accumulated delay value 7d “152.89” represents the minimum value required for the propagation time of the data signal.

  The accumulated delay value 7e (7d) `` 152.89 '' which is the minimum value required for the propagation time of this data signal and the accumulated delay value 7f (6p) `` 266.12 '' which is the propagation time of the data signal obtained in FIG. And the slack value 7g “113.23” is calculated by division. This slack value 7g represents a grace time (margin) when the hold time is defined as “0.75”. When the slack value 7g is negative, it indicates that the specified hold time of “0.75” is not ensured. That is, this timing verification target path represents that there is no timing margin.

  In the specific path selection step S36b in FIG. 3, based on the slack value, a critical path or a path having a timing margin less than a specified value is detected.

  FIG. 8 is an example of outputting the wiring information of the timing verification target path shown in FIG. 5 as the timing analysis report ls1.

  Wiring information is delimited in order from the left by “,” symbols, and output terminal OUTPIN_NAME, connection cell name CELL_INSTANCE, cell name CELL_NAME, wiring capacitance Total_Capacitance, and wiring resistance Resistance are described.

  For example, in the row of the wiring information 8g, information on the wiring na7 connected to the output terminal “Y” of the cell “I_E0” in FIG. 5 is described. That is, the wiring na7 has a wiring capacitance of “0.01” and a wiring resistance of “65.793”. It can also be seen that the cell name of the cell “I_E0” in which the wiring na7 is connected to the output terminal “Y” is “SCGBUFXH1”.

  Similarly, information on the wiring na8, the wiring nck1, the wiring nck2, the wiring nck3, and the wiring na6 is described in order from the top.

[Specific examples of equipment]
Next, an apparatus for performing timing verification will be described.

  FIG. 9 is a block diagram of the timing verification apparatus 10 in the present embodiment.

  The timing verification device 10 comprises a general CAD (Computer Aided Design) device, and has a central processing unit (hereinafter referred to as CPU) 11, a memory 12, an external storage device 13, a display device 14, an input device 15, and a drive device 16. They are connected to each other via a bus 18.

  The external storage device 13 stores programs such as an integrated circuit path search tool and timing analysis tool necessary for timing verification, and various data files such as the database db1 shown in FIG. Furthermore, the external storage device 13 also stores verification conditions j2, j3 and a discrimination condition j10 as files.

  The CPU 11 appropriately stores programs and data files stored in the external storage device 13 in the memory 12, and sequentially reads them to execute processing. In addition, the CPU 11 stores data such as path information d21 and delay related information d22 that are created along with the execution of the program in the external storage device 13. Alternatively, the CPU 11 temporarily stores these data in the memory 12 and reads them appropriately according to the processing.

  The display device 14 is used to display a timing verification screen, a parameter input screen, and the like.

  The input device 15 is used for inputting requests, instructions, and parameters from an operator. The verification conditions j2 and j3 and the determination condition j10 described above are read from the external storage device 13, but are input from the input device 15 when the operator inputs them manually.

[Specific example of this embodiment]
FIGS. 10 to 19 below show specific examples of the timing verification method in the present embodiment.

  18 and 19 are tables showing representative timing verification conditions or specific timing verification conditions for static timing analysis input in each specific example. Each chart will be described as appropriate in the specific examples shown below. Further, as a timing verification procedure, the flowchart of FIG. 4 is referred to as appropriate.

[Multiple power circuit]
In recent semiconductor integrated circuits, a multi-power supply configuration may be employed to reduce power consumption. In such a case, more detailed additional verification by changing the power supply voltage is required for a specific path such as a path crossing the power supply. Thus, in the present embodiment, the procedure for verifying the timing of the multi-power supply circuit is shown below.

  FIG. 10 is an example of a multiple power supply circuit having a plurality of power supplies. The multi-power supply circuit of FIG. 10 has two different power supply regions G1 and G2, and the flip-flops FF1 and FF3 are arranged in the first power supply region G1, and the flip-flop FF2 is arranged in the second power supply region G2, which are different. Level shifter cells LS1, LS2 are arranged at the boundary between the power supply regions G1, G2. The voltages applied to the flip-flops FF1 to FF3 disposed in the respective power supply regions G1 and G2 correspond to the power supply voltages to the power supply regions G1 and G2 provided respectively. A path indicated by a solid line represents a data path, and a path indicated by a broken line represents a clock path. In operation, the power supply voltage G1 is applied to the power supply region G1, and the power supply voltage V2 is applied to the power supply region G2.

  A chart 18A1 illustrated in FIG. 18 is an example of the representative timing verification condition j2 input in the first timing analysis. The leftmost column of the chart 18A1 represents the initial condition. From the left, a process condition column, a power supply voltage condition column, an operating temperature condition column, and a wiring RC condition column are listed.

  The process condition is a process variation at the time of manufacturing the integrated circuit, and at the same time represents the operation speed of the cell. When the process condition is bad, the operation speed of the transistor or cell is slow, and when the process condition is good, the operation speed is fast. That is, “Slow” shown in the process condition column means that the operation speed of the cell in which the timing analysis is performed is slow, and a delay value corresponding to the cell is selected from the cell property library d11. Similarly, “Fast” means a case where the operation speed of the cell is fast.

  In the column of the power supply voltage condition, the power supply voltages of the first power supply regions G1 and G2 in which the cells are arranged are described. The chart 18A1 also describes each cell disposed in each power supply region G1, G2. As described above, a voltage corresponding to the power supply region G1, G2 is applied to each cell. . Further, “Vmin” and “Vmax” in the column of the power supply voltage condition are the minimum power supply voltage and the maximum power supply voltage expected within the range of variations in the power supply voltage due to malfunctions and disturbances assumed during actual operation of the circuit.

  The column of the operating temperature condition represents a temperature at the time of operation of the circuit, and “Low” and “High” are a case where the temperature is low and a case where it is high in a range of variation of the operating temperature assumed at the time of operation.

  The column of the wiring RC condition represents the product of the wiring resistance value and the wiring capacitance value per unit length. “RCmin” and “RCmax” are the minimum value and the maximum value within the variation range of the product of the wiring resistance value and the wiring capacitance value.

  Note that the value of the wiring RC condition may not be directly input as the timing verification condition, but may be indirectly obtained from a file in which the value of the wiring RC prepared in advance in the cell characteristic library d11 or the like is described. For example, this file has wiring RC values corresponding to combinations of process conditions, power supply voltage conditions, and operating temperature conditions, and corresponds to combinations of process conditions, power supply voltage conditions, and operating temperature conditions that are input as timing verification conditions. Thus, the value of the wiring RC condition may be determined.

  In this specific example, boundary conditions are used for the representative timing conditions A1 and A2. That is, the representative timing verification condition A1 is a combination (best condition) that is assumed to be the fastest speed of the signal propagating through the path, and the representative timing verification condition A2 is a combination (worst condition) that is assumed to be the slowest. is there.

  The representative timing condition A1 is the process “Slow”, the power supply voltage “Vmin”, the operating temperature “High”, and the wiring RC “RCmax”. The information for calculating the delay related information d22 corresponding to this condition is stored in the database db1. It is read from the cell property library d11 or the like. For example, a file that summarizes the delay values of cells corresponding to the process “Slow”, the power supply voltage “Vmin”, and the operating temperature “High” exists in the cell property library d11, and the file is read. The same applies to the representative timing condition A2.

  In the first timing analysis, the operating voltage input under the representative timing verification conditions A1 and A2 is a value that takes into account assumed variations including malfunctions as described above. Also, in the first timing analysis, if the power supply voltages applied to the power supply regions G1 and G2 are distinguished, the conditions increase and the number of analysis steps increases, so the power supply voltage is uniformly set to `` Vmax '' or `` Vmin ''. It is unified.

  In the first timing analysis step S13, first, a timing verification target path included in the multi-power supply circuit shown in FIG. 10 is extracted.

  FIG. 11 is a timing verification target path extracted from the multi-power supply circuit shown in FIG. The multi-power supply circuit shown in FIG. 10 has two timing verification target paths shown in FIGS. 11A and 11B. Then, timing analysis based on the above-described representative timing verification conditions A1 and A2 is performed on each of these paths, and the delay related information d22 calculated at that time is related to each path. Then, in the representative timing verification conditions A1 and A2, it is verified whether each path is within the timing allowable range.

  In step S36a in which the specific path determination condition is input, “path including level shifter cell” is input as the determination condition j10. Accordingly, only the path that crosses the power supply in FIG. 11A matches the determination condition j10 and is selected as the specific path d42. At that time, the cell information of the path information d21 generated in the timing verification target path extraction step S31 of the first timing analysis is referred to.

  Then, the second timing analysis based on the unique timing verification condition is performed only on the selected specific path d42. In other words, detailed additional verification is performed only for paths that cross the power supply.

  The chart 18A2 represents an example of the specific timing verification condition j3 input in the second timing analysis. In the power supply voltage conditions of the inherent timing verification conditions A3 and A4, the voltages applied to the power supply regions G1 and G2 are the voltages V1 and V2 during operation of the integrated circuit. Then, the process conditions, the operating temperature conditions, and the wiring RC conditions are set as boundary conditions similar to the representative timing verification conditions A1 and A2. As a result, it is possible to verify to what extent the variation of the process, the operating temperature, and the wiring RC affects the timing in the voltages V1 and V2 during the actual operation of the integrated circuit.

  Furthermore, the unique timing verification conditions A5 to A12 are conditions assuming variations in the voltages V1 and V2 applied to the power supply regions G1 and G2. When the power supply voltage V1 varies in the range of “V1min” to “V1max” and the power supply voltage V2 is assumed to vary in the range of “V2min” to “V2max”, the maximum and minimum values of each are combined, and the four conditions Exists. These four conditions are combined with process conditions, operating temperature conditions, and wiring RC conditions similar to the representative timing verification conditions A1 and A2. In this specific example, in the specific timing verification conditions A5 to A8, it is assumed that the other conditions are combinations of conditions that are expected to have the strictest timing, and in the specific timing verification conditions A9 to A12, it is assumed that there is a margin in timing. A combination of conditions. As a result, more detailed timing verification can be performed in consideration of voltage fluctuations actually assumed during operation of the integrated circuit.

  Then, a second timing analysis is performed based on these unique timing verification conditions A3 to A12, and whether or not each path is within the timing allowable range is verified based on the unique timing verification conditions A5 to A12.

  When performing timing verification of a multi-power supply circuit, there are paths including level shifter cells among paths that are not detected as critical paths or the like in the first timing analysis based on the representative timing verification conditions A1 and A2. In the present embodiment, those undetected paths are selected as the specific path d42. Then, more detailed additional timing analysis is performed under conditions specific to the path.

[Circuit having a cell with a large slew rate value]
FIG. 12 is an example of an integrated circuit having cells with a large slew rate value. The integrated circuit shown in FIG. 12 includes flip-flops FF1 to FF3 and cells c1 to c11, and a solid data path and a broken clock path are input to the registers FF2 and FF3. The slew rate of the signal input to the cell affects the path delay time. Therefore, a path having a cell with a large slew rate value may be detected as timing marginless depending on a timing verification condition unique to the path, and detailed timing verification is required. Therefore, by providing a limit value for the slew rate value, a path having cells exceeding the limit value is detected as a specific path d42 from the result of the first timing analysis, and a second unique to the specific path d42 is detected. The timing verification is performed.

  A chart 18B illustrated in FIG. 18 represents an example of the representative timing verification condition j2 input in the first timing analysis. The power supply voltage condition shown in the chart 18B represents the power supply voltage applied to the flip-flops FF1 to FF3 and the other cells c1 to c11, and the other conditions are the same as in the chart 18A1. That is, the representative timing verification condition 18B represents a boundary condition.

  Then, in the first timing analysis step S13, first, a timing verification target path included in the integrated circuit of FIG. 12 is extracted.

  FIG. 13 shows a timing verification target path extracted from the integrated circuit shown in FIG. As illustrated in FIGS. 13A and 13B, the integrated circuit illustrated in FIG. 12 includes two timing verification target paths. Then, timing analysis based on the above-described representative timing verification conditions B1 and B2 is performed on each of these paths, and the delay related information d22 calculated at that time is related to each path. The slew rate value is included in the delay related information d22, for example, as indicated by the slew rate value Trans of the timing report ls1 in FIG.

  On the input terminal side of each cell in FIG. 13, changes r11 to r17 of the rising edge of the signal are described based on the slew rate value Trans on the input terminal side included in the delay related information. From FIG. 13, it can be seen that the slew rate r8 of the cell c6 is large. Although the slew rate value on the input terminal side of the cell is referred to, the slew rate value on the output terminal side of the cell included in the delay related information d22 may be referred to.

  In step S36a in which a specific path determination condition is input, “path having a cell whose slew rate value exceeds the limit value” is input as the determination condition j10. Then, the slew rate value Trans of the delay related information d22 generated in the first timing analysis is referred to, and only the path shown in FIG. 13A having the cell c6 whose input slew rate value exceeds the limit value is determined as the determination condition j10. It matches and is selected as the specific path d42. The

  The slew rate value is affected by the power supply voltage, operating temperature, and wiring RC. Therefore, in the unique timing verification condition j3, the combination thereof is changed.

  The chart 18C represents an example of the specific timing verification condition j3 input in the second timing analysis. The inherent timing verification conditions C1 and C2 are conditions in which the power supply voltage conditions of the representative timing verification conditions B1 and B2 are interchanged. Similarly, the specific timing verification conditions C3 and C4 are conditions in which the operating temperature conditions of the representative timing verification conditions B1 and B2 are interchanged, and the specific timing verification conditions C5 and C6 are the wiring RC conditions of the representative timing verification conditions B1 and B2. It is the condition which replaced.

  Then, detailed additional verification by the second timing verification is performed on the path shown in FIG. 13A based on these unique timing verification conditions j3.

  In addition, as described above, the second timing analysis based on the unique timing verification condition j3 in which the conditions are individually replaced is performed, so that each condition indicates the slew rate value of the cell c6 and the path delay shown in FIG. You can verify how much it affects time. Further, the additional timing verification may be performed by adjusting the specific timing verification condition based on the result.

  Then, in the unique timing verification conditions C1 to C6, verification is performed as to whether or not the path shown in FIG. 13A is within the allowable timing range.

  As described above, in the present embodiment, as a result of the first timing analysis based on the representative timing verification condition j2, a path having a cell whose slew rate value exceeds the limit value is not detected as a critical path or the like. Selected as path d42. Then, the second timing verification is performed on the specific path d42 under specific detailed conditions, so that verification failure is avoided.

[Circuit with wiring with large wiring capacitance or wiring resistance]
The wiring resistance value and the wiring capacitance value affect the delay value of the signal propagating through the wiring. For example, the larger the wiring resistance value and the wiring capacitance value, the larger the delay value. A wiring having a large wiring resistance and wiring capacitance value is typified by a long wiring or a wiring having many branches, but a long wiring has a large change in delay value with respect to a change in wiring resistance value and wiring capacitance value. Furthermore, the slew rate of a signal propagating through a wiring having a long wiring resistance value and wiring capacitance value is deteriorated. As a result, the delay value of the subsequent cell is affected.

  For this reason, a path with wiring having a large wiring resistance value and wiring capacitance value typified by a long wiring may be detected as timing marginless depending on the timing verification conditions specific to the path. Required. Therefore, by providing limit values for the wiring resistance value and the wiring capacitance value of the path, the path having the wiring exceeding the limit value is detected as the specific path d42 from the result of the first timing analysis, and the specific path d42 A unique second timing verification is performed on.

  This specific example will be described with reference to FIG.

  As an example of the representative timing verification condition j2, a chart 19D1 shown in FIG. 19 is used. The influences of changes in the wiring resistance value and the wiring capacitance value on the delay value are different. Therefore, a wiring resistance value and a wiring capacitance value per unit length are input as wiring conditions.

  FIG. 20 is a diagram illustrating a range of variation in the wiring resistance value and the wiring capacitance value per unit length input as the wiring condition. The horizontal axis represents the wiring resistance value, and the vertical axis represents the wiring capacitance value. The wiring resistance value varies in the range from the minimum value “Rmin” to the maximum value “Rmax” shown on the horizontal axis. Then, the wiring capacitance value per unit length varies within the range of the minimum value “Cmin (R)” to the maximum value “Cmax (R)” for each wiring resistance value “R” within the range.

  In addition, in wiring per unit length, there is a correlation between the wiring resistance value and the wiring capacitance value. Generally, the wiring capacitance value decreases as the wiring resistance value increases, and conversely, the wiring capacitance value decreases as the wiring resistance value decreases. Becomes larger. In FIG. 20, the correlation is taken into consideration, and the range surrounded by the points K1 to K4 in FIG. 20 is represented as the range of variation in the wiring resistance value and the wiring capacitance value per unit length.

  Here, “Cmin (R)” represents the minimum value of the wiring capacitance value at the wiring resistance value “R”, and “Cmax (R)” represents the maximum value thereof. The same applies to the capacitance value indicated on the vertical axis. For example, “Cmax (Rmin)” represents the maximum value of the wiring capacitance when the wiring resistance value takes the minimum value “Rmin”.

  Next, the wiring conditions input in the timing verification will be described based on FIG. The signal propagating through the wiring is slow when both the wiring resistance value and the wiring capacitance value are large, and conversely, when both are small, the signal is fast. However, there is the above-mentioned correlation between the wiring resistance value and the wiring capacitance value, and the worst wiring condition is that the wiring resistance value shown in FIG. 20 is the maximum value `` Rmax '' and the wiring capacitance value is the maximum value `` Cmax (Rmin) ''. There is no case. Similarly, as the best wiring conditions, the wiring resistance value is the minimum value “Rmin” and the wiring capacitance value is the minimum value “Cmin (Rmin)”. Therefore, the wiring resistance values and wiring capacitance values at points K1 to K4 in FIG. And Here, the conditions of points K1 and K3 represent the worst conditions, and points K2 and K4 represent the best conditions.

  Point K1 (Rmin, Cmax (Rmin)) indicates that the wiring resistance value per unit length is the smallest within the range of variations in the wiring resistance value and wiring capacitance value of the above-described wiring, and among these, the unit length This represents the case where the wiring capacitance value per unit is the maximum. That is, it represents the worst condition when the wiring capacitance value is maximum.

  Similarly, the point K3 (Rmax, Cmax (Rmax)) represents the case where the wiring resistance value per unit length is the maximum, and among them, the wiring capacitance value per unit length is the maximum. That is, it represents the worst condition when the wiring resistance value is the maximum.

  A point K2 (Rmax, Cmin (Rmax)) represents a case where the wiring resistance value per unit length is the maximum, and among them, the wiring capacitance value per unit length is the minimum. That is, it represents the best condition when the wiring capacitance value is minimum.

  Point K4 (Rmin, Cmin (Rmin)) represents a case where the wiring resistance value per unit length is the smallest, and the wiring capacitance value per unit length is the smallest among them. That is, it represents the worst condition when the wiring resistance value is minimum.

  As described above, the worst conditions are points K1 and K3, the best conditions are points K2 and K4, but the representative timing verification condition j2 is, for example, point K1 as the worst condition and point K2 as the best condition empirically. The Then, the delay values of all the wirings are calculated uniformly at the points K1 and K2. That is, as shown in the representative timing verification condition j2 in Chart 19D1, the wiring resistance value and wiring shown at point K1 (Rmin, Cmax (Rmin)) as the worst condition D1 and at point K2 (Rmax, Cmin (Rmax)) as the best condition D2 Use the capacitance value.

  In the first timing analysis step S13 shown in the flowchart of FIG. 3, it is assumed that a timing verification target path is detected and two timing verification target paths shown in FIGS. 13A and 13B are detected. Then, the resistance value and the capacitance value of each wiring included in each path are calculated and assigned based on the wiring conditions of the representative timing verification conditions D1 and D2. Here, the wiring L1 connecting the cell c2 and the cell c6 in FIG. 13A is long and has a large wiring capacitance value and wiring resistance value. The timing analysis based on the representative timing verification conditions D1 and D2 described above is performed for each of these paths, and the delay related information d22 calculated at that time is related to each path.

  In step S36a in which the specific path determination condition is input, “path having a wiring whose wiring resistance value or wiring capacitance value exceeds the limit value” is input as the determination condition j10. Then, the wiring information in the path information d21 generated in the timing verification target path extraction step S31 of the first timing analysis is referred to, and the wiring L1 has the wiring L1 whose wiring resistance value or wiring capacitance value exceeds the limit value shown in FIG. 13A. The path matches the determination condition j10 and is selected as the specific path d42.

  The chart 19D2 represents an example of the specific timing verification condition j3 input in the second timing analysis.

  The wiring information input under the specific timing verification conditions D3 and D4 is the point K3 of the other worst condition and the point K4 of the best condition, which are different from the points K1 and K2 of the representative timing verification conditions D1 and D2. That is, the unique timing verification condition D3 is “Rmax, Cmax (Rmax)” at the point K3 as the worst condition. The unique timing verification condition D4 is “Rmin, Cmin (Rmin)” at point K4 as the best condition.

  Then, additional verification by the second timing verification is performed on the path shown in FIG. 13A based on these unique timing verification conditions j3.

  The reason is that the first timing analysis is performed at the wiring condition points K1 and K2 input under the representative timing verification conditions D1 and D2, and the path where the wiring resistance value and the wiring capacitance value exceed the limit values is the specific path d42. Selected as. The specific path d42 is a path having a wiring whose change in delay value is particularly large with respect to a change in wiring conditions, such as a long wiring. As described above, the wiring conditions (points K1 and K2) input under the representative timing verification conditions D1 and D2 are conditions that are empirically assumed to be low speed and high speed. It should be verified that the specific path d42 having a large wiring is not timing marginless by performing an analysis under the other condition (points K3 and K4). Therefore, the worst condition indicated by the point K3 and the best condition indicated by the point K4 are input as the wiring conditions of the specific timing verification conditions D3 and D4, and the second timing verification based on these conditions is performed for the specific path d42. Is called.

  Further, with respect to the specific path d42 selected in the specific path selection step S36b, for example, the wiring resistance value and the wiring capacitance value at any one point and a plurality of points on the solid line of the points K1 to K3 and the points K4 to K2. Additional verification may be performed by selecting a combination.

  As described above, in the present embodiment, as a result of the first timing analysis based on the representative timing verification condition j2, there is a wiring that is not detected as a critical path or the like, but whose wiring resistance and wiring capacitance value exceed the limit values. The path is also selected as the specific path d42. Then, the second timing verification is performed on the specific path d42 under specific detailed conditions, so that verification failure is avoided.

[Circuit with characteristic variation cell]
First, the characteristic variation cell will be described.

  FIG. 21 is a diagram illustrating an example of a change in the delay value with respect to a change in the operating temperature of the characteristic variation cell. Graphs Gp1 and Gp2 in FIG. 21 represent changes in delay values with respect to changes in operating temperature when different power supply voltages V1 and V2 are applied to a certain characteristic variation cell. As a characteristic of the characteristic variation cell, first, the change of the delay value with respect to the change of the power supply voltage and the operating temperature is large. Furthermore, in the characteristic variation cell, as shown in FIG. 21, in the case of a certain power supply voltage V1, the delay value increases monotonously according to the change in the operating temperature, but in the case of another different power supply voltage V2, the change in the operating temperature. Some delay values have a monotonically decreasing characteristic. Thus, the characteristic variation cell has a large signal delay value depending on the power supply voltage and temperature variation, and may vary irregularly.

  FIG. 14 is an example of an integrated circuit having a characteristic variation cell. The integrated circuit shown in FIG. 14 has flip-flops FF1 to FF3, characteristic variation cells c12 and c13, and other cells c1 to c11, and a solid data path and a broken clock path are input to registers FF2 and FF3. ing. As described above, the characteristic variation cell has a large signal delay value depending on the power supply voltage and the operating temperature of the cell, and may vary irregularly. For this reason, a path having a characteristic variation cell may be detected as timing marginless depending on a timing verification condition unique to the path, and detailed timing verification is required. Therefore, the path having the characteristic variation cell is detected as a specific path d42 from the result of the first timing analysis, and the specific second timing verification is performed for the specific path d42.

  As an example of the representative timing verification condition j2, the same boundary condition as in the chart 18B shown in FIG. 18 described above is used.

  In the first timing analysis step S13, first, a timing verification target path is detected.

  FIG. 15 is a timing verification target path extracted from the integrated circuit shown in FIG. As shown in FIGS. 15A and 15B, the integrated circuit shown in FIG. 14 has two timing verification target paths.

  Then, timing analysis based on the above-described representative timing verification conditions B1 and B2 is performed on each of these paths, and the delay related information d22 calculated at that time is related to each path. Then, it is verified whether or not each path is within the allowable timing range.

  In step S36a in which the specific path determination condition is input, “path having characteristic variation cell” is input as the determination condition j10. Then, the cell information of the path information d21 generated in the timing verification target path extraction step S31 of the first timing analysis is referred to, and only the path shown in FIG. 15A having the characteristic variation cells c12 and c13 matches the discrimination condition j10. Then, it is selected as the specific path d42.

  As described above, the characteristic variation cell has characteristics different from those of a general cell, and the power supply voltage and the operating temperature of the cell affect the delay time. Therefore, in the unique timing verification condition j3, the combination thereof is changed.

  The chart 19E represents an example of the specific timing verification condition j3 input in the second timing analysis. The inherent timing verification conditions E1 and E2 are conditions in which the power supply voltage conditions of the representative timing verification conditions B1 and B2 are interchanged. Similarly, the specific timing verification conditions E3 and E4 are conditions in which the operating temperature conditions of the representative timing verification conditions B1 and B2 are interchanged.

  That is, as shown in the representative timing verification conditions B1 and B2, a general cell tends to have a longer delay as the power supply voltage is lower and the operating temperature is higher, and a delay is smaller as the power supply voltage is higher and the operating temperature is lower. However, unlike the above, the characteristic variation cell may have a larger delay as the power supply voltage is lower, and may increase as the operating temperature is lower.

  In this way, by performing the second timing analysis based on the unique timing verification condition j3 in which the conditions are individually switched, each result is changed to the characteristic variation cells c12 and c13 and the path delay time shown in FIG. You can verify how much it affects. Further, the additional timing verification may be performed by adjusting the specific timing verification condition based on the result.

  Then, the second timing verification is performed on the path shown in FIG. 15A based on the unique timing verification conditions E1 to E4.

  As described above, in the present embodiment, as a result of the first timing analysis based on the representative timing verification condition j2, it is not detected as a critical path or the like, but a path having a characteristic variation cell is selected as a specific path d42. Then, the second timing verification is performed on the specific path d42 under specific detailed conditions, so that verification failure is avoided.

[Circuits with limited number of cell stages]
In static timing analysis, each cell is assigned a delay value calculated based on the cell characteristic library d11. At this time, the delay value associated with variations in the operation speed, operation voltage, operation temperature, etc. Variations are taken into account. For example, a value obtained by integrating the variation coefficient with respect to the average value of the delay values is assigned as the delay value of the cell corrected in consideration of the variation.

  FIG. 22 is a diagram related to the variation coefficient. The path Pq in FIG. 22A includes n-stage cells c1 to c (n) between the input terminal Qin and the output terminal Qout. Then, delay values including variations (hereinafter referred to as distribution delay values) B1 to Bn obtained based on variations in operation speed and the like accompanying the process are written in the corresponding cells c1 to c (n). Has been.

  In the distribution delay values B1 to Bn, the horizontal axis represents the delay value, the vertical axis represents the establishment, and is represented by a normal distribution having the center value μ and the standard deviation σ. The central value μ represents the average delay value with the highest probability calculated based on the cell characteristic library d11, and the variation width Sg is the width of the delay value corresponding to 3σ with respect to the standard deviation σ. , “Μ + Sg” represents the maximum delay value, and “μ-Sg” represents the minimum delay value. When static timing analysis is performed without correcting the delay value due to the variation coefficient, when analyzing with a large delay, the maximum value “μ + Sg” is assigned to each cell, and an analysis with a small delay is performed. When doing so, the minimum value “μ-Sg” is assigned to each cell.

  FIG. 22B shows an example of the case where the static timing analysis is performed without correcting the delay value based on the variation coefficient. The distribution delay value B_v is a delay value including variation at the output terminal Qout obtained by simply accumulating the distribution delay values B1 to Bn of the n-stage cells and the delay values assigned to the wiring between them. The variation width Sg_v is calculated by Sg_v = n × Sg.

  On the other hand, the distributed delay value B_r represents a variation in the delay value at the output terminal Qout obtained by obtaining a delay value of a signal propagated through a cell having a certain number of stages or more by a highly accurate simulation or actual measurement. As shown in FIG. 22B, the variation width Sg_r is smaller than the variation width Sg_v obtained by accumulating the variation width Sg assigned to each cell. Because when the delay value of each cell varies around the center value μ, the delay value of each cell is larger or smaller than the center value μ, but those delay values are accumulated in multiple stages, This is because these large and small variations are offset. Furthermore, if the number of stages is equal to or greater than a certain number, the variation width Sg_r is statistically substantially the same value.

  Therefore, in a path having a plurality of stages of cells, the variation coefficient is added to the cell center value μ in order to bring the variation width Sg_v obtained by simply accumulating the variation width Sg of each cell closer to the actual variation width Sg_r. Values are assigned as cell delay values taking into account variation.

  In the following, the relationship between the variation coefficient and the center value μ is shown based on a specific example, and timing verification when the variation coefficient is used will be described.

  FIG. 16 is an example of an integrated circuit having a path in which the number of cell stages is smaller than a predetermined number of stages. The integrated circuit shown in FIG. 16 includes flip-flops FF1 to FF3 and other cells c1 to c14, and a solid data path and a broken clock path are input to the registers FF2 and FF3.

  A chart 19F1 illustrated in FIG. 19 represents an example of the representative timing verification condition j2 input in the first timing analysis of this specific example. The representative timing verification condition F1 is the worst condition, and the representative timing verification condition F2 is the best condition. The rightmost column of the chart 19F1 shows variation coefficients a1 and a2 used for correcting the delay value of the cell in the first timing verification.

  Here, in FIG. 22, the average value (Sg_r / n) obtained by dividing the realistic variation width Sg_r by the number of cell stages n is defined as the variation width “Sg_a” of each cell c1 to c (n). Then, the following formulas are established for the variation coefficients a1 and a2 and the center value μ.

a1 × μ = μ + Sg_a
a2 × μ = μ-Sg_a
That is, a value obtained by averaging the actual variation width Sg_r is set as the variation width Sg_a of each cell. Then, the variation coefficients a1 and a2 are added to the center value μ of the delay value, whereby the maximum value “μ + Sg_a” or the minimum value “μ−Sg_a” of the variation is calculated. Then, they are assigned as delay values of the cells corrected in consideration of variation. Conversely, by using the variation coefficients a1 and a2 based on the distribution delay value B_r defined as described above, the delay value assigned to the cell is corrected, and the output terminal Qout obtained by accumulating these values is used. The variation width of the distribution delay value is close to the actual variation width Sg_r.

  In the above equation, the variation coefficient a1 (> 1) corresponds to the worst condition in which the cell delay value increases, and the variation coefficient a2 (<1) corresponds to the best condition in which the cell delay value decreases.

  The variation coefficients a1 and a2 are values calculated based on the actual variation width Sg_r obtained in advance by measurement or the like under a specific condition and a specific number of cell stages (in this specific example, the number of cell stages “4”). For example, it is described in the constraint condition d14 of the database db1. Then, an appropriate value is read based on the combination of the representative timing verification conditions F1 and F2.

  In the present embodiment, the variation coefficients a1 and a2 of the representative timing verification conditions F1 and F2 shown in the chart 19F1 are uniformly used for all the cells when the delay values assigned to the cells are corrected.

  However, as described above, the variation coefficient is calculated based on the fact that the variation width Sg_r is statistically almost the same value when the number of stages of cells connected to the path is a certain number or more. . Therefore, when the number of cells arranged in the path is small, the delay value of the cell is not appropriately corrected. As a result, a path having a path with a small number of cell stages may be erroneously detected as a path with sufficient timing. That is, when the delay value is appropriately corrected with a more appropriate variation coefficient, there is a possibility that the timing margin is detected.

  Therefore, from the result of the first timing analysis using the variation coefficients a1 and a2, a path having a path with a small number of cell stages is detected as a specific path d42, and the appropriate path corresponding to the number of cell stages for the specific path d42 is detected. A unique second timing verification is performed using a large variation coefficient.

  In the first timing analysis step S13, first, a timing verification target path is detected.

  FIG. 17 is a timing verification target path extracted from the integrated circuit shown in FIG. As illustrated in FIGS. 17A and 17B, the integrated circuit illustrated in FIG. 16 includes two timing verification target paths.

  The first timing analysis based on the representative timing verification conditions F1 and F2 described above is performed for each of these paths, and the delay related information d22 calculated at that time is related to each path.

  In this specific example, it is assumed that the variation coefficients a1 and a2 appropriately correct the delay values of the cells when the number of cells in the path is 4 or more. Then, in step S36a in which the specific path determination condition is input, “path having a route with a cell stage number of less than 4” is input as the determination condition j10. Then, the path information d21 cell and wiring connection information obtained in the timing verification target path extraction step S31 of the first timing analysis is referred to, and the figure includes a path W1 with a cell number of 1 that includes only one cell c6. The path shown in 17A matches the determination condition j10 and is selected as the specific path d42.

  The chart 19F2 represents an example of the specific timing verification condition j3 input in the second timing analysis.

  As described above, the variation coefficients a1 and a2 used in the first timing verification condition appropriately correct the delay values of the cells when the number of cell stages included in the path is 4 or more. For this reason, the delay value of the cell c6 arranged in the path W1 having the number of cell stages is not appropriately corrected. Therefore, inherent variation coefficients b1 and b2 that appropriately correct the delay value of the cell c6 are used. That is, the difference between the specific timing verification conditions F3 and F4 and the representative timing verification conditions F1 and F2 is that the variation coefficients b1 and b2 for correcting the delay value of the cell c6 are input uniquely. In the second timing analysis, proper variation coefficients b1 and b2 unique to the cell c6 are used, and for the other cells, the variation coefficients a1 and f1 are the same as the first timing verification conditions F1 and F2. a2 is used.

  As described above, in the present embodiment, in the first timing analysis, an inappropriate variation coefficient is used for correcting the delay value of some cells, and it may be erroneously detected as a path with sufficient timing. A specific path is also selected as the specific path d42 by limiting the number of cell stages. Then, in the second timing analysis, by using appropriate variation coefficients b1 and b2 specific to some of the cells, accurate timing analysis is performed, and verification failure is avoided.

  In this specific example, the same value is used for all the cells for this variation coefficient, but different values may be used for the data path and the clock path.

  Next, a modification of timing verification using the above-described variation coefficient will be described.

  In the timing verification method described above, the variation coefficient is also used in the second timing analysis. The variation coefficient is a value calculated based on the averaging of variation in delay values related to a certain number of stages of cells. Further, since these are used for a plurality of cells, variation is set for each cell. Less accurate than statistical timing analysis.

  Therefore, in this modification, highly accurate timing analysis is performed by statistical timing analysis in the second timing analysis. Statistical timing analysis is used in the second timing analysis that is performed only on the selected specific path d42 because the analysis time is longer compared to the analysis using the variation coefficient in order to perform more accurate analysis. It is desirable.

  In the statistical timing analysis, based on the combination of the conditions input as the process conditions of the inherent timing verification conditions, the power supply voltage conditions, etc., the distribution delay values (center value μ and standard deviation σ) including the variation described in FIG. Assigned to each cell. Based on the distribution delay value assigned to each of these cells, the cumulative delay value is calculated by the Monte Carlo method or the approximation method. The details of the statistical timing analysis are described in, for example, Patent Document 2.

  In this specific example, when the above description is repeated with reference to FIG. 17A, first, distributed delays corresponding to the process conditions of the specific timing verification conditions 20F3 and 20F4, the power supply voltage conditions, etc., to each of the cells c1 to c6 and the flip-flop FF1 A value is assigned. Then, the distribution delay value at the data input terminal D of the flip-flop FF2 is calculated by the Monte Carlo method or the approximation method based on the distribution delay value assigned to the cell c1, the flip-flop FF1, and the cell 6. Similarly, the distributed delay value at the clock input terminal CK of the flip-flop FF2 is calculated based on the distributed delay value assigned to the cells c2 to c5. Then, based on the calculated distribution delay value at the input terminals D and CK of the flip-flop FF2, the distribution of slack values is calculated. Then, for example, it is determined whether or not the center value of the distribution of the slack value is within the timing allowable range.

As described above, in the present modification, only the specific path d42 that may be detected as the selected critical path or the like is performed, and the detection accuracy is increased by performing a more accurate statistical timing analysis. Analysis man-hours are reduced.
The above embodiment is summarized as follows.

(Appendix 1)
In the integrated circuit timing verification method,
A timing analysis target path extracting step in which the computer analyzes the connection information of the integrated circuit and extracts a plurality of timing verification target paths which are paths having the cells and wirings connecting the cells;
A step of inputting a specific determination condition for the computer to select a specific path from the plurality of timing verification target paths;
A specific path selection step in which a computer selects, as a specific path, a part of paths that match the specific determination condition from the plurality of timing verification target paths;
A specific path timing analysis step in which the computer performs a timing analysis of a signal propagating through the specific path by obtaining a signal delay time in the specific path based on a plurality of timing verification conditions specific to the specific path for the specific path And
The timing verification method, wherein the specific determination condition is a condition related to the cell or the wiring.

(Appendix 2)
In the integrated circuit timing verification method,
A timing analysis target path extracting step in which the computer analyzes the connection information of the integrated circuit and extracts a plurality of timing verification target paths which are paths having the cells and wirings connecting the cells;
A computer obtains delay related information of a signal propagating through the plurality of timing verification target paths based on representative timing verification conditions including manufacturing conditions and operation conditions of the integrated circuit for the plurality of timing verification target paths. In addition, associating the delay related information with each of the timing verification target paths, obtaining signal delay times of the plurality of timing verification target paths from the delay related information, and performing timing analysis of signals propagating through the plurality of timing verification target paths A first timing analysis step of performing
A step of inputting a specific determination condition for the computer to select a specific path from the plurality of timing verification target paths;
A specific path selection step in which the computer selects, as a specific path, a part of paths that match the specific determination condition from the plurality of timing verification target paths associated with the delay related information;
A second timing analysis step in which the computer obtains a signal delay time of the specific path based on a plurality of timing verification conditions unique to the specific path and performs timing analysis of a signal propagating through the specific path with respect to the specific path And a timing verification method.

(Appendix 3)
The timing verification method according to appendix 2, wherein the specific determination condition is a condition related to the cell, wiring, or delay related information.

(Appendix 4)
The timing verification according to appendix 3 or 3, wherein the second timing analysis step is performed not only on the specific path but also on a timing verification target path whose timing margin is less than a specified value in the first timing analysis step. Method.

(Appendix 5)
The timing verification target path is disposed in a plurality of divided power supply areas, and includes a path having a level shifter cell at a boundary between different power supply areas,
In the representative timing verification condition, the power supply voltage of the cell disposed in each power supply region is the same,
The specific determination condition is to include a level shifter cell as a condition for the cell,
4. The timing verification method according to supplementary note 3, wherein the power supply voltage of the cell disposed in each power supply region is different according to each power supply region under the inherent timing verification condition.

(Appendix 6)
The plurality of power supply areas are first and second areas,
The representative timing verification condition includes a first condition in which the voltage in the first and second regions is a first voltage, and a second condition in which the voltage in the first and second regions is higher than the first voltage. Having a second condition of a voltage of
The inherent timing verification condition includes a third condition in which the voltage in the first region is the third voltage, and the voltage in the second region is the fourth voltage, and the voltage in the first region is the voltage in the first region. The timing verification method according to appendix 6, wherein the fifth voltage is higher than the third voltage, and the voltage in the second region is a fourth condition that is a sixth voltage higher than the fourth voltage.

(Appendix 7)
The representative timing verification condition is a combination of at least a cell operating speed, a cell power supply voltage, a cell operating temperature, and a product of a wiring resistance value and a wiring capacitance value, wherein the first operating speed, A first condition having a power supply voltage of 1, a first operating temperature, a product of a first wiring resistance value and a wiring capacitance value, a second operating speed faster than the first operating speed, and the A second power supply voltage higher than the first power supply voltage; a second operating temperature lower than the first operating temperature; and a second wiring smaller than a product of the first wiring resistance value and the wiring capacitance value Having a second condition having a product of a resistance value and a wiring capacitance value;
The specific determination condition includes a cell in which a slew rate value of a cell input signal or output signal exceeds a limit value as a condition related to the delay related information,
The inherent timing verification conditions are the first and second conditions, the third and fourth conditions in which the first and second drive voltages are switched, and the first and second operating temperatures are switched. 4. The timing verification method according to appendix 3, wherein the fifth and sixth conditions and any of seventh and eighth conditions in which a product of the first and second wiring resistance values and the wiring capacitance values are interchanged.

(Appendix 8)
The representative timing verification condition is a combination of at least a cell operating speed, a cell power supply voltage, a cell operating temperature, a wiring resistance value, and a wiring capacitance value, wherein the first operating speed, A first condition having a power supply voltage, a first operating temperature, a first wiring resistance value, and a first wiring capacitance value; a second operating speed that is faster than the first operating speed; A second power supply voltage higher than the first power supply voltage; a second operating temperature lower than the first operating temperature; a second wiring resistance value greater than the first wiring resistance value; Having a second condition having a second wiring capacitance value smaller than the wiring capacitance value of 1,
The specific determination condition is to include a wiring whose wiring resistance value or wiring capacitance value exceeds a limit value as a condition related to the wiring;
The inherent timing verification condition includes a third condition having the second wiring resistance value, a third wiring capacitance value larger than the second wiring capacitance value, the first wiring resistance value, 4. The timing verification method according to appendix 3, which has a fourth condition having a fourth wiring capacitance value smaller than the first wiring capacitance value.

(Appendix 9)
The representative timing verification condition is a combination of at least a cell operating speed, a cell power supply voltage, a cell operating temperature, and a product of a wiring resistance value and a wiring capacitance value, wherein the first operating speed, A first condition having a power supply voltage of 1, a first operating temperature, a product of a first wiring resistance value and a wiring capacitance value, a second operating speed faster than the first operating speed, and the A second power supply voltage higher than the first power supply voltage; a second operating temperature lower than the first operating temperature; and a second wiring smaller than a product of the first wiring resistance value and the wiring capacitance value Having a second condition having a product of a resistance value and a wiring capacitance value;
The specific determination condition is to include a specific cell whose delay characteristic changes with respect to a change in power supply voltage and operating temperature of the cell as a condition regarding the cell,
The inherent timing verification conditions are the first and second conditions, the third and fourth conditions in which the first and second power supply voltages are switched, and the first and second operating temperatures. The timing verification method according to supplementary note 3, wherein the timing verification method has any one of the fifth and sixth conditions.

(Appendix 10)
In the first timing analysis step, the delay time assigned to each cell is corrected based on the first variation coefficient regardless of the number of cells in the path that the path has,
The specific determination condition is a path having a route in which the number of cell stages is less than or equal to a limit value,
The timing verification according to supplementary note 3, wherein in the second timing analysis step, a delay time of a cell existing in the path is corrected based on a second variation coefficient corresponding to the number of cells in the path of the specific path. Method.

(Appendix 11)
In the first timing analysis step, the delay time assigned to each cell is corrected based on the first variation coefficient regardless of the number of cells in the path that the path has,
The specific determination condition is a path having a route in which the number of cell stages is less than or equal to a limit value,
In the second timing analysis step, a statistical delay time is assigned to each cell of the specific path, and a delay time is calculated by a Monte Carlo method or an approximation method based on the delay time including the variation. The timing verification method according to appendix 3, wherein timing analysis is performed.

(Appendix 12)
In the integrated circuit timing verification program,
Timing verification target path extraction procedure for analyzing a connection information of an integrated circuit and extracting a plurality of timing verification target paths, which are paths having cells and wirings connecting the cells,
A procedure for inputting a specific determination condition for selecting a specific path from the plurality of timing verification target paths;
A specific path selection procedure for selecting, as a specific path, a part of the paths that match the specific determination condition from the plurality of timing verification target paths;
For the specific path, a specific path timing analysis procedure is performed for obtaining a signal delay time in the specific path based on a plurality of timing verification conditions specific to the specific path and performing timing analysis of a signal propagating through the specific path. ,
The specific determination condition is a computer-readable timing verification program that is a condition related to the cell or the wiring.

(Appendix 13)
In the integrated circuit timing verification program,
Timing verification target path extraction procedure for analyzing a connection information of an integrated circuit and extracting a plurality of timing verification target paths, which are paths having cells and wirings connecting the cells,
For the plurality of timing verification target paths, delay related information of signals propagating through the plurality of timing verification target paths is obtained based on representative timing verification conditions including manufacturing conditions and operating conditions of the integrated circuit, and the delays Relating related information to each of the timing verification target paths, obtaining signal delay times of the plurality of timing verification target paths from the delay related information, and performing timing analysis of signals propagating through the plurality of timing verification target paths 1 timing analysis procedure,
A procedure for inputting a specific determination condition for selecting a specific path from the plurality of timing verification target paths;
A specific path selection procedure for selecting, as a specific path, some paths that match the specific determination condition from the plurality of timing verification target paths associated with the delay related information;
For the specific path, a second timing analysis procedure for performing a timing analysis of a signal propagating through the specific path by obtaining a signal delay time of the specific path based on a plurality of specific timing verification conditions specific to the specific path is executed. A computer-readable timing verification program.

(Appendix 14)
In a timing verification apparatus that performs path timing verification in an integrated circuit,
Timing verification target path extracting means for analyzing connection information of an integrated circuit and extracting a plurality of timing verification target paths that are targets of timing verification, which are paths having cells and wirings connecting the cells;
Means for inputting a specific determination condition for selecting a specific path from the plurality of timing verification target paths;
Specific path selection means for selecting, as a specific path, a part of paths that match the specific determination condition from the plurality of timing verification target paths;
Specific path timing analysis means for determining the signal delay time in the specific path based on a plurality of timing verification conditions specific to the specific path and analyzing the timing of the signal propagating through the specific path with respect to the specific path. And
The timing verification apparatus, wherein the specific determination condition is a condition related to the cell or the wiring.

(Appendix 15)
In a timing verification apparatus that performs path timing verification in an integrated circuit,
Timing verification target path extracting means for analyzing connection information of an integrated circuit and extracting a plurality of timing verification target paths that are targets of timing verification, which are paths having cells and wirings connecting the cells;
For the plurality of timing verification target paths, delay related information of signals propagating through the plurality of timing verification target paths is obtained based on representative timing verification conditions including manufacturing conditions and operating conditions of the integrated circuit, and the delays Relating related information to each of the timing verification target paths, obtaining signal delay times of the plurality of timing verification target paths from the delay related information, and performing timing analysis of signals propagating through the plurality of timing verification target paths 1 timing analysis means,
Means for inputting a specific determination condition for selecting a specific path from the plurality of timing verification target paths;
Specific path selection means for selecting, as a specific path, a part of paths that match the specific determination condition from the plurality of timing verification target paths associated with the delay related information;
Second timing analysis means for performing timing analysis of a signal propagating through the specific path by obtaining a signal delay time of the specific path based on a plurality of specific timing verification conditions specific to the specific path with respect to the specific path; A timing verification device.

S1: Place and route processing step S2: Route RC extraction step S3: Static timing analysis step
S5: Circuit correction step S13: First timing analysis step S16, S37d: Second timing analysis step S31: Timing verification target path extraction step S36: Specific path timing analysis step
d11 to d14: Cell property library, etc. ls1: Timing analysis report
j2: Representative timing verification condition j3: Specific timing verification condition j10: Discrimination condition
10: Timing verification device FF1 to FF3: Flip-flop c1 to c (n): Cell

Claims (7)

In the integrated circuit timing verification method,
Timing verification target path extraction step in which a computer analyzes connection information of an integrated circuit and extracts a plurality of timing verification target paths that are cells and wirings connected to the cells. When,
A computer obtains delay related information of a signal propagating through the plurality of timing verification target paths based on representative timing verification conditions including manufacturing conditions and operation conditions of the integrated circuit for the plurality of timing verification target paths. In addition, associating the delay related information with each of the timing verification target paths, obtaining signal delay times of the plurality of timing verification target paths from the delay related information, and performing timing analysis of signals propagating through the plurality of timing verification target paths A first timing analysis step of performing
A step of inputting a determination condition of a specific path for the computer to select a specific path from the plurality of timing verification target paths;
A specific path selection step in which the computer selects, as a specific path, a part of paths that match the determination condition of the specific path from the plurality of timing verification target paths associated with the delay related information;
The computer is performed on the selected specific path, the timing analysis of said specified path seeking signal delay time of the particular path based on the unique plurality of timing verification condition signal propagating through the specific path have a and 2 of the timing analysis step,
The timing verification target path is disposed in a plurality of divided power supply areas, and includes a path having a level shifter cell at a boundary between different power supply areas,
In the representative timing verification condition, the power supply voltage of the cell disposed in each power supply region is the same,
The determination condition of the specific path is to include a level shifter cell as a condition regarding the cell,
A timing verification method, wherein a plurality of timing verification conditions unique to the selected specific path are such that the power supply voltages of the cells arranged in the respective power supply regions differ corresponding to the respective power supply regions. In the integrated circuit timing verification method,
Timing verification target path extraction step in which a computer analyzes connection information of an integrated circuit and extracts a plurality of timing verification target paths that are cells and wirings connected to the cells. When,
A computer obtains delay related information of a signal propagating through the plurality of timing verification target paths based on representative timing verification conditions including manufacturing conditions and operation conditions of the integrated circuit for the plurality of timing verification target paths. In addition, associating the delay related information with each of the timing verification target paths, obtaining signal delay times of the plurality of timing verification target paths from the delay related information, and performing timing analysis of signals propagating through the plurality of timing verification target paths A first timing analysis step of performing
A step of inputting a determination condition of a specific path for the computer to select a specific path from the plurality of timing verification target paths;
A specific path selection step in which the computer selects, as a specific path, a part of paths that match the determination condition of the specific path from the plurality of timing verification target paths associated with the delay related information;
The computer obtains a signal delay time of the specific path based on a plurality of timing verification conditions specific to the specific path, and performs timing analysis of a signal propagating through the specific path for the selected specific path. 2 timing analysis steps,
The representative timing verification condition is a combination of at least a cell operating speed, a cell power supply voltage, a cell operating temperature, a product of a wiring resistance value and a wiring capacitance value, wherein the first operating speed, A first condition having a power supply voltage of 1, a first operating temperature, a product of a first wiring resistance value and a wiring capacitance value, a second operating speed higher than the first operating speed, A second power supply voltage higher than the first power supply voltage; a second operating temperature lower than the first operating temperature; and a second wiring smaller than a product of the first wiring resistance value and the wiring capacitance value A second condition having a product of a resistance value and a wiring capacitance value;
The determination condition of the specific path is to include a cell in which a slew rate value of a cell input signal or output signal exceeds a limit value as a condition related to the delay related information,
The plurality of timing verification conditions unique to the selected specific path include third and fourth conditions in which the first and second power supply voltages are switched in the first and second conditions, and the first And the fifth and sixth conditions in which the second operating temperature is switched, and the seventh and eighth conditions in which the products of the first and second wiring resistance values and the wiring capacitance values are switched. A timing verification method characterized by the above. In the integrated circuit timing verification method,
Timing verification target path extraction step in which a computer analyzes connection information of an integrated circuit and extracts a plurality of timing verification target paths that are cells and wirings connected to the cells. When,
A computer obtains delay related information of a signal propagating through the plurality of timing verification target paths based on representative timing verification conditions including manufacturing conditions and operation conditions of the integrated circuit for the plurality of timing verification target paths. In addition, associating the delay related information with each of the timing verification target paths, obtaining signal delay times of the plurality of timing verification target paths from the delay related information, and performing timing analysis of signals propagating through the plurality of timing verification target paths A first timing analysis step of performing
A step of inputting a determination condition of a specific path for the computer to select a specific path from the plurality of timing verification target paths;
A specific path selection step in which the computer selects, as a specific path, a part of paths that match the determination condition of the specific path from the plurality of timing verification target paths associated with the delay related information;
The computer obtains a signal delay time of the specific path based on a plurality of timing verification conditions specific to the specific path, and performs timing analysis of a signal propagating through the specific path for the selected specific path. 2 timing analysis steps,
The representative timing verification condition is a combination of a wiring resistance value and the wiring capacitance value, the first wiring resistance, and the first condition having a first wiring capacitance value, the first wiring resistance A second condition having a second wiring resistance value larger than the first wiring capacitance value and a second wiring capacitance value smaller than the first wiring capacitance value;
The determination condition of the specific path is that the wiring resistance value or the wiring capacitance value of the wiring exceeds a limit value,
In a plurality of timing verification conditions specific to the selected specific path, a third condition having the second wiring resistance value and a third wiring capacitance value larger than the second wiring capacitance value; A timing verification method, comprising: a fourth condition having the first wiring resistance value and a fourth wiring capacitance value smaller than the first wiring capacitance value. In the integrated circuit timing verification method,
  Timing verification target path extraction step in which a computer analyzes connection information of an integrated circuit and extracts a plurality of timing verification target paths that are cells and wirings connected to the cells. When,
  A computer obtains delay related information of a signal propagating through the plurality of timing verification target paths based on representative timing verification conditions including manufacturing conditions and operation conditions of the integrated circuit for the plurality of timing verification target paths. In addition, associating the delay related information with each of the timing verification target paths, obtaining signal delay times of the plurality of timing verification target paths from the delay related information, and performing timing analysis of signals propagating through the plurality of timing verification target paths A first timing analysis step of performing
  A step of inputting a determination condition of a specific path for the computer to select a specific path from the plurality of timing verification target paths;
  A specific path selection step in which the computer selects, as a specific path, a part of paths that match the determination condition of the specific path from the plurality of timing verification target paths associated with the delay related information;
  The computer obtains a signal delay time of the specific path based on a plurality of timing verification conditions specific to the specific path, and performs timing analysis of a signal propagating through the specific path for the selected specific path. 2 timing analysis steps,
  The representative timing verification condition is a combination of at least a cell power supply voltage and a cell operating temperature, and includes a first condition having a first power supply voltage and a first operating temperature, and the first power supply. A second condition having a second power supply voltage higher than the voltage and a second operating temperature lower than the first operating temperature;
  The determination condition of the specific path is to include a specific cell whose delay characteristic changes irregularly with respect to a change in power supply voltage and operating temperature of the cell,
  The plurality of timing verification conditions unique to the selected specific path include third and fourth conditions in which the first and second power supply voltages are switched in the first and second conditions, and the first And a fifth and sixth condition in which the second operating temperature is switched. In the integrated circuit timing verification program,
Analyzing connection information of the integrated circuit, a path having a cell and a wiring connected to the cell, and extracting a plurality of timing verification target paths to be subjected to timing verification;
For the plurality of timing verification target paths, delay related information of signals propagating through the plurality of timing verification target paths is obtained based on representative timing verification conditions including manufacturing conditions and operating conditions of the integrated circuit, and the delays Relating related information to each of the timing verification target paths, obtaining signal delay times of the plurality of timing verification target paths from the delay related information, and performing timing analysis of signals propagating through the plurality of timing verification target paths 1 timing analysis procedure,
A procedure for inputting a specific path determination condition for selecting a specific path from the plurality of timing verification target paths;
A specific path selection procedure for selecting, as a specific path, a part of paths that match the determination condition of the specific path from the plurality of timing verification target paths associated with the delay related information;
With respect to the selected specific path, the specific path to the second performing timing analysis of the signal propagating through the specific path seeking signal delay time of the particular path based on the unique plurality of unique timing verification condition Run the timing analysis procedure,
The timing verification target path is disposed in a plurality of divided power supply areas, and includes a path having a level shifter cell at a boundary between different power supply areas,
In the representative timing verification condition, the power supply voltage of the cell disposed in each power supply region is the same,
The determination condition of the specific path is to include a level shifter cell as a condition regarding the cell,
A timing verification program in which a power supply voltage of a cell arranged in each power supply area can be read by a different computer corresponding to each power supply area under a plurality of timing verification conditions unique to the selected specific path . In the integrated circuit timing verification program,
  Analyzing connection information of the integrated circuit, a path having a cell and a wiring connected to the cell, and extracting a plurality of timing verification target paths to be subjected to timing verification;
  For the plurality of timing verification target paths, delay related information of signals propagating through the plurality of timing verification target paths is obtained based on representative timing verification conditions including manufacturing conditions and operating conditions of the integrated circuit, and the delays Relating related information to each of the timing verification target paths, obtaining signal delay times of the plurality of timing verification target paths from the delay related information, and performing timing analysis of signals propagating through the plurality of timing verification target paths 1 timing analysis procedure,
  A procedure for inputting a specific path determination condition for selecting a specific path from the plurality of timing verification target paths;
  A specific path selection procedure for selecting, as a specific path, a part of paths that match the determination condition of the specific path from the plurality of timing verification target paths associated with the delay related information;
  A second analysis is performed on the selected specific path based on a plurality of specific timing verification conditions specific to the specific path to obtain a signal delay time of the specific path and perform timing analysis of a signal propagating through the specific path. Run the timing analysis procedure,
  The representative timing verification condition is a combination of at least a cell operating speed, a cell power supply voltage, a cell operating temperature, a product of a wiring resistance value and a wiring capacitance value, wherein the first operating speed, A first condition having a power supply voltage of 1, a first operating temperature, a product of a first wiring resistance value and a wiring capacitance value, a second operating speed higher than the first operating speed, A second power supply voltage higher than the first power supply voltage; a second operating temperature lower than the first operating temperature; and a second wiring smaller than a product of the first wiring resistance value and the wiring capacitance value A second condition having a product of a resistance value and a wiring capacitance value;
  The determination condition of the specific path is to include a cell in which a slew rate value of a cell input signal or output signal exceeds a limit value as a condition related to the delay related information,
  The plurality of timing verification conditions unique to the selected specific path include third and fourth conditions in which the first and second power supply voltages are switched in the first and second conditions, and the first And the fifth and sixth conditions in which the second operating temperature is switched, and the seventh and eighth conditions in which the products of the first and second wiring resistance values and the wiring capacitance values are switched. A computer-readable timing verification program. In the integrated circuit timing verification program,
  Analyzing connection information of the integrated circuit, a path having a cell and a wiring connected to the cell, and extracting a plurality of timing verification target paths to be subjected to timing verification;
  For the plurality of timing verification target paths, delay related information of signals propagating through the plurality of timing verification target paths is obtained based on representative timing verification conditions including manufacturing conditions and operating conditions of the integrated circuit, and the delays Relating related information to each of the timing verification target paths, obtaining signal delay times of the plurality of timing verification target paths from the delay related information, and performing timing analysis of signals propagating through the plurality of timing verification target paths 1 timing analysis procedure,
  A procedure for inputting a specific path determination condition for selecting a specific path from the plurality of timing verification target paths;
  A specific path selection procedure for selecting, as a specific path, a part of paths that match the determination condition of the specific path from the plurality of timing verification target paths associated with the delay related information;
  A second analysis is performed on the selected specific path based on a plurality of specific timing verification conditions specific to the specific path to obtain a signal delay time of the specific path and perform timing analysis of a signal propagating through the specific path. Run the timing analysis procedure,
  The representative timing verification condition is a combination of a wiring resistance value and a wiring capacitance value, and includes a first condition having a first wiring resistance value and a first wiring capacitance value, and the first wiring resistance. A second condition having a second wiring resistance value larger than the first wiring capacitance value and a second wiring capacitance value smaller than the first wiring capacitance value;
  The determination condition of the specific path is that the wiring resistance value or the wiring capacitance value of the wiring exceeds a limit value,
  In a plurality of timing verification conditions specific to the selected specific path, a third condition having the second wiring resistance value and a third wiring capacitance value larger than the second wiring capacitance value; A computer-readable timing verification program comprising a fourth condition having the first wiring resistance value and a fourth wiring capacitance value smaller than the first wiring capacitance value.

Images