JP2009163490A - Timing adjustment method of integrated circuit and computer program - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a timing adjustment method, capable of correcting timing error in consideration of influence on all paths in an integrated circuit, and a computer program therefor. <P>SOLUTION: The timing adjustment method includes correcting timing error in each path of the integrated circuit by inserting a buffer cell to each cell constituting the path. At that time, sensitivity information showing the degree of influence on a slack that is a tolerance for a timing regulation for each path is provided for each cell. The timing error is corrected using the sensitivity information. According to this, the timing error can be corrected with consideration of the influence on a path free from timing error (MET path). Consequently, induction of a path with timing error (error path) can be prevented. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to timing adjustment of integrated circuits. In particular, the present invention relates to timing ECO processing for correcting a timing error in each path of an integrated circuit by inserting a buffer cell into a cell (a delay element, hereinafter referred to as a cell) constituting the path.

  In integrated circuit layout, signal timing is taken into account. The layout tool corrects and improves circuit delay in static timing analysis (hereinafter referred to as STA). There are a setup time and a hold time in the static timing of a signal, and both timing specifications need to be satisfied. As a result of the STA, it is determined whether or not the timing regulation is satisfied. If the timing rule is not satisfied, the timing error is corrected in the timing Engineering Change Order (hereinafter referred to as “timing ECO”).

  FIG. 1 is a diagram for explaining the setup time and the hold time. As shown in FIG. 1A, generally, an integrated circuit is decomposed into a path including several stages of circuit cells between flip-flops FF1 and FF2. Generally, a circuit cell includes a buffer, an inverter, a logic gate, and the like. In the path shown in FIG. 1A, the flip-flop FF2 takes in the data Data output from the output Q of the flip-flop FF1 from the input D through the buffer cell. The data Data is fetched by the flip-flop FF2 in response to the rising edge of the clock CLK.

  FIG. 1B shows a timing chart of fetching data Data by the flip-flop FF2. The setup time ST is between the time when the data Data is determined and the rising edge of the clock CLK. The hold time HT is between the rising edge of the clock CLK and the end of the data Data. It is necessary that the setup time ST and the hold time HT be equal to or more than a predetermined value determined from the characteristics of the flip-flop FF2.

  For example, when the clock CLK is delayed with respect to the data Data as shown in FIG. 1C, the time from the rising edge of the clock CLK to the end of the data Data is shortened. If the hold time HT is less than the specified value, a hold error occurs.

  In that case, the delay buffer cell B1 is inserted between the output Q of the FF1 and the input D of the FF2, as shown in FIG. The hold time HT is ensured by delaying the timing of the data Data by the insertion of the delay buffer cell B1 and matching it with the timing of the clock CLK.

  However, when the setup time ST has no margin, the setup time ST is shortened as shown in FIG. 1 (e) by inserting the delay buffer cell B1. As a result, the setup time ST may not reach the specified value and a setup error may occur.

  Patent Document 1 discloses a technique related to the timing ECO.

JP 2003-162556 A

  On the other hand, the signal delay factor considered in the design of the integrated circuit is greatly influenced by statistical factors such as manufacturing variations due to the recent miniaturization of the integrated circuit process. Therefore, a technique for statistically handling circuit delay in STA has been proposed. For example, Patent Documents 2 and 3.

JP 2006-268479 A JP 2004-252831 A

  At timing ECO, a new setup error may occur due to the insertion of a delay buffer cell for correcting a hold error as described above. In the background art disclosed in Patent Document 1 described above, a hold error is corrected by inserting a delay buffer cell in a data path so that a timing error does not occur due to a plurality of timing constraints while referring to a setup time margin. .

  However, for example, when delay buffer cells are inserted before and after a cell having a large driving ability among cells constituting a path, the delay may be larger than expected. Then, as a result of correcting a hold error in one path, a setup error may be induced in another path. Due to the effect of correcting a timing error of a certain path, a path without a timing error (hereinafter referred to as a MET path) becomes a path with a timing error (hereinafter referred to as an error path).

  Also, Patent Documents 2 and 3 do not disclose means for dealing with the above problem by statistically handling circuit delays.

  The present invention has been proposed in view of the above problems. An object of the present invention is to provide a timing adjustment method capable of correcting a timing error in consideration of the influence on all paths in an integrated circuit, and a computer program therefor.

  The timing adjustment method according to the present invention corrects a timing error in each path of an integrated circuit by inserting a buffer cell into a cell constituting the path. In order to solve the above-described problems and achieve the object, in the timing adjustment method according to the present invention, sensitivity information indicating the degree of influence on slack, which is a margin for the timing specification, is provided for each cell for each path. A timing error is corrected using this sensitivity information.

The computer program according to the present invention relates to information processing based on a physical property or a technical property such as signal timing in a physical or technical object called an integrated circuit, and is a technical program using a natural law. It belongs to the creation of thought.
The computer program concerning this invention makes a computer perform the process with which said timing adjustment method is provided.

  Thereby, it is possible to correct the timing error in consideration of the influence on the MET path. Therefore, error path induction can be prevented. Sensitivity information, which is the degree of influence on slack, is provided for each cell for each path, so it is possible to specify at which position the delay buffer cell should be inserted. Further, since the cells where error paths are concentrated can be known from the sensitivity information, the timing error can be corrected by reducing the number of inserted delay buffer cells.

  According to the integrated circuit timing adjustment method and the computer program thereof according to the present invention, the timing error can be corrected in the integrated circuit in consideration of the influence on all paths.

  With reference to FIG. 2, sensitivity information provided for each cell in each path of the integrated circuit in the integrated circuit timing adjustment method according to the present invention will be described. An example will be described with reference to the path shown in FIG. FIG. 2A shows a data path P1 used as a line for data Data and a clock path P2 used as a line for clock CLK. Each path is configured with several buffer cells. For example, buffer cells B1 to B4 are provided in the path P1 between the flip-flops FF1 and FF2.

  Each of the cells such as the buffer cells B1 to B4 constituting the path has a delay distribution as shown in FIG. 2B, for example. FIG. 2B is a statistical representation of the delay variation due to various delay variation factors such as manufacturing variation, temperature, and power supply voltage as a probability distribution of delay. Here, μ represents an average value, and σ represents a standard deviation.

  When there is a timing error in the data path P1, in the timing correction at the timing ECO, for example, the buffer cell B2 is changed from a cell having the delay distribution 1 to a cell having the delay distribution 2 as shown in FIG. . In the example of FIG. 2C, m1 and m2 are called mean values, and s1 and s2 are called sigma values. Specifically, for example, m1 and m2 are given by the average value μ of the delay distributions 1 and 2, respectively, and s1 and s2 are μ-3σ for the delay distributions 1 and 2, respectively, that is, 3 times the standard deviation from the average value. It is given as the subtracted value.

  FIG. 2D shows a distribution of slack (a hold time margin in this example) that is a margin with respect to the timing specification of the data path P1. The slack (hold time margin) distribution of the data path P1 is calculated from the delay distribution of each cell of the buffer cells B1 to B4 constituting the data path P1. For example, when the buffer cell B2 is changed from the delay distribution 1 to the delay distribution 2 as shown in FIG. 2C, the slack (hold time margin) of the data path P1 is changed from the slack distribution 1 as shown in FIG. It changes to slack distribution 2. In the example of FIG. 2D, mp1 and mp2 are called mean values, and sp1 and sp2 are called sigma values. Specifically, as in FIG. 2C, for example, mp1 and mp2 are given by the average value μ of the slack distributions 1 and 2, respectively, and sp1 and sp2 are μ −3σ, that is, the average for the slack distributions 1 and 2, respectively. The value is given by subtracting 3 times the standard deviation from the value.

  As shown in FIGS. 2C and 2D, the slack (hold time margin) of the data path P1 is increased by changing the delay distribution of the buffer cell B2. That is, by inserting a buffer cell having the delay distribution 2 before or after the cell of the buffer cell B2, the slack (hold time margin) of the data path P1 is improved and the timing error is corrected.

  Sensitivity information indicates the degree of influence that path slack is affected by the insertion of a buffer cell into a cell constituting a path in correcting a timing error. The sensitivity information includes a mean value sensitivity and a sigma value sensitivity. For example, in the examples of FIGS. 2C and 2D, the mean value sensitivity SmB2 of the buffer cell B2 satisfies mp2 = mp1 + SmB2 (m2−m1). The sigma value sensitivity SsB2 of the buffer cell B2 satisfies sp2 = sp1 + SsB2 (s2-s1). That is, the mean value sensitivity is a change rate of the mean value in the slack distribution of the target path when the mean value in the delay distribution of the cells constituting the path is slightly corrected (for example, 1 [ps]). The sigma value sensitivity is a change rate of the sigma value in the slack distribution of the target path when the sigma value in the delay distribution of the cells constituting the path is slightly corrected (for example, 1 [ps]). Accordingly, a cell having a larger value of the mean value sensitivity and sigma value sensitivity included in the sensitivity information has a greater influence on the slack of the target path.

  FIG. 3 is an example of a flowchart of the entire integrated circuit layout process including the timing ECO by the integrated circuit timing adjustment method according to the present invention. In the layout processing of the integrated circuit, for example, first, a description in a hardware description language (HDL) of a register transfer level (RTL) is logically synthesized (S1). Next, a logic-synthesized circuit layout, that is, physical placement and routing is performed (S2). After the layout is completed or in parallel with the layout, STA is performed (S3). In STA, delay calculation is performed and timing analysis is performed. Also, sensitivity information F1 is generated. As a result of the STA, it is determined whether or not the timing rule is satisfied in sign-off (S4). When the timing regulation is not satisfied (S4: NG), the process proceeds to the timing ECO.

  The setup time can be satisfied as the data is determined earlier, but it is difficult to advance the data timing after the logic circuit is laid out. On the other hand, the hold time can be satisfied as the end of data is late, but even after the logic circuit is laid out, the delay can be easily delayed by inserting a delay buffer cell. Therefore, the layout tool generally lays out the cells so that setup errors do not occur, then checks the hold error for the laid-out integrated circuit, and delay buffer cells on the path where the hold error occurs (error path). To fix the hold error. Therefore, at the timing ECO, the timing error is corrected by inserting the buffer cell into the cells constituting the error path (S5). In correcting the timing error at the timing ECO, the sensitivity information F1 is referred to. In addition, circuit correction information F2 by the buffer cell insertion is generated.

  When the correction of the timing error at the timing ECO is completed, the layout is performed again based on the circuit correction information F2.

  On the other hand, when the timing regulation is satisfied in sign-off (S4: OK), verification is performed to verify that there is no physical problem and that there is no problem by test simulation (S6).

  A detailed processing flow of the timing ECO (S5) in FIG. 3 will be described with reference to FIG. Here, as described above, slack is a margin with respect to the timing specification, that is, a margin. Hereinafter, the setup time margin is expressed as setup slack, and the hold time margin is expressed as hold slack.

  At timing ECO, necessary data is input prior to error path correction (S51 to S53). In the timing list input in S51, an error path is read from the result of STA (S3) in FIG. In the input of slack information in S52, the setup slack is read from the STA result, and the setup slack is set for each terminal of each cell. At this time, the setup slack having the strictest condition, that is, the minimum setup slack is set for a cell through which a plurality of paths pass. In the input of sensitivity information in S53, sensitivity information F1 generated by STA is read. Specifically, for each path, a mean value sensitivity and a sigma value sensitivity are set for each terminal of the cells constituting the path.

  When the necessary data has been entered, the process proceeds to error path correction. In the error path correction, of the error paths read in S51, for the error path that is the target of timing error correction, the cells that affect the MET path without the timing error are excluded from the cells that are candidates for inserting buffer cells. (S501). The cell that affects the MET path is identified with reference to the value of the mean value sensitivity for the MET path from the sensitivity information F1.

  After the cells that affect the MET path are excluded, with respect to the remaining cells, the value of the mean value sensitivity to the error path is referred to from the sensitivity information F1, and a cell having a higher value is searched (S502).

  As a result of the search in S502, for the cell having a high mean value sensitivity value for the error path, a cell having a high value is searched by referring to the sigma value sensitivity value for the error path from the sensitivity information F1. (S503).

  As a result of the search in S503, a cell having a high sigma value sensitivity for the error path is specified as a position (cell) at which the buffer cell is inserted. A delay buffer cell that does not exceed the setup slack value set in S52 is inserted before or after the specified cell (S504).

  After the insertion of the buffer cell in S504, hold slack and setup slack are recalculated (S505, 506). As a result of the recalculation of slack, it is determined whether or not the setup time and hold time satisfy the regulations (S507, S508). If the setup time does not reach the specified value due to the insertion of the delay buffer cell and a setup error occurs (S507: No), the delay buffer cell has too high driving capability and the delay becomes too large. . Therefore, the inserted buffer cell is deleted (S509), a buffer cell whose driving capability is one rank lower is inserted (S510), and the process returns to slack recalculation (S505, 506).

  If the setup time satisfies the regulation (S507: Yes) and a hold error has occurred (S508: No), the delay amount is still insufficient. Therefore, it is determined whether the setup slack still has room (S511). If there is room in the setup slack (S511: Yes), it means that further delay is possible. Therefore, the same delay buffer cell is further inserted at the same position (cell) as the previous S504 (S512), and the process returns to the slack recalculation (S505, 506).

  If there is no allowance for setup slack (S511: No), it means that no further delay buffer cell can be inserted at the same position (cell) as the previous S504. Therefore, the cell having the highest sigma value sensitivity one rank below, that is, the cell having the second highest sigma value sensitivity is searched (S513), and the delay buffer cell is inserted before or after the cell (S514), and slack recalculation is performed. Return to (S505, 506).

  If the hold time also satisfies the regulation (S508: Yes), it means that the timing error has been corrected for the error path targeted for timing error correction. Therefore, circuit correction information F2 by the buffer cell insertion is generated. In this way, the error path correction loop of FIG. 4 is repeated until there is no next error path that is the target of timing error correction.

  A specific process of the timing ECO will be described with reference to FIGS. FIG. 5 shows an example of a circuit to be subjected to timing ECO processing. An explanation will be given by taking three paths FF1-FF3, FF2-FF3, and FF5-FF4 included in the circuit of FIG. 5 as an example. Here, for example, the paths FF1-FF3 are paths from the flip-flop FF1 through the cells A, C, D, E, F, G to the flip-flop FF3. For the sake of explanation, the slack included in each path is in the order of hold slack and setup slack, the path FF1-FF3 is -50 [ps], 50 [ps], the path FF2-FF3 is -100 [ps], 150 [ps], Assume that the paths FF5 to FF4 are 50 [ps] and 50 [ps]. Here, a negative value means that a timing error that is less than the specified value has occurred due to a lack of slack. That is, the path FF1-FF3 and the path FF2-FF3 are error paths, and the path FF5-FF4 is a MET path. Each slack value is input in S51 and S52 of FIG.

  FIG. 6 shows an example of the sensitivity information F1. “StartPoint” and “EndPoint” represent the start point and end point of the path, respectively. In the “Instance” column, the cells constituting the path are shown for each terminal. “Incr” represents the delay of each cell. For example, “/ INSTANCE_name1 / A 3.0” means that the wiring delay to terminal A of cell INSTANCE_name1 is 3.0, and “/ INSTANCE_name1 / X 6.0” means that the delay of cell INSTANCE_name1 itself is 6.0. To do. “Path” represents a value obtained by adding the delay “Incr” of each cell. “Mean sensitivity” and “sigma sensitivity” enclosed by squares represent the mean value sensitivity and sigma value sensitivity of each cell with respect to the path, respectively. “Slack” is a hold slack value of the path. That is, a path in which “slack” is a negative value is an error path. In S53 of FIG. 4, as shown in FIG. 6, the mean value sensitivity and the sigma value sensitivity are set for each terminal of the cells constituting the path, as shown in FIG.

  FIG. 7 shows an example of the sensitivity information table. The sensitivity information table is generated based on the sensitivity information F1 in FIG. As described above, the sensitivity information F1 sets, for each path, the mean value sensitivity and the sigma value sensitivity for each terminal of the cells constituting the path. The sensitivity information table summarizes sensitivity information F1 for each path as a mean value sensitivity for an error path, a sigma value sensitivity for an error path, and a mean value sensitivity for a MET path for each cell terminal included in the integrated circuit. Is. In the specific example described here, the sensitivity information F1 is referred to by this sensitivity information table.

  In the sensitivity information table shown in FIG. 7, the instance cell column includes a cell name and a terminal name. Here, the cell names in FIG. 7 correspond to the cell names in FIG. In the Globalslack column, the setup slack value set in S52 of FIG. 4 is entered. Values set based on the sensitivity information F1 are entered in the sensitivity fields of the error path mean value, error path sigma value, and MET path mean value. For a cell through which a plurality of paths pass, the minimum value excluding 0 of the sensitivity of each path is entered. This is because a sensitivity value of 0 means that there is no influence on the path, and it is not necessary to take it into consideration. For example, taking the cell C as an example, the output terminal C. Out passes through the path FF1-FF3 and the path FF2-FF3 among the three paths FF1-FF3, FF2-FF3, and FF5-FF4 in FIG. Since both are error paths, the input terminals C.C. of the cell C through which each of the paths FF1-FF3 and FF2-FF3 passes. in1, C.I. From the mean value sensitivity of the error path of in2, it can be seen that the respective mean value sensitivities are 1.01 and 1.02. Therefore, the output terminal C.C of the cell C through which both the paths FF1-FF3 and FF2-FF3 pass. The out value is 1.01 which is the minimum value of the mean value sensitivities 1.01 and 1.02 of the paths FF1-FF3 and FF2-FF3.

  When the error paths FF1 to FF3 in FIG. 5 are targets of timing error correction, the cells A, C, D, E, F, and G that constitute the paths FF1 to FF3 Become. Cells that affect the MET paths FF5-FF4 having no timing error are excluded from the cells A, C, D, E, F, and G that are candidates for inserting buffer cells (S501 in FIG. 4). The mean value sensitivity value of the MET path is referenced from the sensitivity information table of FIG. Of the cells A, C, D, E, F, and G, it can be seen that the cells E and F affect the MET paths FF5-FF4 (frame 1). Therefore, the cells E and F are excluded from candidates for the position (cell) where the buffer cell is inserted.

  After the cells E and F affecting the MET paths FF5 to FF4 are excluded, for the remaining cells A, C, D, and G, the mean value sensitivity value of the error path is referred from the sensitivity information table of FIG. A cell having a high value is searched (S502 in FIG. 4). Here, for example, when the value differs depending on the terminal as in the cell C, the minimum value excluding 0 is the cell value as described above. For cells A, C, D, and G, the mean value sensitivity value of the error path is 1.01, which is the same (frame 2). Therefore, in this specific example, cells A, C, D, and G are all selected as they are.

  As a result of searching for a cell having a high mean value sensitivity value of the error path, for the cells A, C, D, and G having a high mean value sensitivity value of the error path, this time, from the sensitivity information table of FIG. With reference to the value of the sigma value sensitivity, a cell having a high value is searched (S503 in FIG. 4). It can be seen that among the cells A, C, D, and G, the value of the sigma value sensitivity of the error path of the cell D is the highest (frame 3).

  As a result of searching for a cell having a high sigma value sensitivity of the error path, a cell D having a high value of the sigma value sensitivity of the error path is specified as a position (cell) where the buffer cell is inserted. Therefore, a delay buffer cell that does not exceed the Globalslack value 50 [ps] of the cell D is inserted before or after the cell D (S504 in FIG. 4).

  Thus, in the search for the position (cell) where the delay buffer cell is inserted in order to correct the timing error, the value of the mean value sensitivity of the MET path is referred to. For a cell through which a plurality of paths pass, the minimum value excluding 0 of the sensitivity of each path is referred to. Therefore, it is possible to identify a cell that slightly affects the MET path and exclude it from candidates for the position (cell) to insert the buffer cell. Therefore, the timing error can be corrected in consideration of the influence on the MET path, and the induction of the error path can be prevented.

  With reference to the value of the mean value sensitivity of the error path, a cell having a high value is searched. For a cell through which a plurality of paths pass, the minimum value excluding 0 of the sensitivity of each path is referred to. As a result, it is possible to identify cells where error paths are concentrated. Therefore, a plurality of error paths can be corrected at a time. Timing error correction with a small number of inserted buffer cells can be expected.

  With reference to the value of the sigma value sensitivity of the error path, a cell having a high value is searched. For a cell through which a plurality of paths pass, the minimum value excluding 0 of the sensitivity of each path is referred to. As a result, under the guarantee of the minimum timing error improvement, as the position (cell) for inserting the buffer cell, the position (cell) having the greatest influence on the timing error improvement, that is, the most suitable position for inserting the buffer cell (cell) is selected. Can be identified.

  A delay buffer cell that does not exceed the value of Globalslack at the position (cell) where the buffer cell is inserted is inserted. As described above, for a cell through which a plurality of paths pass, the value of Globalslack is the minimum setup slack value that is the most severe. Therefore, it is possible to prevent the setup error due to the insertion of the delay buffer cell.

Here, the correspondence with the claims is as follows.
The sensitivity information F1 is an example of sensitivity information.
The static timing analysis STA is an example of a process including sensitivity information for each cell.
Timing ECO is an example of a process for correcting a timing error using sensitivity information.
Step S501 for excluding cells that affect the MET path is an example of a process for excluding cells that affect the MET path.
Step S502 for searching for a cell having a high mean value sensitivity is an example of a step for specifying a cell where error paths are concentrated.
The step S503 for searching for a cell with high sigma value sensitivity is an example of a step of specifying a position (cell) for inserting a buffer cell.

  As described above in detail, according to the present invention, the timing error in each path of the integrated circuit is corrected by inserting a buffer cell into a cell constituting the path. At this time, sensitivity information indicating the degree of influence on slack, which is a margin for timing regulation, is provided for each cell for each path. The timing error is corrected using this sensitivity information.

  As a result, the timing error can be corrected in consideration of the influence on the MET path, and the induction of the error path can be prevented. Sensitivity information, which is the degree of influence on slack, is provided for each cell for each path, so it is possible to specify at which position (cell) the delay buffer cell should be inserted. In addition, since the cells with concentrated error paths can be found from the sensitivity information, it is possible to correct timing errors while suppressing the number of inserted delay buffer cells. According to the integrated circuit timing adjustment method and the computer program thereof according to the present invention, the timing error can be corrected in the integrated circuit in consideration of the influence on all paths.

Note that the present invention is not limited to the above-described embodiment, and it goes without saying that various improvements and modifications can be made without departing from the spirit of the present invention.
For example, in the flow of the timing ECO process shown in FIG. 4, cells having high mean value sensitivity and sigma value sensitivity are searched in S502 and S503, but the present invention is not limited to this. If the setup slack has no margin, a cell with low mean value sensitivity and low sigma value sensitivity may be searched so that the minimum error correction can be performed. Of course, it is conceivable to switch the processing according to the case. If the determination in S507 is No, the inserted buffer cell is deleted (S509), and a buffer cell whose driving capability is one rank lower is inserted (S510). However, it is not limited to this. When the determination in S507 is No, a delay buffer cell may be inserted into a cell having a high sigma value sensitivity one rank below.

It is a figure explaining setup time and hold time. It is a figure for demonstrating sensitivity information in relation to this invention. It is an example of the flowchart of the whole layout process of the integrated circuit concerning this invention. It is an example of the flowchart of the timing ECO process concerning this invention. It is an example of the circuit used as the object of the timing ECO process concerning this invention. It is an example of the sensitivity information F1 concerning this invention. It is an example of the sensitivity information table concerning this invention.

Explanation of symbols

A to J cells B1 to B4 buffer cells CLK clock data data F1 sensitivity information F2 circuit correction information FF1 to FF5 flip-flop HT hold time P1, P2 path ST setup time

Claims (6)

A timing adjustment method for correcting a timing error in each path of an integrated circuit by inserting a buffer cell into a cell constituting the path,
Providing each cell with sensitivity information indicating the degree of influence on slack that is a margin for the timing regulation for each path;
And a step of correcting the timing error using the sensitivity information. In the search for the position where the buffer cell is inserted, the correcting step includes:
Excluding cells that affect the MET path, which is a path without timing errors;
A step of identifying cells where error paths that are timing errors are concentrated, and
The timing adjustment method according to claim 1, further comprising a step of specifying a position where the buffer cell is inserted. The sensitivity information includes a mean value sensitivity and a sigma value sensitivity,
3. The step of excluding cells that affect the MET path refers to a value of the mean value sensitivity for the MET path, and identifies a cell that affects the MET path. Timing adjustment method. The sensitivity information includes a mean value sensitivity and a sigma value sensitivity,
4. The cell according to claim 2, wherein, in the step of identifying the cell where the error path is concentrated, the cell where the error path is concentrated is identified by referring to the mean value sensitivity value for the error path. Timing adjustment method. The sensitivity information includes a mean value sensitivity and a sigma value sensitivity,
The step of specifying the position where the buffer cell is inserted specifies the position where the buffer cell is inserted with reference to the value of the sigma value sensitivity with respect to the error path. The timing adjustment method according to any one of the above. A computer program for adjusting timing by correcting a timing error in each path of an integrated circuit by inserting a buffer cell into a cell constituting the path,
A computer program that causes a computer to execute the steps of the timing adjustment method according to claim 1.

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