TWI281031B - Test structures for on-chip real-time reliability testing - Google Patents

Abstract

Described is a system with three on chip monitoring test structures. If any of the three test structures indicates an end of life failure, a bit will be set indicating that the IC is near failure and should be replaced. This is done prior to actual device failure and will eliminate down time of the system where this IC is used. The first test structure monitors hot carrier degradation and is comprised of two ring oscillators. One is subjected to hot carrier effects (degrading ring oscillator) and the other is not subjected to hot carrier effects (non-degrading ring oscillator). Initially, both ring oscillators will each have fixed frequencies, but as the device ages, hot carrier effects degrade the degrading ring counter. Using the non-degrading ring oscillator, the degradation can be quantified and flag a failure. The second test structure monitors TDDB degradation. A plurality of N parallel connected capacitors have a stress voltage applied to them such that the time to failure of the first capacitor is the same time to failure experienced by 0.1 percentile of gates under normal usage. Breakdown of a capacitor is observed by a drop in the resistance of the structure and is used to trigger a bit indicating a TDDB end of life signal. The third test structure monitors electromigration degradation. M minimum width metal lines are connected in parallel. A current is applied to them such that the time to failure of all metal lines is the same as the time to failure experienced by 0.1 percentile of minimum width metal lines under normal usage. Breakdown of a metal line is observed by an increase in the resistance of the structure and is used to trigger a bit indicating an electromigration end of life signal. 0.1 percentile is given as an example and can be varied depending upon the users definition of device lifetime.

Description

I?81031 IX. OBJECTS OF THE INVENTION: TECHNICAL FIELD OF THE INVENTION The present invention relates to a method and apparatus for making a semiconductor, and determining the reliability in the manufacture of a special integrated circuit and using the end point of the steel semiconductor element 4 [Prior Art] (4) Specialized lion-knot lions in the forest species include the existence of inter-polar oxide collapse, electromigration, and stress-induced ribs. The ribs can be placed in the wire-like condition. The equivalent of the service circuit "year = two, the degree of success, its fine component voltage and electrical calculation and operation of the power cycle, these data are used to predict the circuit life of the circuit. ', μ - first! ^ and, the carrier is the main reliability wear mechanism of the VLSIf road, the heat carrier withstand capability of the CMOS process is due to the separate components, and the standard geometry of the component The shortened, produced and used. With Yu Lai Yu—therefore, using the current inference method to determine the simulation effect of the model heat carrier injection in the fruit VLS丨 component, the 4b complexity is true.] With the shortening of the design cycle, there is a short time. Foot:: Wei Cheng and the model heat carrier effect used for all process differences is - therefore 'have, to test the structural requirements, the system can be included in any element 1 ^ reach - Wei Ding _ when the slanting element Like the standard 代替2 instead of the die, it can be placed in the scribe line, the π in the initial grain area, and the _ parent product and Wei's explicit structure design, and can avoid 1281031 correction = inter-consumption And the reliability of the simulation of the work. Where the product is included, the reliability of the wafer is monitored to enable the _-component's end point and the component to be replaced. Other methods for determining the guilty factors have been found in U.S. Patent No. 5,875,665 ("_), a silk-guided method, which measures - (four) series of counter-compensation rises under conditions in which the family has the ability to weave money. Fall time and propagation delay. U.S. Patent No. 6,169,694 B1 (Nam et al.) teaches a method and a circuit for pre-firing a wafer on a wafer for DRAM devices, which is a method for making oxide film and capacitor failures. Patent No. 6,136,619 (Ceunindc et al.) describes a method for determining the resistance of a f-transformed charge in a conductor (four) and a method, and a single-current source can be applied to both the ί: ΐ and the It is placed close to the semiconductor die, and the direction of the current in the conductor structure is staggered to the high, and the conductor is tested at the off time. The current in the structure flows only in one direction, and the flow of the reference conductor structure by interleaving will eliminate the effect of electron migration, and the structure of the two structures can be reduced by the frequency and the red method and the method includes DC. The input is fresh to control a variety of test functions, including temperature and operating frequency. & [Summary of the Invention] The main purpose of the invention is to provide a method for monitoring the structure of money, including the heat carrier effect, _ oxide time dependent dielectric collapse (TDDB), and services. Another object of the present invention is to provide a circuit that is still due to the reliability mechanism. The purpose of monitoring the present invention is due to the relationship of the heat carrier effect, which is to provide a circuit for monitoring the reliability mechanism by the electrical collapse (T_ relationship). It is to provide a circuit due to the dependency mechanism. The purpose of the invention is to provide a reliability mechanism for indicating that the reliability mechanism to be monitored exceeds the pre-value before the failure of the active device. The day-to-day, thereby reducing the downtime of the system using the component. Pre-4 port 1281031 The correction bar uses three kinds of systems on the wafer, if any of the three test structures refers to the ^, ,, ° structure to achieve the above The target will be merged into the dry ir, "/I will be completed when the end of the fault period, and will be excluded from the system downtime when using lc. Mussels ^ Niu shot early river into the river. _ by the (four) reducer group clothing i read its own transistor, it will (lower ring vibrator), another fresh soup crying ^ heat carrier effect (four) 戸 α a clothing Zhen Meng is not Will go to the effect of heat carrier effect The oscillators each have a fixed frequency, and the f rate of the two frequencies is in the (four) lower gated binary count II, and is reset in another state. Just after the process, at each gate cycle, The binary counter will have a finite number of counts "I". With the reduced ring oscillator frequency due to the heat carrier effect below, at some point the binary counter will see less pulses applied, and the count The result will be "j" (its j<j), the designer will decide the difference.), the extent of the decline will show a sinful problem, and then if (H) more than one A certain degree of preset limit 'circuit will generate a signal of the end of the use period. The first / test structure is to monitor the decline of the gate oxide TDDB, a plurality of "η" parallel connected capacitors Having a stress voltage applied to it so that under normal use conditions, the 'faulty _ system fault has a small fraction of the time, the capacitance collapse is monitored by the difference in structural resistance and is used to trigger a bit Yuan indicates the use period signal TDD B. The second test structure monitors the electromigration drop, ·, Μ"the smallest width of the metal line is connected in parallel'. A current system is applied to it so that under normal use, the time of failure is somewhat small. Part of the time, the collapse of a metal line is monitored by the difference in structural resistance and is used to trigger a bit to indicate the end of the use signal electromigration end point. [Embodiment] 1281031 Correction Now refer to Figure 1, showing this Hairline Use - The system has three types of frames in the preferred embodiment of the present invention. The preferred embodiment of the present invention provides a test structure 30, and provides a test structure 30, and Depending on the dielectric breakdown (TDDB), there is a logic output. Each test structure (1〇, 30, 5〇) has ^. To reach the end of its useful use period, any of the - output - logic layer makes the indicator G, will lose the logic, (four) money 丨 c close to the scale and lose the dragon 1G health _ face down, said After the description, I am now special ΞΓ ΞΓ / 本 发 发 C 丨 结构 structure 1 (10) - better real compensation block diagram, ' ^ ^ reduced % vibrator 12 (which will not be affected by the heat carrier effect) and - drop , the ring oscillator 14 (which is affected by the heat carrier effect), the non-reduced ring oscillator ▲ 2 port non-reduced output signal a is applied to the - divider 彳 6, the frequency divider 1 is The binary 4 and the binary comparison n 20 provide the start signal 17, and the frequency of the start signal 17 is the non-reduced output signal 13 frequency fraction, which is known by the formula: f __ fNon-Degraded hn 2k~ k = 1, 2, 3, ..., the reduced output signal 15 of the reduced ring oscillator 14 is applied to the input of the binary counter 18. The multi-bit output 19 of the binary counter 18 is applied to the binary comparator 2 The output of the binary comparator 20 is supplied to the η CL lifetime end indicator 21. Referring now to Figure 3, the timing of the HCL test structure 1 第 of Figure 2 is shown. It should be noted that Figure 3 is merely an embodiment of circuit operation, and the actual timing varies as needed, and the display is non-reduced. The output signal 13 shows a reduced output signal 15 before the reduction on the left and after the decrease on the right. It should be noted that the frequency of the non-reduced output signal 13 and the reduced output signal 15 before the reduction is not required to be the same, but is the same in the operation of this embodiment. In this embodiment, the enable signal 17 (from the frequency divider 16) is one-eighth of the frequency of the non-reduced output signal 13. During its high period, the enable signal 17 provides the start of a binary counter. During its low period, the enable signal 17 resets the binary counter and initiates the function of the binary comparator 20. If the 1281031 correction is activated in response to the fault input limit when the binary counter 18 is activated, the multi-bit wheel will be reduced to "4" (01002) before lowering the output signal 15 (left). After the (right) multi-bit output 19 will only be, 3n (〇〇1〇2). During the low period of the enable signal 17, the comparator compares to a multi-bit output 彳9 against a fixed number (4 in this embodiment), and when the multi-bit output 19 is less than a predetermined limit At 4 o'clock, the signal of the end of life indicator 21 is issued. Then, when the το component is new, the binary counter 18 can be pulsed as a finite number of lowering ring oscillators 14 between each gated cycle, with a J = oscillation of the falling = as a function of the heat carrier effect. The frequency of the device 14 drops, the binary counter will appear at some point to apply = less pulse, and the final output count will be " factory (its kind. Binary comparator 2〇 will be designed as when the difference (jj) indicates In the case of a reliability problem, the circuit will produce an end point of the lifetime flag. The multiple pairs of inverting || of the zero 4a® towel can produce a reduced ring oscillator 4. To reduce the voltage across the component, Non-reducing ring oscillators can be fabricated, for example, similar to 4a, which use FETs with longer channel lengths. Stacked FETs can be used, for example, as shown in Figure 4b. Non-reduced ring oscillator for the towel. Figure 4c shows a non-reduced weaver of another type - a preferred embodiment using a current mirror to reduce the potential across each FET. The first test structure 3 〇 system monitoring gate oxide tddb Referring to Figure 5, a preferred embodiment of a circuit for determining the termination of a TDDB is provided by a complex, uncoupled capacitor 32, the plurality of capacitors H32 being arranged in series, and Connect f low resistance 34 to a common circuit. Apply a pressure voltage % through a switch 8' to a plurality of capacitors 32 and low resistance legs connected in series. The capacitor voltage is - a solid (four) voltage It is set at 丨c power supply voltage _)_ to 18 ports "depending on the manufacturing technology used. In order to sense - capacitor failure, apply a common pressure of 4 〇 (equal to Vdd) through a switch 42 To one end of the high resistance 44; the other one is connected to the latch 48 by a plurality of capacitors 32 connected in series and a plurality of resistors 32. The capacitors are connected to the latch 48. The 32 series is turned off by turning off the switcher and simultaneously turning on the switches 42 and 46. 10 1281031 / The correction is subjected to the pressure 'and the stress is applied 36. In order to sense the plurality of capacitors (4), the switch 38 is turned on and the switches 42 and 46 are turned off, This removes the stress voltage % and applies a gas voltage of 40. Excessive resistance 44 to a plurality of capacitors. If the capacitor % operates correctly (high resistance), then the voltage input to the latch 48 will be a logic ^48, the output (end of life end flag) will For "〇" (low). During sensing, the breakdown of the capacitance % is monitored by a plurality of resistor drops, thereby pulling the input to the latch (4) to logic (low), and the latch 48 The output (end of life flag) will show the conversion of Weber __ curve for the 6th figure, which is used to design the voltage and region of the complex structure of the td end point flag capacitor test, cumulative distribution function (cumulative distribution) Function, CDF) is selected as ·, the number of capacitors 2 is designed to be - a suitable special product and process on the wafer TDDB monitoring circuit 'target oxide region must be known, and must have Nabo The sub-parameters (the unique reduction and subtraction parameters are supplemented in Figure 6) are characterized by the stress voltage and the oxide region of the product to convert the Weber curve (1) to the Weber curve (2) product. The stress voltage and number (N) of the capacitor 32 are selected such that the Weber curve CDF1/N percentile is about 10 years, and the sixth figure uses 〇1% as an embodiment, but the hundred bits can be used. The change is based on the definition of the component's lifetime. - The third test structure 50 monitors the electromigration drop, see in particular, Figure 7, · μ" Parallel connection (minimum width) metal wire 52 connects one end of the wire to a common path, A fixed stress voltage 56 between 0_5 and 1.0 times Vdd is applied through the switch 58 to the other end of the wire 52. The stress is determined based on the resistance of the wire 52 and the manufacturing technique. In order to sense a metal line 52 failure, an induced voltage 60 (typically 0.5 times _) is applied through the switch 62 to a low resistance end; the other end of the resistor 64 is interspersed with the metal line 52, The Jinlin 52 series connects through the Guanshi and reaches the setting input of the latch. The wire 52 is subjected to a force by closing the switch 58 while simultaneously opening the switch bit and the book, and thereby applying a stress voltage 56. In order to sense that the metal line 52 is faulty, the open unit 11 is turned on and the switches 62 and 66 are turned off, which applies an induced voltage 60 through the low resistance 64 to the plurality of metal lines 52. If the wire 52 is operating correctly (it has a low resistance), then the voltage input to the latch 68 will be a logic "〇··(low), and the output of the latch is clear (used) The end of the flag will be "〇" (low). Failure (opening) of the individual wires 52 during compression will increase the current at the remaining wires 52, causing them to be systematically opened. The failure of all of the metal lines 52 during sensing is monitored by the substantial increase in the resistance of the parallel metal lines 52, whereby the set input of the pull-up latch 68 reaches a logic Π 1 " (high), and thereby sets the latch 68 The end-of-life flag is generated as a "1" (high). Figure 8 shows the conversion of the lognormal curve (丨〇gn〇rma| p|〇t), which is used to design the electromigration metal line structure. The stress current and area, in the design-type _ process ^ product in the on-wafer electromigration monitoring circuit, will use a static strategy similar to the TDDB design. Must be distributed in logarithmic normal parameters (fault and the formation of the middle of the parameters Time) is characterized by a stress current to convert the lognormal curve (1), and a second lognormal curve (2) results in a special manufacturing technique. Selecting the force current (determined by the dynamic voltage 56) and the metal line 52 : number: (10), in order to convert the logarithmic normal curve (2), the CDF (M_1) / M percentile is about 1 〇 component Γ Γ 用 用 为 为 为 但是 但是 但是 但是 但是 但是 但是 但是 但是 但是 但是 但是 但是 但是 但是According to J Ming, the type is used for the end of the use on the wafer. Point indicator method 5 Effective use of the lying end point, which is related to the heat carrier effect call failure to be replaced. In the actual yuan, more institutions are instructed to indicate the use period of the structure = the second operator can understand the τ's purpose The familiarity of the technique should be included in the modification or modification of the patent application method described below, and still [simplified description of the drawing] 12 1281031 U is detailed by the specific embodiment with the attached drawings, the original The purpose, technical content, characteristics and the effects achieved. Tian Gengyi understands this issue. Figure 1 depicts the block diagram of the reliability system. The =2 diagram description is used to determine when a hot note has occurred. Figure 3 shows the timing example of the system in Figure 1. [...] The description of the ghost system shows the reduced ring vibrator of Figure 1. The preferred embodiment is shown in Figure 2f4. Reduced Ring Attack - Preferred Embodiment. Figure 5 shows the TDDB endpoint of the unused test circuit - a preferred embodiment. The system is a WeibUH curve used to determine the TDDB. Reliability machine

Figure 7 shows a preferred embodiment of the use of fine-tune money transfer endpoints. Figure 8 shows a lognormal curve (丨〇gn〇rma| _) that is used to determine the parameters in the shift reliability mechanism. [Main component symbol description] 10 hot carrier injection (HCI) test structure 12 non-reduced ring oscillator 13 frequency divider 14 reduced ring oscillator 15 reduced output signal 16 frequency divider 17 start signal 18 binary counter 19 more Bit output 20 binary comparator 21 use end point indicator 30 gate oxide time dependent dielectric collapse (TDDB0, j test structure 32 capacitor 36 pressure voltage 13 1281031 correction 38 switch 40 induced voltage 44 high resistance 46 switch 48 latch 50 electromigration test structure 52 metal line 56 stress voltage 62 switch 66 switch 64 low resistance 68 latch 70 use end point indicator

14

Claims (1)

Amend the scope of the patent, the scope of the patent application: the obstacle, which is thus predicted to indicate the failure of the hot-loaded Zhao-injection threshold; the frequency of the ugly field is lower than a known borrowing! , Prediction • Oxide surface failure, which is borrowed, has been = = shows: Therefore, when the resistance of the plurality of capacitors, the resistance drops below - "barrier, flat j, take the resistance of small width metal wire and predict electricity Migration The power of the gold C is L' and the failure is indicated when the plurality of parallel connections, the minimum number of the parallel connections, and the known threshold; and the method described in the item, wherein the ring oscillation This frequency of the device is measured by a pulse of 3^ί ^ exceeding the interval of -_. The method of the present invention, wherein the fixed interval is caused by a non-reduced one, the method of claim 2, wherein the mosquito spacer is The edging device is determined by dividing the frequency of the non-reducing ring oscillator. The method of claim 1, wherein the resistance of the plurality of capacitors is determined by applying an inductive voltage and a large resistor in series to the plurality of capacitors, and measuring a voltage across the plurality of capacitors. of. 6. The method of claim 5, wherein the induced voltage is equal to a supply voltage of the integrated circuit. The method of claim 1, wherein the stress voltage is between 1.2 and 1.8 times the supply voltage of the integrated circuit. The method of claim 1, wherein the number of the plurality of capacitors and the intensity of the induced voltage are selected by the conversion condition of Weber, so that 15 1281031 is repaired. The first fault will reflect a typical component that causes the fault to go to the percentile. The method of claim 1, wherein the plurality of parallel connection and the resistance of the metal wire of the small gold are applied by the induction-f-voltage and the small-resistor string, the plurality of parallel connections, and the minimum width. The metal line and the measured voltage are determined across the plurality of quick connect, minimum width metal lines. 10ΐΓ=: The method described in item 9 wherein the inductive power plant is strong in the integrated circuit, the greening of the inductive circuit, the keying force, the circuit described in the first item, wherein the plurality of metals The number of lines and the strength of the induced voltage are selected by converting the logarithmic normal distribution of the use conditions such that the first fault reflects a selected percentile of a typical component lifetime fault. 13. A method for indicating the end of the use period in an integrated circuit, purely included. By calculating - the on-chip ring oscillator pulse exceeds one solid to measure the ring reduction rate, · Measure the texture of the body, which is reduced by the heat load' and when the frequency drops below the known threshold, it indicates early, and by using a sense, the pressure is connected in series with a large resistor. Measure the resistance of the plurality of capacitors by a plurality of capacitors, and measure the voltage across the plurality of capacitors, and measure the resistance of the plurality of capacitors by pre-measurement == 匕TDDB failure', which operates by a stress voltage, and The resistance is reduced to a known threshold to indicate a fault; the precision voltage is connected in series with a small resistor to a plurality of parallel connections, the minimum width = ? two measurements across the plurality of parallel connections, the minimum width of the metal : ί it;:3 force _ and operate, and when the plurality of parallel links are: ί the resistance rises above a known threshold and indicates 16 1281031 γ ρ 士 indicates when the heat carrier injection fails The gate oxide TDDB fault--one of the faults has failed.戍 • • • 14. 14. 14. 14. 14. 14. 14. 14. 14. 14. 14. 14. 14. 14. 14. 14. 14. 14. 14. 14. 14. 14. 14. 14. 14. 14. 14. 14. Non-reduced 15·如: please = 范” The method described in item 13, wherein the fixed interval is determined by the % vibration of - and the error is determined by dividing the frequency of the non-reducing ring oscillator - 16_ The method described in Item 13 of Weiwei, the supply voltage of the sense circuit. The pin body 17_, as claimed in claim 13, the method of claim 13, wherein the supply voltage of the stress voltage is from 1.2 to 1.8 times. The method of claim 13 wherein the induced voltage is the method of the product #19_===:r, and the side force surface of the circuit 20 is as in the 13th article of the patent scope The method wherein the number of the plurality of capacitors is the intensity of the induced voltage is selected by converting the use condition of the Weber distribution, and the first barrier is reflected by the selection of a typical component. The method of claim 13, wherein the intensity of the inductive electric castle of the plurality of metal lines is converted by using a logarithmic normal distribution and the position of the ^ / / so that the first fault will reflect a typical component system The choice of the period of failure ^ · 22 · - in the - integrated circuit indicates the end of the closure The on-chip (just post) system includes: a circuit for predicting a failure of a heat carrier injection, comprising: - a bad oscillator, which is generated by a hot-spot person - a timing signal falling; a ring oscillator, A second timing signal is generated by the hot carrier injection without falling; a 2k frequency divider, k is an integer; a binary counter having a multi-bit output; and 17 1281031 correcting the binary comparator; A circuit for predicting a gate oxide TDDB fault; a circuit for predicting an electromigration fault; and, - a type indicating when the heat carrier is inflated, or the Thunder is being smashed虱 TD TD TD TD TD TD TD TD TD TD TD TD TD TD TD TD TD TD TD TD TD TD TD TD TD TD TD TD TD TD TD TD TD TD TD TD TD TD TD TD TD TD TD TD TD TD TD TD TD TD TD TD TD · The output of the 2k frequency divider is used to output a multiple; the frequency of the second clock signal is the second timing signal to enable the Hi timing signal to be initialized and capable of driving The binary counter and the multi-bit output of the binary counter are applied to the female-to-two_: a second dysfunction recording capacitor Hi, which is composed of a plurality of terminals connected to the f-bearing, the capacitor having a terminal A and B; port ~, two first resistors, which are electrically connected between the terminal B and a shared circuit; a stress voltage source 'connected to the terminal A by a first switch; An induced voltage source connected to the terminal A by a second switch connected in series with a second resistor; and a second switch connected to the input of the terminal A to an inverter; wherein: The capacitor group is stressed by turning off the first switch and opening the second switch and the second switch; and the 5th predicted gate oxide TDDB fault is caused by opening the first switch and closing The second open 18 1281031 is modified by the == the third switch, and the output logic of the inverter is monitored, where the logic level of the output of the inverter is high. After the time, the gate oxide TDDB has already occurred Barrier. 25. The component described in claim 24, wherein the number of the plurality of capacitors and the inductance of the voltage are selected by converting the use condition of the Weber distribution, so that the first fault will be reflected. A selection of quantiles for the failure of a typical component lifetime. 26. The component of claim 22, wherein the circuit for predicting electromigration failure comprises: - a metal wire group consisting of a plurality of parallel connected, minimum width metal wires, The system has terminals A and B, wherein the terminal B is electrically connected to a common circuit; and a stress voltage source is connected to the terminal A by a first switch; - an induced voltage source Passing a second switch and a second resistor to the terminal A; and P^ a third switch, which connects the terminal A to the input of a latch. Where: 'The wire group is used by The first switch is turned off and the first three switch is turned on to be stressed; and the predicted electromigration fault is caused by opening the first switch and turning off the second switch and the second switch. A logical bear that determines and monitors the output of the latch, wherein the electromigration fault occurs if the logical hierarchy of the output of the latch is high. 27_ The component of claim 26, wherein the number of the plurality of metal wires and the intensity of the induced voltage are selected by converting a logarithmic normal distribution of use conditions, so that the first fault is reflected A typical component lifetime failure ^ percentile. ,, select 19 Amendment 1281031 - ^ VII. Designated representative map: (1) The representative representative of the case is: (1). (2) A brief description of the component symbols of this representative figure: 10 HCI test structure 30 gate oxide TDDB test structure 50 electromigration test structure 70 end of life indicator 8. If there is a chemical formula in this case, please disclose the chemical formula that best shows the characteristics of the invention: