TWI281031B - Test structures for on-chip real-time reliability testing - Google Patents
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- G—PHYSICS
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- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2855—Environmental, reliability or burn-in testing
- G01R31/2856—Internal circuit aspects, e.g. built-in test features; Test chips; Measuring material aspects, e.g. electro migration [EM]
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- G—PHYSICS
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- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/12—Testing dielectric strength or breakdown voltage ; Testing or monitoring effectiveness or level of insulation, e.g. of a cable or of an apparatus, for example using partial discharge measurements; Electrostatic testing
- G01R31/1227—Testing dielectric strength or breakdown voltage ; Testing or monitoring effectiveness or level of insulation, e.g. of a cable or of an apparatus, for example using partial discharge measurements; Electrostatic testing of components, parts or materials
- G01R31/1263—Testing dielectric strength or breakdown voltage ; Testing or monitoring effectiveness or level of insulation, e.g. of a cable or of an apparatus, for example using partial discharge measurements; Electrostatic testing of components, parts or materials of solid or fluid materials, e.g. insulation films, bulk material; of semiconductors or LV electronic components or parts; of cable, line or wire insulation
- G01R31/129—Testing dielectric strength or breakdown voltage ; Testing or monitoring effectiveness or level of insulation, e.g. of a cable or of an apparatus, for example using partial discharge measurements; Electrostatic testing of components, parts or materials of solid or fluid materials, e.g. insulation films, bulk material; of semiconductors or LV electronic components or parts; of cable, line or wire insulation of components or parts made of semiconducting materials; of LV components or parts
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/26—Testing of individual semiconductor devices
- G01R31/2642—Testing semiconductor operation lifetime or reliability, e.g. by accelerated life tests
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- G—PHYSICS
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- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
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- G—PHYSICS
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- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/30—Marginal testing, e.g. by varying supply voltage
- G01R31/3004—Current or voltage test
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
- H01L22/34—Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line
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Abstract
Description
I?81031 修正 九、發明說明: 【發明所屬之技術領域】 本發明係有關於-種使祕半導體觀之方法及裝置,特 積體電路製造中決定可靠度且鋼半導體元4使用終點之方 【先前技術】 ㈣林種專門的峨結獅使胁在積 機構包括有間極氧化物崩潰、電遷移、應力遷 使肋可該絲齡職型絲類條件進^ 難置諸^btabertr,雜服電路"年= 二Γ、成度的等效估計,其細元件電壓及電料算及操作功^ 循環為基礎,這些資料係使用於預測電路的讎壽命。’、μ --先!^及,载體注人係VLSIf路中主要可靠度磨損機構的其中 刖,CMOS製程的熱載體耐受力係由 於單獨的元件、及推_標準操_ 著元件幾何的縮短,產使用』而付到的。隨 變得俞來俞—因此,使用電流推斷方法的使用期判斷 果型VLS丨元件中模型熱載體注入的模擬效 夠去進ί這4b複雜確及】隨著設計週期的縮短’短時間有足 :的:魏程及用於所有製程差異的模型熱載體效應是為- 因此’有,要測試結構的需求,其係可納入任何元 1 ^達到-魏定的_時,將傾著元似標丨 ς二 代替晶粒,可適合置於切割道(scribe line)中、最初晶粒區中的 π、而_擬母個產品及魏的顯結構設計,且可避免 1281031 修正 =間消耗及可靠度模擬的鋪卫作。其在包含有產品處,在晶片上可 靠度監測可使_ -元件的使職終點,且標出需要取代的元件。 其他決疋可罪度因素的方法已見於美國專利第5,875,665號 (」_),絲導-種方法,其在具有科具有織賴錢力的條件 下’測量出-㈣串聯的反補上升及下降時間及傳播延遲。美國專 利第6,169,694B1號(Nam等),係教導一種進行DRAM元件的在晶片上 晶圓預燒的方法及電路,_地是,使耻方法制試氧化物膜 及電容器故障。額專利第6,136,619號(Ceunindc等)係描述-種決定 在導體中的f遷闕發抵抗力電荷㈣路及方法,單—電流源可施加 ί:ίΐ及—職導體結構兩者上,其係設置於接近半導體晶粒上, 導體結構中電流的方向係交錯仙—高,關時測試導體 、、、。構中的電流只流向-個方向,藉由交錯使用參考導體结構 流’會排除電子遷移的效應,而轉兩者結構中 電 而頻可减及故_紅方法及,這財法包含有DC輸入鮮的 以控制多種測試功能,其係包括有溫度及操作頻率。 & 【發明内容】 t發明之主要目的,係在提供—種監断靠錢構之方法,々系 匕括有熱載體效應、_氧化物時間相依介電崩潰(TDDB)、務。、 本發明之另一目的,係在提供一猶由於刼番 可靠度機構的電路。 種由於熱载體效應的關係而監測 本發明之又-目的’係在於提供—種由 電崩潰(T_的關係而監測可靠度機構的電路。减物時間相依介 本發明之又-目的,係在於提供一種由於 靠度機構的電路。 而i测可 本發明之又-目的,係在於提供—種用於標示 二當-個要監測的可靠度機構在主動元件故障前超過—個預 值日守,從而減少利用該元件的系統之停工期。 預4 口限 1281031 修正 條 使用-種系統具有三種在晶片上 的,若三種測試結構的任何一種指 ^、、、°構而獲致上述的目 元將合役成於干ir垃、“/I 使用期故障終點時,一位 完成,且將會排除使用lc時系統的停工期。纟貝^牛射早之河 成.馳賴下降,電_由㈣減器所組 衣振i讀具有自己的電晶體,其會 (降低的環振蘯器),另一個鮮湯哭目^ 熱載體效應的影響 ㈣戸α 個衣振孟為則不會戈到熱载體效應影響(非降 ?個環振盪器每個都具有固定的頻率,兩頻率 士的f率在—個㈣下閘控二進制計數II,且在另-個狀態下重設 。正好在製程之後,在每個閘控循環時,二進制計數器將會 至ϋ有限數目的計數"I"。隨著因熱載體效應使降低的環振盈器頻 以下在某些點上二進制計數器將會看到施加的較少脈衝,且計數 的,果將會為"j"(其j<j),職設計者將會決定差·),其下降的程度 曰才曰示出個可罪性的問題,且然後若(H)超過一個某種程度的預設限 制時’電路將會產生—個使用期終點的訊號。 第一種/則试結構係監測閘極氧化物TDDB的下降,複數個"η"平行 連接的電容器’係具有—應力電壓施加於其上,以致於在正常使用狀 態下’故障的_係故障某些小部份的時間,—電容的崩潰係由結構 電阻的差異所監測到的,且使用於觸發一個位元指示出使用期訊號 TDDB終點。 第二種測試結構係監測電遷移下降,·,Μ"最小寬度金屬線係平行的 連接’ 一電流係施加於其上,以致於在正常使用狀態下,故障的時間 係故障某些小部份的時間,一金屬線的崩潰係由結構電阻的差異所監 測到’且使用於觸發一個位元指示使用期訊號電遷移終點。 【實施方式] 1281031 修正 現在參閱第1圖,係顯示本發 係使用-系統具有三種在Μ 方塊圖本發明的―較佳實施例 熱載體注人(HCI)職上監_試結構,係提供一 測試結構30、及—電遷極祕物時附目依介電崩潰(TDDB) 有一邏輯輸出料Ϊ 每個測試結構(1〇、30、5〇)具 ^。達到其有用的使用期終 ^右似、、、.構中的任何—輸出—邏輯層使 指示器G、將輸f邏輯姑㈣錢丨c接近鱗且 失龍構1G健_麵下降,謂會描毅後,現在特別 ιΞΓ/ 本發彻c丨職結構1⑽—較佳實補之方塊圖, ’ ^ ^降低的%振盈器12(其不會受到熱載體效應的影響)及-降 ,的環振盪器14(其會受到熱載體效應的影響),該非降低的環振盈器 ▲2的口非降低輸出訊號a係施加於—分頻器彳6上,分頻器1崎於二進制 4數器18及—進制比較n 20提供啟動訊號17,啟動訊號17的頻率係為 非降低的輸出訊號13的-頻率分數,係由公式得知: f __ fNon-Degraded hn 2k~ 其中k=1,2,3····., 降低的環振盪器14的降低輸出訊號15係施加於二進制計數器18 的輸入上’二進制計數器18的多位元輸出19則施加於二進制比較器2〇 的輸入上’ 一進制比較器20的輸出則提供到η CL使用期終點指示器21。 現在參閱第3圖,係顯示第2圖HCL測試結構1〇的定時,應該注意 的,第3圖僅僅為電路操作的一種實施例,且實際的定時隨著需要而變 化,其係顯示非降低的輸出訊號13,在左邊的降低之前及在右邊的降 低之後顯示出降低的輸出訊號15。應該注意的是,在降低之前非降低 的輸出訊號13及降低的輸出訊號15之頻率不需要相同,但在此實施例 操作中係顯示相同的。在此實施例中,啟動訊號17(來自分頻器16的) 係為非降低輸出訊號13頻率的八分之一。在其高週期間,啟動訊號17 係提供二進制計數器的啟動,在其低週期間,啟動訊號17重設二進制 計數器,且啟動二進制比較器20的功能。若當啟動二進制計數器18時 1281031 修正本 對故障輸入界限有反應時,在降低輸出訊號15的降低(左側)之前多位 元輪.出19將會為"4"(01002),然後在降低(右側)之後多位元輸 出19將只 會,3n(〇〇1〇2)。在啟動訊號17的低週期間,比較器對照一個固定的 數字(在此實施例中為4)與多位元輸出彳9相比較,且當由一個預設的限 制使多位元輸出19小於4時發出使用期終點指示器21的信號。 然後,當το件是新的時,在每個閘控循環間,可以使二進制計數器18 作為有限數量的降低環振盪器14脈衝,隨著因熱載體效應的關係而使 降=的J辰振盪器14頻率下降,二進制計數器輝某些點上會出現施加 =少脈衝,且最後的輸出計數將會為"厂(其种。二進制比較器2〇將 會设计成為,當差異(j-j)指示出一種可靠度問題時,則電路將會產生一 使用期旗標的終點。 零 4a®巾的多對反相||可製造出降低的環振盈器 4。為了要降低跨過元件的電壓,可製造出非降低的環振蘯器,例如, 與第4a,相似,其係使用具有較長通道長度的FETs(場效電晶體)。可 使用堆豐的FETs,例如,顯示於第4b圖巾的非降低的環振盪器。第4c 圖係顯不另-種案例的非降低的還織器之—較佳實施例,其係使用 一電流鏡以降低跨過每個FETs的電位。 -第一種測試結構3〇係監測閘極氧化物tddb下降,參閱第5圖,係 =不-種用於決定使關TDDB終點的電路的一較佳實施例,係提供複 數,解行連接的電容器32,此複數個電容H32係串聯的設置,且連 f低電阻34到-個共用的電路。施加一壓力電壓%穿過一開關器 8 ’而到串聯結合在—起的複數個電容器32及低電阻腿。電容器壓 係為-個固㈣電壓,其設在丨c電源電壓_)_到18 口“係依使用的製造技術而定。為了要感測—電容器的故障,施加 古壓4〇(等於Vdd)穿過一開關器42,而到高電阻44的一端;此 另I,則繫在串聯結合在—起的複數個電容器32及低電阻 數個f容ϋ 32储由—關祕而連接到—鎖存器48。 複數個電容器32係藉由關閉開關器洲同時打開開關器42及46而 10 1281031 / 修正本 受到壓力’且藉以施加應力輕36。為了感應複數個電容㈣ 則打開開關器38同時關閉開關器42及46,此會移除應力電壓%,且施 加气應電壓40穿過高電阻44到複數個電容器上。若電容器%正確地運 作(高電阻)時,則在輸入到鎖存器48的電壓將為一邏輯 ^48的,出(使用期終點旗標)將會為"〇"(低)。在感應期間,電容%的 崩潰會藉由複數個電阻下降而監測到,藉以拉高到鎖存㈣的輸入以 邏輯(低),且鎖存器48的輸出(使用期終點旗標)將會為 第6圖係顯示韋伯__曲線的轉換,其係有用於設計td 用期終點旗標電容器測試複數個結構的電壓及區域,累計分佈函數 (cumulative distribution function,CDF)係選擇為·,其中 個電容幻2的數目4了要設計—個適當的特別產品及製程的在晶片 上TDDB監測電路’目標氧化物區域必須為所知,且必須具有拿伯分 參數(獨特的制減參數補示於第6圖)的特徵,藉由應力電壓及產 品的氧化物區域以轉換韋伯曲線⑴,韋伯曲線⑵會產 的產品。選擇電容器32的應力電壓及數目(N),以便使韋伯曲線 CDF1/N百分位係約為10年,第6圖係使用〇1%作為一實施例,但是百 为位可藉由没计者依元件使用期定義而有所改變。 -第三種測試結構50係監測電遷移下降,3^見在特別參閱第7圖,,·μ" 平行連接(最小寬度)金屬線52係將金屬線的一端連接到一共用的 路,在0_5到1.0倍的Vdd之間固定的應力電壓56,係被施加穿過開關器 58而到達金屬線52的另-端,應力霞係以金屬線52電阻及製造技術 為基礎而決定的。為了要感應一金屬線52故障,所以施加一感應電壓 60(通常為0.5倍的_)穿過開關器62而到達低電阻似的一端;此電阻 64的另-端雜在金屬線52上,金麟52係連接穿過關獅而到達 鎖存器的設定輸入。 金屬線52係藉由關閉開關器58同時打開開關器位及册而受到厣 力,且藉以施加應力電壓56。為了感應—金屬線52故障,所以將開^ 11 1281031 修正本 器58打開同時關閉開關器62及66,此會將感應電壓60施加穿過低電阻 64到複數個金屬線52。若金屬線52正確地運作(其係具有一低電阻) 時,則在輸入到鎖存器68的電壓將會為一邏輯"〇··(低),且鎖存器明的 輸出(使用期終點旗標)將會為"〇"(低)。在受到壓力期間單獨金屬線52 的故障(打開)會增加在剩餘線52的電流,而使它們有系統地打開。在 感應期間所有金屬線52的故障會藉由平行金屬線52的電阻大量增加而 監測到,藉以拉南鎖存器68的設定輸入到達一邏輯Π1"(高),且藉以設 定鎖存器68而產生一使用期終點旗標為一”1"(高)。 第8圖係顯示對數常態曲線(丨〇gn〇rma| p|〇t)的轉換,其係有用於設 計電遷移金屬線結構的應力電流及區域,在設計—種·_製程^ 產品的在晶片上電遷移監測電路中,會使用相似於TDDB設計的靜電策攀 略。必須以對數常態分佈參數(故障及形成參數的中間時間)為特徵,藉 由應力電流以轉換對數常態曲線⑴,第二對數常態曲線(2)會造成一 ^ 特別的製造技術。選顆力電流(藉由動電壓56而決定)及金屬線52 :數:⑽,以便使對數常態曲線(2)轉換的CDF(M_1)/M百分位約為1〇 元件Γ用Γ的用定一義種為一實施例’但是百分位係藉由設計者依 j明揭露-種用於在晶片上使用期終點指示器之方法 5 有效使用躺終點,其係有關於熱載體效應籲 件故障要更換。在實際元 喊更多的機構指示峨構的使用期= 二 術者能瞭解明之τ ’其目的在使熟習該技 應包含在以下所述之申請專利範^申斤7°成之纽修飾或修改,仍 【圖式簡單說明】 12 1281031 U由具體實施例配合所附的圖式詳加 ,正本 之目的、技術内容、特點及其所達成之功效。田更合易瞭解本發曰月. 第1圖係描述可靠度系統之方塊圖。 =2圖係描述用於決定何時已發生熱賴注人故 第3圖係顯示第1圖中系統之定時案例。 、…’鬼 係說明顯示第1圖降低的環振盡器之-較佳實施例。 Ϊ圖2f4(f係說明顯示第1財降低的環振奸之—較佳實施例。 第5圖係顯不使用期測試電路的TDDB終點之-較佳實施例。 =的係t一齡伯(WeibUH)曲線,係使用於決定在TDDB可靠度機I?81031 IX. OBJECTS OF THE INVENTION: TECHNICAL FIELD OF THE INVENTION The present invention relates to a method and apparatus for making a semiconductor, and determining the reliability in the manufacture of a special integrated circuit and using the end point of the steel semiconductor element 4 [Prior Art] (4) Specialized lion-knot lions in the forest species include the existence of inter-polar oxide collapse, electromigration, and stress-induced ribs. The ribs can be placed in the wire-like condition. The equivalent of the service circuit "year = two, the degree of success, its fine component voltage and electrical calculation and operation of the power cycle, these data are used to predict the circuit life of the circuit. ', μ - first! ^ and, the carrier is the main reliability wear mechanism of the VLSIf road, the heat carrier withstand capability of the CMOS process is due to the separate components, and the standard geometry of the component The shortened, produced and used. With Yu Lai Yu—therefore, using the current inference method to determine the simulation effect of the model heat carrier injection in the fruit VLS丨 component, the 4b complexity is true.] With the shortening of the design cycle, there is a short time. Foot:: Wei Cheng and the model heat carrier effect used for all process differences is - therefore 'have, to test the structural requirements, the system can be included in any element 1 ^ reach - Wei Ding _ when the slanting element Like the standard 代替2 instead of the die, it can be placed in the scribe line, the π in the initial grain area, and the _ parent product and Wei's explicit structure design, and can avoid 1281031 correction = inter-consumption And the reliability of the simulation of the work. Where the product is included, the reliability of the wafer is monitored to enable the _-component's end point and the component to be replaced. Other methods for determining the guilty factors have been found in U.S. Patent No. 5,875,665 ("_), a silk-guided method, which measures - (four) series of counter-compensation rises under conditions in which the family has the ability to weave money. Fall time and propagation delay. U.S. Patent No. 6,169,694 B1 (Nam et al.) teaches a method and a circuit for pre-firing a wafer on a wafer for DRAM devices, which is a method for making oxide film and capacitor failures. Patent No. 6,136,619 (Ceunindc et al.) describes a method for determining the resistance of a f-transformed charge in a conductor (four) and a method, and a single-current source can be applied to both the ί: ΐ and the It is placed close to the semiconductor die, and the direction of the current in the conductor structure is staggered to the high, and the conductor is tested at the off time. The current in the structure flows only in one direction, and the flow of the reference conductor structure by interleaving will eliminate the effect of electron migration, and the structure of the two structures can be reduced by the frequency and the red method and the method includes DC. The input is fresh to control a variety of test functions, including temperature and operating frequency. & [Summary of the Invention] The main purpose of the invention is to provide a method for monitoring the structure of money, including the heat carrier effect, _ oxide time dependent dielectric collapse (TDDB), and services. Another object of the present invention is to provide a circuit that is still due to the reliability mechanism. The purpose of monitoring the present invention is due to the relationship of the heat carrier effect, which is to provide a circuit for monitoring the reliability mechanism by the electrical collapse (T_ relationship). It is to provide a circuit due to the dependency mechanism. The purpose of the invention is to provide a reliability mechanism for indicating that the reliability mechanism to be monitored exceeds the pre-value before the failure of the active device. The day-to-day, thereby reducing the downtime of the system using the component. Pre-4 port 1281031 The correction bar uses three kinds of systems on the wafer, if any of the three test structures refers to the ^, ,, ° structure to achieve the above The target will be merged into the dry ir, "/I will be completed when the end of the fault period, and will be excluded from the system downtime when using lc. Mussels ^ Niu shot early river into the river. _ by the (four) reducer group clothing i read its own transistor, it will (lower ring vibrator), another fresh soup crying ^ heat carrier effect (four) 戸 α a clothing Zhen Meng is not Will go to the effect of heat carrier effect The oscillators each have a fixed frequency, and the f rate of the two frequencies is in the (four) lower gated binary count II, and is reset in another state. Just after the process, at each gate cycle, The binary counter will have a finite number of counts "I". With the reduced ring oscillator frequency due to the heat carrier effect below, at some point the binary counter will see less pulses applied, and the count The result will be "j" (its j<j), the designer will decide the difference.), the extent of the decline will show a sinful problem, and then if (H) more than one A certain degree of preset limit 'circuit will generate a signal of the end of the use period. The first / test structure is to monitor the decline of the gate oxide TDDB, a plurality of "η" parallel connected capacitors Having a stress voltage applied to it so that under normal use conditions, the 'faulty _ system fault has a small fraction of the time, the capacitance collapse is monitored by the difference in structural resistance and is used to trigger a bit Yuan indicates the use period signal TDD B. The second test structure monitors the electromigration drop, ·, Μ"the smallest width of the metal line is connected in parallel'. A current system is applied to it so that under normal use, the time of failure is somewhat small. Part of the time, the collapse of a metal line is monitored by the difference in structural resistance and is used to trigger a bit to indicate the end of the use signal electromigration end point. [Embodiment] 1281031 Correction Now refer to Figure 1, showing this Hairline Use - The system has three types of frames in the preferred embodiment of the present invention. The preferred embodiment of the present invention provides a test structure 30, and provides a test structure 30, and Depending on the dielectric breakdown (TDDB), there is a logic output. Each test structure (1〇, 30, 5〇) has ^. To reach the end of its useful use period, any of the - output - logic layer makes the indicator G, will lose the logic, (four) money 丨 c close to the scale and lose the dragon 1G health _ face down, said After the description, I am now special ΞΓ ΞΓ / 本 发 发 C 丨 结构 structure 1 (10) - better real compensation block diagram, ' ^ ^ reduced % vibrator 12 (which will not be affected by the heat carrier effect) and - drop , the ring oscillator 14 (which is affected by the heat carrier effect), the non-reduced ring oscillator ▲ 2 port non-reduced output signal a is applied to the - divider 彳 6, the frequency divider 1 is The binary 4 and the binary comparison n 20 provide the start signal 17, and the frequency of the start signal 17 is the non-reduced output signal 13 frequency fraction, which is known by the formula: f __ fNon-Degraded hn 2k~ k = 1, 2, 3, ..., the reduced output signal 15 of the reduced ring oscillator 14 is applied to the input of the binary counter 18. The multi-bit output 19 of the binary counter 18 is applied to the binary comparator 2 The output of the binary comparator 20 is supplied to the η CL lifetime end indicator 21. Referring now to Figure 3, the timing of the HCL test structure 1 第 of Figure 2 is shown. It should be noted that Figure 3 is merely an embodiment of circuit operation, and the actual timing varies as needed, and the display is non-reduced. The output signal 13 shows a reduced output signal 15 before the reduction on the left and after the decrease on the right. It should be noted that the frequency of the non-reduced output signal 13 and the reduced output signal 15 before the reduction is not required to be the same, but is the same in the operation of this embodiment. In this embodiment, the enable signal 17 (from the frequency divider 16) is one-eighth of the frequency of the non-reduced output signal 13. During its high period, the enable signal 17 provides the start of a binary counter. During its low period, the enable signal 17 resets the binary counter and initiates the function of the binary comparator 20. If the 1281031 correction is activated in response to the fault input limit when the binary counter 18 is activated, the multi-bit wheel will be reduced to "4" (01002) before lowering the output signal 15 (left). After the (right) multi-bit output 19 will only be, 3n (〇〇1〇2). During the low period of the enable signal 17, the comparator compares to a multi-bit output 彳9 against a fixed number (4 in this embodiment), and when the multi-bit output 19 is less than a predetermined limit At 4 o'clock, the signal of the end of life indicator 21 is issued. Then, when the το component is new, the binary counter 18 can be pulsed as a finite number of lowering ring oscillators 14 between each gated cycle, with a J = oscillation of the falling = as a function of the heat carrier effect. The frequency of the device 14 drops, the binary counter will appear at some point to apply = less pulse, and the final output count will be " factory (its kind. Binary comparator 2〇 will be designed as when the difference (jj) indicates In the case of a reliability problem, the circuit will produce an end point of the lifetime flag. The multiple pairs of inverting || of the zero 4a® towel can produce a reduced ring oscillator 4. To reduce the voltage across the component, Non-reducing ring oscillators can be fabricated, for example, similar to 4a, which use FETs with longer channel lengths. Stacked FETs can be used, for example, as shown in Figure 4b. Non-reduced ring oscillator for the towel. Figure 4c shows a non-reduced weaver of another type - a preferred embodiment using a current mirror to reduce the potential across each FET. The first test structure 3 〇 system monitoring gate oxide tddb Referring to Figure 5, a preferred embodiment of a circuit for determining the termination of a TDDB is provided by a complex, uncoupled capacitor 32, the plurality of capacitors H32 being arranged in series, and Connect f low resistance 34 to a common circuit. Apply a pressure voltage % through a switch 8' to a plurality of capacitors 32 and low resistance legs connected in series. The capacitor voltage is - a solid (four) voltage It is set at 丨c power supply voltage _)_ to 18 ports "depending on the manufacturing technology used. In order to sense - capacitor failure, apply a common pressure of 4 〇 (equal to Vdd) through a switch 42 To one end of the high resistance 44; the other one is connected to the latch 48 by a plurality of capacitors 32 connected in series and a plurality of resistors 32. The capacitors are connected to the latch 48. The 32 series is turned off by turning off the switcher and simultaneously turning on the switches 42 and 46. 10 1281031 / The correction is subjected to the pressure 'and the stress is applied 36. In order to sense the plurality of capacitors (4), the switch 38 is turned on and the switches 42 and 46 are turned off, This removes the stress voltage % and applies a gas voltage of 40. Excessive resistance 44 to a plurality of capacitors. If the capacitor % operates correctly (high resistance), then the voltage input to the latch 48 will be a logic ^48, the output (end of life end flag) will For "〇" (low). During sensing, the breakdown of the capacitance % is monitored by a plurality of resistor drops, thereby pulling the input to the latch (4) to logic (low), and the latch 48 The output (end of life flag) will show the conversion of Weber __ curve for the 6th figure, which is used to design the voltage and region of the complex structure of the td end point flag capacitor test, cumulative distribution function (cumulative distribution) Function, CDF) is selected as ·, the number of capacitors 2 is designed to be - a suitable special product and process on the wafer TDDB monitoring circuit 'target oxide region must be known, and must have Nabo The sub-parameters (the unique reduction and subtraction parameters are supplemented in Figure 6) are characterized by the stress voltage and the oxide region of the product to convert the Weber curve (1) to the Weber curve (2) product. The stress voltage and number (N) of the capacitor 32 are selected such that the Weber curve CDF1/N percentile is about 10 years, and the sixth figure uses 〇1% as an embodiment, but the hundred bits can be used. The change is based on the definition of the component's lifetime. - The third test structure 50 monitors the electromigration drop, see in particular, Figure 7, · μ" Parallel connection (minimum width) metal wire 52 connects one end of the wire to a common path, A fixed stress voltage 56 between 0_5 and 1.0 times Vdd is applied through the switch 58 to the other end of the wire 52. The stress is determined based on the resistance of the wire 52 and the manufacturing technique. In order to sense a metal line 52 failure, an induced voltage 60 (typically 0.5 times _) is applied through the switch 62 to a low resistance end; the other end of the resistor 64 is interspersed with the metal line 52, The Jinlin 52 series connects through the Guanshi and reaches the setting input of the latch. The wire 52 is subjected to a force by closing the switch 58 while simultaneously opening the switch bit and the book, and thereby applying a stress voltage 56. In order to sense that the metal line 52 is faulty, the open unit 11 is turned on and the switches 62 and 66 are turned off, which applies an induced voltage 60 through the low resistance 64 to the plurality of metal lines 52. If the wire 52 is operating correctly (it has a low resistance), then the voltage input to the latch 68 will be a logic "〇··(low), and the output of the latch is clear (used) The end of the flag will be "〇" (low). Failure (opening) of the individual wires 52 during compression will increase the current at the remaining wires 52, causing them to be systematically opened. The failure of all of the metal lines 52 during sensing is monitored by the substantial increase in the resistance of the parallel metal lines 52, whereby the set input of the pull-up latch 68 reaches a logic Π 1 " (high), and thereby sets the latch 68 The end-of-life flag is generated as a "1" (high). Figure 8 shows the conversion of the lognormal curve (丨〇gn〇rma| p|〇t), which is used to design the electromigration metal line structure. The stress current and area, in the design-type _ process ^ product in the on-wafer electromigration monitoring circuit, will use a static strategy similar to the TDDB design. Must be distributed in logarithmic normal parameters (fault and the formation of the middle of the parameters Time) is characterized by a stress current to convert the lognormal curve (1), and a second lognormal curve (2) results in a special manufacturing technique. Selecting the force current (determined by the dynamic voltage 56) and the metal line 52 : number: (10), in order to convert the logarithmic normal curve (2), the CDF (M_1) / M percentile is about 1 〇 component Γ Γ 用 用 为 为 为 但是 但是 但是 但是 但是 但是 但是 但是 但是 但是 但是 但是 但是 但是 但是According to J Ming, the type is used for the end of the use on the wafer. Point indicator method 5 Effective use of the lying end point, which is related to the heat carrier effect call failure to be replaced. In the actual yuan, more institutions are instructed to indicate the use period of the structure = the second operator can understand the τ's purpose The familiarity of the technique should be included in the modification or modification of the patent application method described below, and still [simplified description of the drawing] 12 1281031 U is detailed by the specific embodiment with the attached drawings, the original The purpose, technical content, characteristics and the effects achieved. Tian Gengyi understands this issue. Figure 1 depicts the block diagram of the reliability system. The =2 diagram description is used to determine when a hot note has occurred. Figure 3 shows the timing example of the system in Figure 1. [...] The description of the ghost system shows the reduced ring vibrator of Figure 1. The preferred embodiment is shown in Figure 2f4. Reduced Ring Attack - Preferred Embodiment. Figure 5 shows the TDDB endpoint of the unused test circuit - a preferred embodiment. The system is a WeibUH curve used to determine the TDDB. Reliability machine
第7圖係顯示使用細試祕的錢移終點之—較佳實施例。 第8圖係顯不一種對數常態曲線(丨〇gn〇rma| _),其係用於決定在 移可靠度機構中的參數。 【主要元件符號說明】 10熱载體注入(HCI)測試結構 12非降低的環振盪器 13分頻器 14降低的環振盪器 15降低的輸出訊號 16分頻器 17啟動訊號 18二進制計數器 19多位元輸出 20二進制比較器 21使用期終點指示器 30閘極氧化物時間相依介電崩潰(TDDB0、,j試結構 32電容器 36壓力電壓 13 1281031 修正本 38開關器 40感應電壓 44高電阻 46開關器 48鎖存器 50電遷移測試結構 52金屬線 56應力電壓 62開關器 66開關器 64低電阻 68鎖存器 70使用期終點指示器Figure 7 shows a preferred embodiment of the use of fine-tune money transfer endpoints. Figure 8 shows a lognormal curve (丨〇gn〇rma| _) that is used to determine the parameters in the shift reliability mechanism. [Main component symbol description] 10 hot carrier injection (HCI) test structure 12 non-reduced ring oscillator 13 frequency divider 14 reduced ring oscillator 15 reduced output signal 16 frequency divider 17 start signal 18 binary counter 19 more Bit output 20 binary comparator 21 use end point indicator 30 gate oxide time dependent dielectric collapse (TDDB0, j test structure 32 capacitor 36 pressure voltage 13 1281031 correction 38 switch 40 induced voltage 44 high resistance 46 switch 48 latch 50 electromigration test structure 52 metal line 56 stress voltage 62 switch 66 switch 64 low resistance 68 latch 70 use end point indicator
1414
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US10/243,392 US6724214B2 (en) | 2002-09-13 | 2002-09-13 | Test structures for on-chip real-time reliability testing |
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