JP3803343B2 - Semiconductor device evaluation method - Google Patents

Description

  The present invention relates to a semiconductor device evaluation method.

  Contacts and vias used in semiconductor devices are one of the important components, and evaluation of contacts and vias is one of the important evaluation items not only during development of semiconductor processes but also during mass production of semiconductor devices. It is. There are two things to evaluate for contacts and vias. The first is evaluation as to whether the contact resistance value of the contact or via is not high resistance as an initial characteristic. The second is an evaluation of whether the contact resistance value of the contact or the via is not higher than the initial value after the stress (temperature, current) acceleration test from the viewpoint of reliability.

  Conventionally, a test element group (TEG) has been used to evaluate an initial failure related to contact resistance of a contact or via (initial characteristic is high resistance) on a large scale for a large number of contacts or vias. SRAMs (Static Random Access Memory) and the above-mentioned conventional TEGs have been used as TEGs for evaluating contact or via reliability failures (high resistance after stress application) on a large scale.

A conventional TEG has a configuration in which an evaluation pattern is arranged on the entire surface of a reticle, and an evaluation method thereof will be described with reference to FIG.
FIG. 2A is a conceptual diagram illustrating a conventional resistance measurement circuit of a semiconductor device, and FIG. 2B is a flowchart illustrating a conventional semiconductor device evaluation method.

  2A shows a resistance measurement circuit configured by connecting a current source 702 and a voltmeter 703 to both ends of a resistance element 701 corresponding to a measurement target such as a contact chain or a via chain. Here, a contact chain is a structure in which a contact hole is formed at both ends of one diffusion layer, polysilicon conductor, etc., and many vias are connected in series with wiring such as aluminum, and a via chain has the same structure as a contact chain. However, it refers to a structure in which a contact hole connects metal wiring layers such as aluminum. The resistance value in this structure is the sum of the resistance value of the diffusion layer, polysilicon conductor, aluminum wiring, etc. and the contact resistance. As can be easily understood, the higher the number of connections in the chain, the higher the resistance. Show.

Next, a method of measuring the resistance element 701 such as a contact chain using the resistance measurement circuit having the above configuration will be described.
In FIG. 2B, first, a constant current I is applied to the resistor 701 by the current source 702 (step 7-a). Next, after waiting about 50 ms for the current to stabilize, the voltage V across the resistor 701 is measured by the voltmeter 703 (step 7-b). Next, the resistance R is calculated from the obtained voltage V and current I (step 7-c). Next, it is determined whether the resistance R is smaller than a preset standard Rspec (step 7-d). Finally, it is determined that R <Rspec is Pass (good), and R ≧ Rspec is Fail (bad) (step 7-e). The standard Rspec is, for example, the resistance value of the entire contact chain when the contact resistance has a low and good value that does not deteriorate the performance of the integrated circuit.

  Next, a method for evaluating a reliability defect related to contact resistance of a contact hole or via hole will be described. There are thermal stress and current stress as stress applied to contacts or vias.

  First, an evaluation method when heat stress is applied will be described. A large number of resistance measuring circuits having the configuration described in the conventional TEG are formed over the entire surface of the wafer, and the initial resistance value of the contact or via chain is measured. Subsequently, the wafer is stored in a constant temperature storage furnace and left for a predetermined time. Subsequently, the resistance value is measured again in the same manner as when the initial resistance value is measured. After that, constant temperature storage furnace storage and resistance measurement will be performed a specified number of times. When the transition of the resistance value of the same evaluation element, such as a contact or via chain, becomes higher than the initial resistance value by 10% or more, for example, the reliability is considered to be poor. In the reliability evaluation, the contact resistance of the contact holes constituting the chain is increased by applying a stress, and this increased amount appears mainly as a contribution to increasing the resistance of the entire chain.

Next, an evaluation method when current stress is applied will be described. Conventionally, in order to increase the evaluation scale of contacts or vias, the number of contacts or vias per evaluation element such as a contact or via chain is set to about 100k to 10M. Therefore, the resistance value of the entire chain is as high as about 1 M to 100 MΩ, and a current flows only about 50 nA to 5 μA even when 5 V is applied to both ends of the evaluation element. In the actual product, considering that a current of about 2 mA at the maximum flows through one contact or via, there is no point in evaluating reliability by applying current stress with a TEG such as a conventional contact or via chain. Only by operating the SRAM, it is possible to pass a current of about 200 μA to the contact or via, but even if this method is used, it is only 10% of 2 mA. The SRAM is used for contact or via evaluation because when the reliability failure occurs, the address of the failed memory cell is known, that is, the location of the failed contact is known. Conventional contact evaluation methods are described in, for example, Patent Documents 1, 2 and 3.
JP 63-33665 A JP 63-299358 A JP 07-86351 A

  However, in recent years, with the miniaturization of element patterns of semiconductor devices, the shapes of contacts and vias have been miniaturized, and the layout for connecting a plurality of conductive layers with a single contact or via has increased in order to increase the degree of integration. The number of contacts of this type reaches 5 million per chip. Also, if the number of contacts is 5 million, assuming that the incidence of defective chips due to contact failure is 1%, it is necessary to extract one defective contact from 500 million contacts, specify the location, and evaluate and analyze it. There is. Further, new structures such as new materials such as cobalt silicide and Cu, a SAC (Self Align Contact) structure, and a dual damascene structure have been adopted as wirings or a part thereof. For this reason, the manufacturing process becomes complicated, and there is a problem that evaluation analysis becomes difficult as the defect occurrence rate of contacts or vias increases.

  In order to solve the above-mentioned problems, it is necessary to evaluate contacts or vias in a shorter time than in the past, although the number of contacts and the number of vias is as large as possible. In addition, in response to an increase in wafer diameter, resistance variation per contact or via can be detected up to several tens of ohms due to the need to suppress variations in characteristics within the wafer surface and to check the operating margin of the semiconductor device. Evaluation methods are becoming essential. Further, in the reliability evaluation, it has become necessary to detect a contact or via whose resistance is increased to several kΩ.

  However, in the prior art, the resistance value per evaluation element such as a contact or via chain is as high as 1 M to 100 MΩ, and the resistance of the chain unless the resistance value of one contact or via is increased to 100 k to 10 MΩ or more. There was a problem that it could not be detected as a change.

  An object of the semiconductor device evaluation method of the present invention is to perform contact or via evaluation on a large scale in a short time and with high sensitivity.

To achieve the above object, method for evaluating a semiconductor device according to claim 1, wherein the present invention, a resistance element made of the measurement target, such benzalkonium Ntakuto chain or via chain one end of which is grounded, one end of which is grounded capacity and, inverters, the other end of the resistive element to the source terminal, a signal terminal gate terminal is configured to drain terminals in the switching MOSFET connected to the input terminal of the other end and the inverter of the capacitance of the resistive element In the measurement circuit for evaluating the resistance value, charging the capacitor with charge, and turning on the switching MOSFET with the signal terminal to discharge the charge charged in the capacitor via the resistor element ; The output signal value of the inverter after a predetermined time after the switching MOSFET is turned on is confirmed. And a step of, the resistance of the resistive element by the output signal value of the inverter is characterized by determining meets the standards.

  The semiconductor device evaluation method according to claim 2 is the semiconductor device evaluation method according to claim 1, wherein an output signal of the inverter is applied after the switching MOSFET is turned on for the resistance elements having various resistance values. An access time which is a time until inversion is obtained, and an access time standard and a resistance value standard are determined from the relationship between the resistance value of the resistance element and the access time.

According to a third aspect of the present invention, there is provided the semiconductor device evaluation method according to the first or second aspect, wherein a parasitic wiring capacitance is used as the capacitor.
As described above, the contact or via can be evaluated on a large scale in a short time and at a high sensitivity.

  As described above, a resistance element including a contact or via having the other end grounded is connected to the source terminal of the switching MOSFET, and an inverter and a capacitor grounded at the other end are connected to the drain terminal of the switching MOSFET for switching. MOSFET gate is connected to the signal terminal, and the inverter uses a resistance measurement circuit connected to the output terminal, and the resistance value of the resistance element including the contact or via from the inverter output value after a predetermined time after charging the capacitor By evaluating the above, it is possible to perform contact or via evaluation on a large scale in a short time and at high sensitivity.

  In order to solve the above problems, a semiconductor device evaluation method according to the present invention includes a contact or via chain connected as a resistance element whose other end is grounded to a source terminal of a switching MOSFET, and an inverter connected to a drain terminal of the switching MOSFET. And a capacitor grounded at the other end, the gate of the switching MOSFET is connected to the signal terminal, and the inverter performs the evaluation method described below in the resistance measuring circuit connected to the output terminal.

  First, charge is charged in the capacitor. Next, by turning on the switching MOSFET, the charge charged in the capacitor is discharged via the resistor. Subsequently, H and L of the output signal of the inverter are confirmed after a predetermined time since the switching MOSFET is turned on, that is, with respect to the standard time. Finally, when the output signal of the inverter is H (L), it is determined as Pass, and when it is L (H), it is determined as Fail.

  In addition, the access time standard and the resistance value standard can be determined by obtaining the relationship with the access time, which is the time when the output signal of the inverter is inverted after the switching MOSFET is turned on for contacts of various resistance values. .

In the circuit configuration described at the beginning, a wiring parasitic capacitance may be used as the capacitance.
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
A method for evaluating a semiconductor device according to the present invention will be described with reference to FIG.

  1A is a conceptual diagram illustrating a resistance measurement circuit of a semiconductor device according to the present invention, FIG. 1B is a conceptual diagram illustrating a signal state of the resistance measurement circuit of the semiconductor device according to the present invention, and FIG. FIG. 1C is a flowchart for explaining a semiconductor device evaluation method according to the present invention, and FIG. 1D is a diagram showing a relational expression between an access time and a resistance value by the semiconductor device evaluation method according to the present invention.

  In FIG. 1A, a resistance element 102 corresponding to an object to be measured such as a contact chain or a via chain whose other end is grounded is connected to the source terminal of the switching MOSFET 101, and the inverter 104 and the like are connected to the drain terminal of the switching MOSFET 101. A resistance measuring circuit having a configuration in which a capacitor 103 whose end is grounded is connected, a gate of a switching MOSFET 101 is connected to a signal terminal 107, and an inverter 104 is connected to an output terminal 106 is shown.

  Unit circuits 109 each including a switching MOSFET 101, a resistance element 102, and a capacitor 103 are arranged in a matrix (for example, 4k units = 64 × 64) to constitute one chip. The gate signal terminal 107 is connected to a row decoder (not shown) and a column decoder (not shown) as in the circuit configuration of a normal semiconductor memory device, and can turn on the switching MOSFET 101 of an arbitrary address. . The inverter 104 is configured to be connected to all 4k unit circuits 109 through a common node 105. As the capacitor 103, a parasitic capacitance of a wiring can be used.

  Next, each signal in FIG. 1B will be described by focusing on a certain unit circuit 109. Signal 121 is a signal input to gate signal terminal 107, signal 122 is a signal indicating a change in potential of node 105 when resistance element 102 such as a contact or via chain has a normal resistance value, and signal 123 is a resistance element. A signal indicating a change in potential of the node 105 when the resistance of the node 102 is increased. The signal 125 is inverted by the signal 122. The output 106 of the inverter 104 set so as to be inverted at half Vdd / 2 with respect to the power supply voltage Vdd. The signal 126 is a signal obtained by inverting the output 106 of the inverter 104 by the signal 123 so as to be inverted at Vdd / 2 that is half of the power supply voltage Vdd. The access time 127 and the access time 128 are times from when the signal 121 becomes “H” to when the output 106 becomes “H”. The access time 128 when the resistance value of the resistance element 102 is high is longer than the access time 127 when the resistance value of the resistance element 102 is normal. This is because the higher the resistance value of the resistance element 102, the longer it takes for the charge stored in the capacitor 103 to escape to ground.

  FIG. 1D shows the relationship between the access time 127 or the access time 128 and the resistance value of the resistance element 102. As the resistance value of the resistance element 102 increases, the access time increases.

Next, an evaluation method of the semiconductor device (resistance element) according to the embodiment of the present invention in the resistance measurement circuit having the above configuration will be described with reference to FIG.
First, in an array in which unit circuits 109 are arranged in a matrix, addresses are fixed to, for example, a unit circuit having the smallest address arranged at the end of the array. The capacitor 103 is charged until the charge reaches Vdd (step 1-a). Next, the signal 121 is input to the signal terminal 107 to turn on the switching MOSFET 101 (step 1-b). Next, the level of the output signal 106 is confirmed at the timing of the preset access time standard time 129 (step 1-c). Here, for example, when the resistance element 102 is a contact chain, the access time standard time is an access corresponding to an allowable resistance value that is determined to have a good value that is low enough not to deteriorate the performance of the integrated circuit. The lower the contact resistance value, the lower the resistance of the entire chain and the shorter the access time. Next, when the output signal 106 is “H”, it is judged as Pass, and when it is “L”, it is judged as Fail (step 1-d). Next, it is determined whether the address of the unit circuit just measured is the last address (the unit circuit to be measured last in the array arranged in a matrix). If it is the last address, the process ends and the last address If not, the address is fixed to the next address (step 1-a) and the process returns to step 1-e.

  With the above evaluation method, 80 k contacts or vias can be measured in 4 ms. The scale of 80k evaluation contacts or vias is achieved by arranging 4k resistive elements 102, which is a chain including 20 contacts or vias, in a matrix on one chip. The measurement time of 4 ms is based on the time required for one resistance measurement in consideration of the time required for unit circuit address selection, unit circuit address position determination, etc., when the access time standard time 129 is 50 ns when measuring with a memory tester. In the case of 1 μs, it is the time taken to repeat 4k times to measure one chip. The access time standard time 129 is set as follows, for example. The resistance value that is twice the design resistance value (200 Ω for 20 contacts included in one contact chain when the resistance value of one contact is 10 Ω) is defined as the standard resistance value, and the relationship shown in FIG. An access time standard time 129 is set.

  On the other hand, the time required to evaluate 80k contacts or vias by the conventional evaluation method is about 50 ms. This is because current is applied and voltage is measured to measure the resistance, and it is necessary to wait for about 50 ms for the current to stabilize before measuring the voltage. The evaluation method according to the present embodiment can measure 12 times faster than the conventional method. Furthermore, if the resistance of one contact or via is 10Ω, the resistance of 10Ω × 80k = 800 kΩ must be measured with the conventional method, whereas the resistance of 200Ω is measured with the method of this embodiment. . If it is possible to detect a resistance value exceeding 10% of the normal resistance value as an abnormality, it is detected when a resistance rise of 80 kΩ or more occurs in one contact or via in the method of this embodiment, in the case of the conventional method. Will be. The detection sensitivity of a contact or via exhibiting abnormal resistance is three orders of magnitude higher in the measurement evaluation method according to this embodiment than in the conventional method.

  As described above, by improving the sensitivity for detecting abnormal contacts or vias by three orders of magnitude, it becomes possible to analyze a contact resistance failure that could not be detected by the conventional method. In this way, it is possible to identify yield factors and take countermeasures to improve yield and reliability.

  The evaluation method of a semiconductor device according to the present invention has an effect that the evaluation of a contact or via can be performed in a short time and with high sensitivity even though the evaluation is large, and the evaluation method of a semiconductor device, etc. Useful as.

(A) Conceptual diagram for explaining a resistance measurement circuit of a semiconductor device according to the present invention (b) Conceptual diagram for explaining a signal state of a resistance measurement circuit of a semiconductor device according to the present invention (c) Evaluation of a semiconductor device according to the present invention (D) A diagram representing a relational expression between an access time and a resistance value according to the semiconductor device evaluation method of the present invention. (A) Conceptual diagram for explaining a resistance measurement circuit of a conventional semiconductor device (b) A flowchart for explaining a conventional semiconductor device evaluation method

Explanation of symbols

101 MOSFET for switching
DESCRIPTION OF SYMBOLS 102 Resistive element 103 Capacity 104 Inverter 105 Node 106 Output terminal 107 Signal terminal 109 Unit circuit 121 Signal 122 Signal 123 Signal 125 Signal 126 Signal 127 Access time 128 Access time 129 Access time Standard time 701 Resistive element 702 Current source 703 Voltmeter

Claims (3)

A resistive element having one end consisting of benzalkonium Ntakuto chain or via chain such as the measurement target is grounded, and a capacitor whose one end is grounded, the inverter and the other end of the resistive element to the source terminal, a gate terminal signal terminal, the drain In a measurement circuit configured to evaluate a resistance value of the resistance element , which is configured with a switching MOSFET that connects a terminal to the other end of the capacitor and an input terminal of the inverter,
Charging the capacitor with a charge;
A step of turning on the switching MOSFET by the signal terminal and discharging the charge charged in the capacitor via the resistance element ;
A step of confirming an output signal value of the inverter after a predetermined time after the switching MOSFET is turned on, and determining whether a resistance value of the resistance element satisfies a standard based on the output signal value of the inverter A method for evaluating a semiconductor device.   The access time, which is the time from when the switching MOSFET is turned on to the inversion of the output signal of the inverter, is obtained for the resistance elements having various resistance values, and the relationship between the resistance value of the resistance elements and the access time 2. The method of evaluating a semiconductor device according to claim 1, further comprising a step of determining an access time standard and a resistance value standard from the following.   The semiconductor device evaluation method according to claim 1, wherein a wiring parasitic capacitance is used as the capacitance.

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