TWI280635B - Memory element, array of memory cell, method of forming contact structure and apparatus and semiconductor device produced by the method - Google Patents

Memory element, array of memory cell, method of forming contact structure and apparatus and semiconductor device produced by the method Download PDF

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TWI280635B
TWI280635B TW93135393A TW93135393A TWI280635B TW I280635 B TWI280635 B TW I280635B TW 93135393 A TW93135393 A TW 93135393A TW 93135393 A TW93135393 A TW 93135393A TW I280635 B TWI280635 B TW I280635B
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Taiwan
Prior art keywords
contact structure
memory
contact
layer
shaped
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TW93135393A
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Chinese (zh)
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TW200618171A (en
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Ming-Hsiu Lee
Rui-Chen Liu
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Macronix Int Co Ltd
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Publication of TWI280635B publication Critical patent/TWI280635B/en

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Abstract

Contact structures having I shapes and L shapes, and methods of fabricating I-shaped and L-shaped contact structures, are employed in semiconductor devices and, in certain instances, phase-change nonvolatile memory devices. The I-shaped and L-shaped contact structures produced by these methods exhibit relatively small active areas. The methods that determine the contact structure dimensions employ conventional semiconductor deposit and etch processing steps that are capable of creating readily reproducible results.

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1280635 12300twf.doc/g 九、發明說明: 【發明所屬之技術領域】 本發明是有關於半導體元件及其製造方法,且特別是 有關於用於相變型記憶元件之接觸結構的製造方法、含^ 種接觸結構之記憶體元件及記憶胞陣列,以及使用該方法 所製造的電子裝置與半導體元件。 ‘ 【先前技術】 固悲§己憶體元件係廣泛使用於電子學領域中。典型的 记憶體包括動態隨機存取記憶體(DRAM)、靜態隨機存取 記憶體(SRAM)、唯讀記憶雖QM)、可絲可程式唯 k、體(EPROM)、可電除可程式唯讀記憶體(E2pR〇M)及快閃 1憶體等,其可區分為揮發與非揮發記憶體兩大類。 E PROM等鱗發記㈣的主要構件基本上為具浮置閑的 場效電晶體,而在程式化任—記憶位元時,電荷係存入場 效電晶體的料财。然而’此類記,隨的可再程式化次 數有限,且其程式化速度也可能相當低。另外,雖缺 咖0M、E2PR0M及快閃記憶體的記._ 不居進订貝料更新㈣eshing)’但與揮發性的dram元件 =下,其尚有儲存密度較低,尺寸較大及製造成本較高 且已有由相變型記憶胞所構成,可隨機存取且 存型記憶胞不同。本文中「記憶材料」-細曰可□外界刺激而產生結構相變的材料,例如是硫族 1280635 12300twf.doc/g (chalcogenide)材料等相變㈣。 情 -結構狀態與通常在通常為非晶相之第 土 4 ^,兩、、、〇b日相之第二結構狀態之間以電切換 料也可能可衫全非晶態到完全結晶態 間夕個不_局°卩有序狀態之m讀,只要处狀能可以 1區別即可。這些材料亦具有真正的轉發 結晶相、半結晶相、非晶相或半非晶相^具 電阻值。此電阻值可—直轉到其被重設之前, 而可代表此材料的物理狀態,如結晶 由於相變型記憶材料有頗大的電阻變化 上可容許纽福二雜資·存在單—記馳中。達此 目的的可能做法,即是以類比方式為二進位資訊編碼,將 -段被編碼的二進位資料的多個位元對應至多個不同電阻 值中的-個,再據以程式化單-記憶胞。如此,相變型記 憶體之操作即可如同傳統的二進位記憶體,或如同進位數 大於2的記憶體。 適合用作相變記憶材料的典型材料包括各種含硫族材 料。用作相變記憶材料的典型含硫族材料例如可含有碲 (Te)、石西(Se)、鍺(Ge)、銻(Sb)、叫Bi)、錯(pb)、錫(Sn)、 石申(As)、硫(S)、矽(Si)及磷(P)中的至少一者與/或氧。此種 非揮發記憶體元件例如可使用一整塊的硫族材料來製做, 且至少在理論上,製得之記憶體結構可僅以很小的晶片面 積來儲存一位元的資料,故可得本質上高密度的記情 然而,相變型記憶體元件等固態記憶元件(s〇lid_state 1280635 12300twf.doc/g1280635 12300twf.doc/g IX. Description of the Invention: [Technical Field] The present invention relates to a semiconductor device and a method of fabricating the same, and more particularly to a method of fabricating a contact structure for a phase change memory device, comprising A memory element and a memory cell array of a contact structure, and an electronic device and a semiconductor element manufactured using the method. ‘ 【Prior Art】 Solid and sufficiency components are widely used in the field of electronics. Typical memory includes dynamic random access memory (DRAM), static random access memory (SRAM), read-only memory (QM), configurable only k, body (EPROM), and electrically erasable Read-only memory (E2pR〇M) and flash 1 memory, etc., can be divided into two major categories of volatile and non-volatile memory. The main components of E PROM and other scales (4) are basically floating-effect field-effect transistors, and in the case of stylized any memory bits, the charge is stored in the field-effect transistor. However, such a record can be reprogrammed in a limited number of times, and its stylization speed can be quite low. In addition, although the lack of coffee 0M, E2PR0M and flash memory notes. _ not in the order of the shell material update (four) eshing) 'but with the volatile dram components =, it still has a lower storage density, larger size and manufacturing The cost is high and has been composed of phase change memory cells, which can be randomly accessed and stored in different memory cells. In this paper, "memory material" - a material that can cause structural phase transitions due to external stimuli, such as phase transitions such as chalcogen 1280635 12300 twf.doc/g (chalcogenide) materials (4). The state-structure state is usually between the second structural state of the fourth phase, the normal phase of the amorphous phase, and the second structural state of the daytime, the electrically-switched material may also be between the fully amorphous state and the completely crystalline state. The evening is not _ bureau ° 卩 orderly state m read, as long as the shape can be 1 difference. These materials also have a true transmissive crystalline phase, semi-crystalline phase, amorphous phase or semi-amorphous phase with resistance values. This resistance value can be - directly before it is reset, and can represent the physical state of the material, such as crystallization. Due to the considerable resistance change of the phase change memory material, it can be tolerated by Newfoundt II. in. A possible way to achieve this goal is to encode the binary information in an analogy manner, and to map a plurality of bits of the encoded binary data to one of a plurality of different resistance values, and then to programmatically- Memory cell. Thus, the phase change type of memory can be operated as a conventional binary memory or as a memory having a carry value greater than two. Typical materials suitable for use as phase change memory materials include various sulfur-containing materials. Typical chalcogenide materials used as phase change memory materials may, for example, contain cerium (Te), tar (Se), cerium (Ge), strontium (Sb), Bi), erbium (pb), tin (Sn), At least one of and/or oxygen of Ashen, sulfur (S), strontium (Si), and phosphorus (P). Such a non-volatile memory component can be fabricated, for example, using a monolithic chalcogenide material, and at least in theory, the resulting memory structure can store one bit of data with only a small wafer area, Obtaining essentially high-density sensation, however, solid-state memory components such as phase-change memory components (s〇lid_state 1280635 12300twf.doc/g

讀nor^leviee)的共同特性即是其高耗電量,特別是在( 設定記憶體兀件時。即使在構件 CO 耗電量仍是不顺重要課題尺==;力 胞(P_Cell)供電的可攜式|置中。因此,如二 體元件的耗電量—直是須優先處理的問題。&amp; 炉材料之讀、胞時,必須使—電流脈衝通過 的貝難u邊It體元件的場電壓、電流及電力的大 ^應他IkTG件大小及接觸窗面積而改變,使得較小的接觸 自可以相應之較低的耗電量產生較小的絲區。以習知的 半,體製造技術製做硫族記憶體元㈣,可達到的最小接 觸窗尺寸係受限於微影機台。對此種元件與許多尖端半導 體技術的整合而言,如此尺寸可能會使娜電流、電壓過 大或切換時間過長’並使循環使用壽命過短。此外,習知 =石二私體製造方法常無法有效率且可靠地製造大型記 憶7〇件所需的全體一致的記憶體元件。 处因此,業界亟須尺寸縮減之記憶體接觸窗的結構,以 及月b夠可罪地製造相變型記憶體元件之接觸窗的方法,使 種記憶體元件程式化所需電力得崎低,並得其他優點。 【發明内容】 為因應前述需求,本發明提出I形及L形的接觸結構, /y、V體層的介面有相當小的截面積(或謂接觸區)。此種工 形及L形接觸結構的材質可為導電材料或記憶材料。 1280635 12300twf.doc/g 本發明例如是在半導體元件領域上可錢進—步的應 =,因其提供製造超小接觸㈣方法,而可進—步縮小半 導體元件的尺寸。此外,在本發明之製造方法中,每一個 接觸區僅财—支撐結構(職定義)的—側,而可有較佳 規則及較寬的製程裕度,且沒有任何無用的結構。 變^之實施例巾,記憶材料可能包括硫雜料之類的相 刻4發ΪΪίί係使用半導體製造領域熟知的沉積與餘 法^叮/、可合易地重覆產生相當一致的製程、结果。本方 Ϊ:= 自行對準於接觸結構的頂電極,而形成自行對 影,^ ^形接觸結構陣列。此特性即可進—步增加微 線的^立&amp;又_\此外,由於支撐結構的間隔(pitch)為位元 ' ,°不έ過小,故支撐結構的钮刻製程容易控制。 法/Γ 月之—實施例提出一種1形接觸結構及其製造方 面,’ 制彡成在置於基底上之技結構的側 窄县古#貝σ蛉電材料或§己憶材料。接觸結構的剖面呈 方式Γ 其與英*字母”1,,或”1,,相似,且將在稍後 「實施 χ」邛匀中以圖式輔助說明。 法 ,^明另—實施例提出-種L形接騎構及其製造方 面,i材構㈣成在置於基底上之支#結構的側 具足部的。2電記憶材料。接觸結構的剖面呈 「實於方形,其與央文字母”L”相似,且亦將在稍後 、ι =式」部分中以圖式辅助說明。 本么明再另—實施例包括一種記憶體元件,其包括置 1280635 12300twf.doc/g 本實施例更包括至少有部分置於 形或L形接觸結構,其配置方式係使 4二二可払作性地耦接。本實施例更包括例如是相變型材 其至少有部分配置於1形或l形接 材料於作作性地缺。另有—頂導電構件與記憶 一:、*乍也麵接’而此記憶體元件更可包括-電晶體或 一極體,以作為存取元件。 一 $明之—實例包括至少有部分形成在基底内的記憶 凡=陣列’其係排列成行列狀,而記憶體元件則在行與 列的交會處。其中,每_個記憶體元件皆包括—存取元件, 其係使义饫體元件耦接至列走向的一條底導電構件。 此處須特別說明的是,雖然前述及下文的元件/裝置及 方法係藉功能性說明以便描述,但本發明之申請專利範圍 並不受方法/裝置或步驟」等用詞的限制,而是依照均等論 所容許的完整範圍加以界定者。 為讓本發明之上述和其他目的、特徵和優點能更明顯 易懂’下文特舉較佳實施例,並配合所附圖式,作詳細說 明如下。 【實施方式】 以下將詳細說明本發明之較佳實施例,其實例係繪示 於附圖中;而在圖式及說明文中,相同或相似的部分已盡 可能以相同或相似的標號來標示。另外,請注意所有圖式 皆已經過簡化,其尺寸比例並不一定精確。同時,為方便 清楚地描述本實施例,下文中係使用如頂、底、左、右、 1280635 12300twf.doc/g 上、下、在上、在下、前、後等方 耕 本發明之範圍。 應被解釋成疋在以任何方式限制 而非^ ^ 的_實施例’但其僅為範例 非限制’亦即’ T文雖僅討論實蘭,但騎可被解釋 成是涵蓋該些實施例__、顿淑㈣例,口要 在申請專職_界定之本發明翻内。另請了解 ίί製结構並未涵蓋製做記憶材料胞的完整製造 4。本發明亦可與業界常用的各種1C製造技術一同施 =甘,其巾只有可令本發日収科了解的常用製程步驟才 明。—般錢,本發财半導體元件與製程的領域 白有其制L為作清楚的綱,下文主要說明的是 相變記憶材料記憶㈣、域胞,以及主動面積較小的 I形或L形接觸結構的製造方法。 請進一步參照圖式,圖卜)係繪示本發明的背景技 術、,圖4A及4B為本發明實施例之記憶胞的立體圖/圖5 之流程@制以制製造〗形及L形翻結構之記憶胞的 ,明步驟,其中接觸結構係由導電材料或記憶材料製成。 這些步驟係繪示於圖7〜25B中,但圖25A/B之結構係以電 晶體作為存取元件,而非二極體。 凊參照圖1,其係晶圓10 (例如是半導體晶圓)的平面 圖,其上可能形成有一或多個積體電路,且可分割為多個 W晶方12,其將可被封裝成1(:晶片。圖2為包含記憶元 件之基板的示意方塊圖,此記憶元件係位在晶方12的部分 1280635 12300twf.doc/g 區域中,且此晶方12可包含—IC記憶體。記憶 括一或多個記憶陣列20。此繪示之記憶陣列=14可包 18耦接至控制電路16。此控制電路16係選 糸以導線 適當的行及列座標以存取記憶陣列2〇,而得以所+繪之 圖3為依本發明實施例之方法所製做之 寫。 的圖2記憶胞陣列20的―部分的電路簡圖;=斤構成 Μ基本土包括許多記憶胞22,其—般排列成垂^陣列 ί線其24中母:行f憶胞22基本上共用一電性連接,即It 瓜線24,母-列記憶胞22基本上共用—電性 P位 字元線26。在典型的實施方式中,每一位元線 ,導電構件形成’且每-字猶26係由—頂導電構_ f。如此領域所知者,圖2之控制電路16係選擇對 2f=來啟動對應之存取元件,藉此讀寫每-個二I: 22。此存取兀件可能包括電晶體或二極體。 · 圖]為本發明實施例之記憶胞形成方法的流程圖。此 摘由導電或記憶材料製成的!形或l形接觸結 構,且以二極體作為存取元件。 ^驟3〇—開始即提供一底導電構件,其依後續操件來看 二二iTC線1圖5方法製造之記憶胞的實施例顯示 j A ’其中底導電構件2〇(M系作為位元線。形成此底導 電構件2GG (步驟3G)的製程步驟綠示於圖6〜9中。 步驟35係、形成一存取元件,其在所緣實施例中係由第 曰摻雜石夕材225與第二層摻雜石夕材25〇所構成之二極體 子取元件,且其形成步驟綠示於圖〜Μ中。 11 1280635 12300twf.doc/g 接著,材質可包括導電材料的j形接觸結構4〇〇可以 二驟4〇〜65形成’其係繪示於圖16〜18及19A、20A、21A ί形接觸結構_形成後’即以步驟7㈣形成記 ’巧料”頂導電構件(即字元線〕。舉例來說,如下文將詳 二=to *於支樓結構上沉積導電材料(例如呈薄膜狀) 的v &amp; 50及後續步驟55〜65完成之後驟〇成 憶材料或硫族材料等相變型記憶㈣_,如圖糸2开;^ 不L接者,步驟75沉積頂導電構件700的材料’如圖23A 所不。形成導電材料之1形導電結構_的另—選擇,則 2如t:I0:100般形成材質包括記憶材料的1形接觸結 構’其亚未坪細繪於圖式中。 广墓iliG5係圖2情示之侧步驟,其係圖案化糊 m2r以上的各層,以形成字元線與記憶胞。 棚二似之立體圖,除其中1形導電結構 另一實施例,其—開二: ^籌件200 (步驟30) ’如圖6〜9所示。接著如同圖4A之 層摻雜石夕材225與第二層摻雜石夕材250 以構成-極體存取元件(倾切,如圖lb所示。牛 40〜65係形成L形導電結構_,如圖16〜18及/ 20Β、21Β所示,其材質例如包括一導電材料。 牛 材料或硫族材料等相變型記憶材料_,二 圖22Β所示’下一步驟75則沉積頂導電構件·的材料, 如圖23Β所示。再者,如同ζ形接觸結構_的情形,l 12 1280635 12300twf.doc/g 形接觸結構働亦可依步驟8G〜⑽改以記憶材料或相變 材料形成,而非導電材料。接著,進行圖24繪示之蝕刻井 驟(步驟105 )’目案化繼刻底導電構件2〇〇以上的各/ 以形成字元線與記憶胞。 &quot; 底導電構件與二極體存取元件的形成步驟係 6〜15為輔作說明。特別是,圖6為其上沉積有第-氧化居 1—50 (如二氧切層)的半導體基板148的剖面圖,圖7則二 一氧化層150的多個部分以習知微影蝕刻 形成溝渠175的情形。圖8綠示圖7 :==形成在第一氧化層15°_。)。= 二夕、複晶石夕、鶴、銅、銘銅合金 銅曰金或其組合,或是其他類似材料。 姓法ί ϋ示圖8結構中第一層導電材料的多個部分以回 姓法或CMP去除,而滅$第—氧化層15 ==情形。此步驟係產生可作為記憶陣列之位i缘ί 底導電構件2〇〇。 干ami兀、尿的 雜石夕導電構件200上形成第一層換 225上开,成/ H 圖11所示’於第一層摻雜石夕材 中,第^^ 材25G (步驟35)。在所繪實施例 g払雜矽材225的材質包括N-換 度例如約l〇i5〜1〇17/ 3 · 杉雊矽,其摻貝/辰 括P+摻雜石夕,1换所、曲 層換雜石夕材250的材質包 /、夕’其摻質浪度例如約1〇18〜1〇2〇 3 請參照圖12,其繪示圖U处構中楚⑽。 口 、、、°構中弟二層與第一層摻 13 1280635 12300twf.doc/g 雜石夕材250與225被餘刻成二極體存取元件(步驟玢的产 形’此存取元件係與底導電構件2〇〇操作性地接觸二 改的實施例中,亦可以N/P/金屬(225/25咖_ : 述P婦屬⑽/225/200)結構。P或N摻雜石夕 可變化以得南整流比(rectiflcati〇n加1〇)及高電流密度,並 使其兩端,低接觸電阻。雖然、此處所示者為二ϋ,但 在修改之實施例中亦可適用他種存取元件,例如是金氢 (MOS)元件等,但不限於此。 ”礼干 圖13為圖12結構的上視圖,而圖12為圖13的12_12, 剖面圖。接著如圖14所示,在蝕刻後的第一層鱼第二層摻 雜石夕材225與250上形成—層第二氧化材料、275 (^驟 35) ’其例如是包括以CVD形成的二氧化矽。接下來可對 圖14結構進行CMP或回蝕製程,以移除第二氧化材料奶 至第一層摻雜矽材250露出為止,藉以形成圖15之結構。The common feature of reading nor^leviee is its high power consumption, especially when setting the memory component. Even if the CO power consumption of the component is still not important, the ruler ==; the power cell (P_Cell) power supply Portable type; therefore, the power consumption of the two-body component is a problem that must be prioritized. &amp; The reading of the furnace material, the cell must be made - the current pulse passes through the shell The field voltage, current, and power of the component vary depending on the size of the IkTG component and the contact window area, so that a smaller contact can produce a smaller wire area from a correspondingly lower power consumption. The body manufacturing technology makes the chalcogen memory element (4), and the minimum contact window size that can be achieved is limited by the lithography machine. For the integration of such components with many cutting-edge semiconductor technologies, such a size may cause the current. The voltage is too large or the switching time is too long' and the cycle life is too short. In addition, the conventional = stone two private manufacturing method often cannot efficiently and reliably manufacture all the consistent memory components required for large memory 7-pieces. Therefore, the industry does not need to be reduced in size. The structure of the contact window and the method of manufacturing the contact window of the phase change memory element are sinful, and the power required for stylizing the memory element is low, and has other advantages. In view of the foregoing needs, the present invention proposes an I-shaped and L-shaped contact structure, and the interface of the /y and V-body layers has a relatively small cross-sectional area (or a contact area). The material of the shape and the L-shaped contact structure can be electrically conductive. Materials or memory materials. 1280635 12300 twf.doc/g The present invention is, for example, a cost-effective step in the field of semiconductor devices, as it provides a method of fabricating ultra-small contacts (4), which can further reduce the size of semiconductor components. Further, in the manufacturing method of the present invention, each contact area is only the side of the support structure (professional definition), and there are better rules and a wider process margin, and there is no useless structure. In the embodiment of the invention, the memory material may include a phase of sulphur, such as sulphur, which is a well-known process in the field of semiconductor fabrication, and a reproducible method to produce a process that is fairly consistent. Ϊ:= Align yourself to the top electrode of the contact structure to form a self-aligning, ^^-shaped contact structure array. This feature can be used to increase the number of microwires and/or _\ in addition, due to the support structure The pitch is a bit ', and the angle is not too small, so the button engraving process of the support structure is easy to control. Method / Γ Month - The embodiment proposes a 1-shaped contact structure and its manufacturing aspect, 'the system is placed The structure of the structure on the base of the narrow county ancient #贝σ蛉 electric material or § recall material. The cross section of the contact structure is in the same way as the English * letter "1,, or "1,", and will be later "Implementation χ" 邛 中 以 以 以 辅助 。 。 法 法 法 法 法 法 法 法 法 法 法 法 法 法 法 法 法 法 法 法 ^ 法 法 法 法 ^ ^ ^ ^ ^ ^ ^ ^ ^ 实施 实施 实施 实施 实施With feet. 2 electrical memory materials. The section of the contact structure is "real square", which is similar to the letter "L" of the central text, and will be explained by a pattern in the later part of the "ι = formula". The present invention further includes an embodiment comprising a memory element comprising: 1280635 12300 twf.doc/g. The embodiment further comprises at least a partial placement or L-shaped contact structure configured in such a way that the Couplingly coupled. This embodiment further includes, for example, a phase change profile which is at least partially disposed in a 1- or 1-jointed material. In addition, the top conductive member and the memory one: , *乍 are also interfaced' and the memory element may further include a transistor or a pole body as an access element. An example - the memory includes at least a portion of the memory formed in the substrate. The arrays are arranged in rows and columns, and the memory elements are at the intersection of rows and columns. Each of the memory elements includes an access element that couples the metaphysical element to a bottom conductive member of the column. It is to be noted that, although the foregoing and the following elements/devices and methods are described by way of a functional description, the scope of the invention is not limited by the terms of the method, the device, or the steps, but rather Defined according to the full scope allowed by the theory of equalization. The above and other objects, features, and advantages of the present invention will become more apparent <RTIgt; DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT OF THE INVENTION The preferred embodiments of the present invention will be described in detail in the accompanying drawings. . Also, please note that all drawings have been simplified and their size ratios are not necessarily accurate. Meanwhile, the present embodiment is clearly described for convenience, and the scope of the present invention is hereinafter employed using top, bottom, left, right, 1280635 12300 twf.doc/g upper, lower, upper, lower, front, and rear. It should be construed that the embodiment is limited in any way and not ^^ but it is merely exemplary and non-limiting, that is, the T text only discusses the real, but the ride can be interpreted to cover the embodiments. __, Dun Shu (four), the mouth should be in the application for full-time _ defined by the invention. Please also understand that the structure of ίί does not cover the complete manufacture of memory cells. The invention can also be applied together with various 1C manufacturing techniques commonly used in the industry, and the towel can only be used in the usual process steps which can be understood by the present day. As for the money, the field of semiconductor components and processes of the company is clearly defined. The following mainly describes the memory of the phase change memory material (4), the domain cell, and the I or L shape with a small active area. A method of manufacturing a contact structure. Further, referring to the drawings, FIG. 4B shows the background art of the present invention, and FIGS. 4A and 4B are perspective views of the memory cell of the embodiment of the present invention/the flow of FIG. 5 to manufacture the shape and the L-shaped structure. A memory cell, in which the contact structure is made of a conductive material or a memory material. These steps are illustrated in Figures 7 through 25B, but the structure of Figure 25A/B uses a transistor as the access element rather than a diode. Referring to FIG. 1, which is a plan view of a wafer 10 (eg, a semiconductor wafer), one or more integrated circuits may be formed thereon, and may be divided into a plurality of W crystals 12, which may be packaged into 1 (: wafer. Fig. 2 is a schematic block diagram of a substrate including a memory element which is located in the portion 1280635 12300 twf.doc/g of the crystal 12, and the crystal 12 may include - IC memory. One or more memory arrays 20 are included. The illustrated memory array=14 can be coupled to the control circuit 16. The control circuit 16 selects the appropriate row and column coordinates of the wires to access the memory array 2〇, Figure 3 is a schematic diagram of the method according to the embodiment of the present invention. Figure 2 is a schematic diagram of a portion of the memory cell array 20; = kg constitutes a basic earth comprising a plurality of memory cells 22, Generally arranged in a vertical array ί line its 24 mothers: row f memory cells 22 basically share an electrical connection, that is, the melon line 24, the mother-column memory cell 22 is basically shared - the electrical P-bit word line 26. In a typical embodiment, each bit line, the conductive member forms 'and each word is 26-by-top lead Structure _ f. As is known in the art, the control circuit 16 of Figure 2 selects the pair of 2f = to activate the corresponding access element, thereby reading and writing each of the two I: 22. The access element may include electricity. Crystal or diode. Fig. 1 is a flow chart of a method for forming a memory cell according to an embodiment of the present invention. This is an ! shape or an l-shaped contact structure made of a conductive or memory material, and a diode is used as an access element. ^ 〇 3〇—Beginning to provide a bottom conductive member, which according to the subsequent operation, the embodiment of the memory cell fabricated by the method of Figure 2 shows that the bottom conductive member 2〇(M system acts as The bit line. The process steps for forming the bottom conductive member 2GG (step 3G) are shown in Figures 6-9. Step 35 is to form an access element, which in the embodiment is a doped stone The dipole body 225 and the second layer doped stone urethane 25 〇 are formed by a diode, and the forming step is shown in Fig. Μ. 11 1280635 12300 twf.doc/g Next, the material may include a conductive material. The j-shaped contact structure 4〇〇 can be formed by two steps 4〇~65', which are shown in Figures 16~18 and 19A, 20A, 21A After the contact structure _ is formed, the step (7) is used to form a top conductive member (ie, a word line). For example, a conductive material (for example, a thin film) is deposited on the structure of the branch as follows. After the v &amp; 50 and subsequent steps 55 to 65 are completed, the phase change memory such as the memory material or the chalcogenide material is further circulated (4) _, as shown in FIG. 2; ^ is not connected, and the step 75 is used to deposit the top conductive member 700. The material 'as shown in Fig. 23A. Another type of conductive structure forming a conductive material _ is selected as follows: 2: t: I0: 100 is formed into a material including a 1-shaped contact structure of a memory material. In the formula. Guang Tomb iliG5 is the side step of Figure 2, which is to pattern each layer above m2r to form word lines and memory cells. A two-dimensional view of the shed, except for the one-shaped conductive structure, another embodiment, which is opened two: ^ is prepared 200 (step 30)' as shown in Figs. Then, as in the layer of FIG. 4A, the doped stone material 225 and the second layer of doped stone material 250 are formed to form a polar body access element (dipping, as shown in FIG. 1b. The cow 40~65 system forms an L-shaped conductive structure. _, as shown in Figures 16 to 18 and / 20 Β, 21 ,, the material thereof includes, for example, a conductive material. A phase change memory material such as a bovine material or a chalcogenide material, as shown in Fig. 22A, 'the next step 75 deposits a top conductive The material of the member is as shown in Fig. 23A. Furthermore, as in the case of the 接触-shaped contact structure, the l 12 1280635 12300 twf.doc/g contact structure can also be changed to the memory material or the phase change material according to steps 8G to (10). Forming, rather than conducting, a conductive material. Next, an etching well (Fig. 105) shown in Fig. 24 is performed to visualize each of the above-mentioned conductive members 2 to form a word line and a memory cell. The steps of forming the conductive member and the diode access element are shown in the accompanying steps 6 to 15. In particular, FIG. 6 is a semiconductor substrate 148 on which a first oxide-doped oxide (eg, a dioxy-cut layer) is deposited. In the cross-sectional view, FIG. 7 illustrates the case where portions of the oxide layer 150 are etched into a trench 175 by conventional lithography. Figure 8 Green Figure 7: == formed in the first oxide layer 15 ° _.). = Erxi, Fujing Shixi, Crane, Copper, Ming Copper Alloy, Tongluo Gold or a combination thereof, or other similar materials. The surname method ί shows that portions of the first layer of conductive material in the structure of Fig. 8 are removed by a back-to-last method or CMP, and the first-oxide layer 15 == case is extinguished. This step produces a bottom conductive member 2〇〇 that can serve as a memory array. The first layer is formed on the dry ami 兀, the urethane, and the first layer 225 is opened, and is formed in the first layer of the doped stone material, and the second layer is 25G (step 35). . In the example of the example, the material of the doped coffin 225 includes an N-degree of change, for example, about l〇i5~1〇17/3 · cedar, which is mixed with bai/chen, including P+ doped shixi, 1 exchange, The material of the curved layer is changed to the material of the stone material 250, and the wavelength of the doping is, for example, about 1〇18~1〇2〇3. Referring to FIG. 12, the structure of the U is shown in FIG. The mouth, the middle, the second layer and the first layer are mixed with 13 1280635 12300 twf.doc/g. The stone materials 250 and 225 are engraved into a diode access element (the production of the step ' 'this access element In the embodiment in which the bottom conductive member 2 is in operative contact with the second conductive member 2, it may also be N/P/metal (225/25 coffee _: described P (10) / 225/200) structure. P or N doping Shi Xi can change the south rectification ratio (rectiflcati〇n plus 1〇) and high current density, and make it have low contact resistance at both ends. Although, as shown here, it is a second, but in the modified embodiment Other types of access elements, such as gold-hydrogen (MOS) elements, may be applied, but are not limited thereto. "Figure 13 is a top view of the structure of Figure 12, and Figure 12 is a 12-12, cross-sectional view of Figure 13. As shown in FIG. 14, a second layer of oxidized material is formed on the second layer of doped stone 225 and 250 after etching, and 275 (step 35) is formed, for example, including two formed by CVD. Cerium oxide. Next, the structure of FIG. 14 may be subjected to a CMP or etch back process to remove the second oxidized material milk until the first layer of doped coffin 250 is exposed, thereby forming the structure of FIG.

請參照圖16,接著在第二層摻雜矽材25〇與第一氧化 層225 一者上方形成墊材料層3〇〇 (步驟4〇),其材質例如 可包括二氧化矽、氮化矽或一些其他的氧化物或非氧化物 材料。在一實施例中,墊材料層300之材質可包括以CVD 形成的二氧化矽。 圖17繪示圖16結構之墊材料層300以微影蝕刻步驟 圖案化(步驟45)後的情形。墊材料層300被圖案化為支樓 結構310,其係在之後用於I形或L形接觸結構之形成。 支撐結構310包括操作性地於第二層摻雜石夕材250之頂面 上方延伸的側壁。 14 1280635 12300twf.doc/g 圖18繪示依照本發明一實施例,在圖以結 結構310上形成薄膜層395 (步驟%與比較之°驟,撐 樓結構31G的側壁係直接用以形塑I形或L形的接2 構’因此不需要任何罩幕層蚊義接觸結構。^。 提供更佳的電流密度控制性,例如,電流密度可在形γ 觸結構的足部降低。此薄膜層395之材f可 &gt;接 (步驟50),或是薄臈記憶材料或相變材料(比較步驟^料 ,395以形成圖19A之結構(步驟;5 ?較步驟85),其係除去薄膜層395的多個水平八, 以在支撐結構310上形成導電間隙壁(或丨形觸^盖 4〇〇,其厚度標號為彻。移去薄膜層395 m) 膜層395的選擇性高於第二氧化材料275、支擇j = t f _材25()。,19A之實施例中,接觸^構的 以,少有部分依薄膜層395的厚度而定。依昭-奋 ^列’溥膜層395可以錢鑛或⑽法來沉積。^二 衣孝王可精確地控制薄膜層395的 調整沉積時間。 /、方法例如疋 的二:顯示本發明之形成導電間隙壁或L形接觸結構 層4〇5形成在圖18結構之薄膜層395 層=均句地形成在該結構幾乎所有的暴露:面:以化 C緣示圖腦結構經過—餘刻序列而得氧化物間 1280635 123 OOtwf. doc/g =及結構41G的情形’其中_序列包括— 夕二人的非等向性侧。非等向崎 或 :去氧化層叫圖㈣的水平部分,==二 姓2垂直部分及部分較低水平部分的氧化物_壁。 侧序列例如包含兩次非等向钮刻··在 “此Referring to FIG. 16 , a pad material layer 3 〇〇 is formed over the second layer of the doped material 25 〇 and the first oxide layer 225 (step 4 〇), and the material thereof may include, for example, hafnium oxide or tantalum nitride. Or some other oxide or non-oxide material. In an embodiment, the material of the pad material layer 300 may include cerium oxide formed by CVD. Figure 17 illustrates the situation in which the pad material layer 300 of the structure of Figure 16 is patterned (step 45) in a photolithographic etching step. The pad material layer 300 is patterned into a wrap structure 310 which is then used for the formation of an I-shaped or L-shaped contact structure. The support structure 310 includes sidewalls that operatively extend over the top surface of the second layer of doped stone material 250. 14 1280635 12300twf.doc/g FIG. 18 illustrates the formation of a film layer 395 on the junction structure 310 in accordance with an embodiment of the present invention (step % versus comparison), the sidewalls of the support structure 31G are directly used to shape The I-shaped or L-shaped connection structure therefore does not require any cover-layer mosquito-repellent contact structure. Provides better current density control, for example, current density can be reduced in the foot of the shaped gamma-contact structure. The material f of layer 395 can be followed by (step 50), or a thin memory material or phase change material (compare step 395 to form the structure of Figure 19A (step; 5? compared to step 85), which is removed A plurality of levels VIII of the film layer 395 are formed on the support structure 310 to form a conductive spacer (or a 触-shaped contact cover 4, the thickness of which is labeled as follows. The film layer is removed 395 m). The selectivity of the film layer 395 is high. In the second oxidizing material 275, the alternative j = tf _ material 25 (). In the embodiment of 19A, a small portion depends on the thickness of the film layer 395. The ruthenium film layer 395 can be deposited by Qianyan or (10) method. ^ 二衣孝王 can precisely control the adjustment deposition time of the film layer 395. As shown in Fig. 2, it is shown that the conductive spacer or L-shaped contact structure layer 4〇5 of the present invention is formed on the film layer 395 layer of the structure of Fig. 18 = almost uniformly formed in the structure: face: C The characterization of the brain structure through the --received sequence results in an oxide between 1280635 123 OOtwf. doc/g = and the structure of the 41G 'where _ sequence includes - the non-isotropic side of the two people. Non-isotropic or: The deoxidation layer is called the horizontal part of the figure (4), == the second part of the second part and the oxide layer of the part of the lower level. The side sequence contains, for example, two non-isotropic buttons.

Hi用對氧化層405之選擇性高於薄膜層395 ^ίίΐ 八中例如可變化壓力及功率以垂直加速離子,二The selectivity of Hi for the oxide layer 405 is higher than that of the thin film layer 395 ^ ίί ΐ, for example, the pressure and power can be varied to accelerate the ions vertically,

斜角。在姓刻後,留下的氧化物間隙壁即具圓化或彎曲= 而可用以在後續侧中定義L形接觸結構,其中薄膜層 的暴露出部分全被除去。接著,在第二次非等向飯刻曰, 膜層395的選擇性高於氧化物間隙壁、支撐結bevel. After the last name, the remaining oxide spacers are rounded or curved = and can be used to define an L-shaped contact structure in the subsequent side, wherein the exposed portions of the film layer are all removed. Then, in the second anisotropic meal, the selectivity of the film layer 395 is higher than the oxide spacers and the support nodes.

410二第7乳化層275的韻刻劑,以形成L形接觸結構 。另了種選制是此侧序龍包括單—料向餘刻+ 驟,其係除去氧化層405與薄膜層395的多個部分二 所用蝕刻劑對氧化層4〇5與薄膜層395之選擇性高於^ 結構310與第二氧化層275。另外,控制每_ l ^觸二 構410的足部長度的方法,例如是控制氧化層4〇5的厚^ 與/或該蝕刻序列的非等向程度或其他相關特性。 又 在可視為片狀接觸窗(blade contact)的I形及l形接觸 結構二者的典型實施例中,側壁厚度450約可為〇·!〜〗〇〇〇 奈米,而在一實例中可為1〇〇奈米。圖18之薄膜層 之材質可包括一導電材料,如鈦、鎢、氮化鈦、鈦鎢合金、 石夕化鈦(TixSiy)、氮化鈦|S(TixAlyNz)或其組合,或他 似材料。 &quot;、心头貝 16 1280635 12300twf.doc/g 在I形或L形接觸結構以記憶材料形成的修改實施例 中’相似的流程可能包括在支撐結構上沉積記憶材料,再 以類似前述的製程蝕刻此記憶材料,以形成定義〗形或L 形接觸結構的記憶材料側壁。典型實施例的記憶材料倒如 可包括鍺、銻及蹄(如Gejl^Te5),其係以濺鍍製程形成在 支撐結構310上方,且其厚度(450)為(U〜10〇〇奈米,而在 一實例中約為200奈米。 …、 以上兩種型態的沉積薄膜層皆與第二層摻雜矽材25〇 的頂面操作性地接觸,而另—選制是藉由接觸插塞84〇410 2nd 7th emulsion layer 275 engraving agent to form an L-shaped contact structure. Another alternative is that the side sequence includes a single-material-to-received step, which removes the oxide layer 405 and the plurality of portions of the film layer 395. The etchant is used to select the oxide layer 4〇5 and the film layer 395. The property is higher than the structure 310 and the second oxide layer 275. Additionally, the method of controlling the length of the foot of each of the haptics 410 is, for example, controlling the thickness of the oxide layer 4 〇 5 and/or the degree of anisotropy of the etch sequence or other related characteristics. In another exemplary embodiment of both the I-shaped and the 1-shaped contact structure, which may be considered as a blade contact, the sidewall thickness 450 may be approximately !·!~ 〇〇〇 nanometer, and in an example Can be 1 〇〇 nano. The material of the film layer of FIG. 18 may include a conductive material such as titanium, tungsten, titanium nitride, titanium tungsten alloy, TixSiy, titanium nitride|S (TixAlyNz) or a combination thereof, or the like material. . &quot;Hearthead 16 1280635 12300twf.doc/g In a modified embodiment in which the I- or L-shaped contact structure is formed of a memory material, a similar process may include depositing a memory material on the support structure and etching it in a process similar to the foregoing. This memory material is used to form the sidewalls of the memory material defining the shaped or L-shaped contact structure. The memory material of the exemplary embodiment may include, for example, ruthenium, ruthenium and hoof (such as Gejl^Te5) formed on the support structure 310 by a sputtering process, and the thickness (450) is (U~10 〇〇 nanometer) And in an example about 200 nm. ..., the above two types of deposited film layers are in operative contact with the top surface of the second layer of doped coffin 25, and alternatively by Contact plug 84〇

與電晶體存取元件810操作性地連接,如圖25八盥25β 示。 -、 I 圖20A繪示在圖19A結構之支撐結構31〇 結構400、第二摻雜石夕材25〇 &amp;第二氧化材料27^方形 5()()(步驟6G與比較步驟9G)的情形。此絕 緣材科500例如可包括TE〇S-氧化石夕、SOG、BPSG或Si02。 在圖21A中,圖20A結構的表面係以CMp製平 中匕支=场训之上表面暴露出為止。在 ,θ/ 形或^形接觸窗的上端剛暴露出時即停 社槿之=广的接觸面。然而,由於接觸面大小會因接觸 接觸結:二:口:心 310之頂面心 兀王磨平’而形成大致與支撐結構 種以化學機平坦面為止(步驟65與比較步驟95)。此 予械械研磨而得均勻寬度之結構的製程可提供更佳 1280635 12300twf.doc/g 的尺寸控繼。在做的實關巾,CMp可在上述兩種情 形之間的中間位置處停止,以調整】形接觸結彻上 的截面積。 ^ 圖20B !會示在圖19c結構之支撐結構3i〇、l形接觸 氧化材料275上形成一層絕緣材料 =:使用前述相同技術’以產生圖 紝禮L b、,不在圖21A、结構之1形接觸結構400、支撐 ^冓二及絕緣材料500上沉積記憶材料600 (步驟7〇及 情形。如此沉積揚崎料^即^^ 觸二,接觸結構400的頂面操作性地接觸。每-接 400 ^mn 6〇〇 ^^ (圖服)及字元二庚尤1疋以1形接觸窗猶之厚度450 厚度約為0.!〜_二2 其可以賤鑛製程來沉積,且 圖223緣千坊不、而在一實例中約為200奈米。 觸結構410。1圖^圖3相似的結構’但其卻具有L形接 支撐結構310及‘^ B結構之L形接觸結構彻、 料_的情形。記=:Γί露出表:上沉積記憶材 前述材料。如此沉私^ 可此包括以前述方法形成的It is operatively coupled to transistor access element 810, as shown in Figure 25, 盥25β. -, I FIG. 20A illustrates the support structure 31〇 structure 400 of the structure of FIG. 19A, the second doped stone material 25〇&amp; second oxide material 27^square 5()() (step 6G and comparison step 9G) The situation. The insulating material 500 may include, for example, TE〇S-stone oxide, SOG, BPSG or SiO 2 . In Fig. 21A, the surface of the structure of Fig. 20A is made of CMp flattened = = the upper surface of the field is exposed. When the upper end of the θ/shape or ^-shaped contact window is exposed, the contact surface of the = = wide contact area is stopped. However, since the size of the contact surface is due to the contact contact: 2: mouth: the top surface of the heart 310 is swelled by the king, and is formed substantially parallel to the support structure by the chemical machine (step 65 and comparison step 95). This process of mechanically grinding a uniform width provides better control of the size of 1280635 12300 twf.doc/g. In the actual closing towel, the CMp can be stopped at an intermediate position between the above two situations to adjust the cross-sectional area of the shape contact. ^ Figure 20B! A layer of insulating material is formed on the support structure 3i, l-type contact oxide material 275 of the structure of Fig. 19c =: using the same technique as described above to generate the diagram L b, not in Fig. 21A, structure 1 The memory structure 600 is deposited on the contact structure 400, the support structure, and the insulating material 500. (Step 7 and the case. Thus, the deposition of the yakisaki material, ie, the touch surface, the top surface of the contact structure 400 is operatively contacted. Connected to 400 ^ mn 6 〇〇 ^ ^ (Figure service) and the character two Geng You 1 疋 with a 1-shaped contact window thickness of 450 thickness is about 0.! ~ _ 2 2 It can be deposited in the antimony process, and 223 缘千坊不, and in an example about 200 nm. Contact structure 410. 1 Figure ^ Figure 3 similar structure 'but it has L-shaped support structure 310 and '^ B structure L-shaped contact structure The situation of the _ _ _ _ 露出 露出 露出 露出 露出 露出 露出 露出 露出 露出 露出 露出 露出 露出 露出 露出 露出 露出 露出 露出 露出 露出 露出 露出 露出 露出 露出 露出 露出 露出

形接觸結構410的了材料_即可與導電材料之L 、面刼作性接觸。如同I形接觸結構400 1280635 12300twf.doc/g 的情形,由L形接觸結構410與記憶材料6〇〇的界面所定 義的每一個接觸面的面積可以某些方法調整,特別是以控 制L形接觸結構41〇之厚度450 (圖19C)與字元線寬度750 (圖24)的方法。 、在圖與22B之形成記憶材料的實施例中,記憶材 料600係形成在導電材料之〗形與/或L形接觸結構上方; 而與其不同的本發明其他實施方式係在記憶材料之〗形與/ 或L形接觸結構上方形成導電材料(步驟1〇〇)。在此實^ 方式中,絕緣材料(500)係沉積在〗形或L形接觸結構上方 (步驟90),其後進行任一種上述的CMp製程(步驟%)。步 驟1〇〇之形成在記憶材料之!形或L形接 方 電材料_)例如可包括鈦、鶴、氮化鈦、鈦鶴^ =(Tlxsly)、氮化鈦紹(TixA1yNz)或其組合,歧其他類似材 典型的貫施例中’導電材料可包括以雜法沉積的 〜、、厚度約10nm至l〇〇〇nm,而在一實例中係為4〇〇nm。 圖23A緣示在圖22A結構上形成一層導電材料7〇〇 八其可包括複晶石夕、鶴、銅、軸合金、銘石夕銅合 恭Lr組合’或疋其他類似材料。在典型的實施例中,導 =;斗700可包括以麵法沉積的鶴,其厚度約1〇腿至 料的圖23B麟示在圖22B結構上形成一層導電材 抖的情形,其可以前述方法形成。 圖24繪不圖23入結構經飿刻(步驟ι〇5)後,在垂直之 13:^上_面圖’亦即’對應圖24之剖面線係與圖 的12_!2,垂直。另外,圖加結構祕刻(步驟卿麦 19 1280635 亦可得與圖24類似的剖面結構。 藉由圖23A與23B結構的蝕刻步驟,頂導電構件或字 凡線即可自行對準I形或L形接觸結構400或410,其中 钮刻係停止在底導電構件200的上表面,而形成字元線與 Afe胞。在不使用存取元件的修改實施例中,姓刻可以連 續進行至通過I形或L形接觸結構400或410為止,或可 持續進行而通過底導電構件。 依照典型的實施例,頂導電構件700的寬度75〇約可 ;丨於10奈米到1微米之間;而在一實例中則約為。 字元線寬度750 了決定I形與L形接觸結構4〇〇與41〇之The material of the contact structure 410 can be in contact with the L and the surface of the conductive material. As in the case of the I-shaped contact structure 400 1280635 12300twf.doc/g, the area of each contact surface defined by the interface of the L-shaped contact structure 410 and the memory material 6〇〇 can be adjusted in some ways, in particular to control the L-shape. The method of contact structure 41 has a thickness 450 (Fig. 19C) and a word line width 750 (Fig. 24). In the embodiment in which the memory material is formed in FIG. 22B, the memory material 600 is formed over the shaped and/or L-shaped contact structure of the conductive material; and other embodiments of the present invention different therefrom are in the shape of the memory material. A conductive material is formed over the / or L-shaped contact structure (step 1). In this embodiment, the insulating material (500) is deposited over the shaped or L-shaped contact structure (step 90), followed by any of the above-described CMp processes (step %). Step 1 is formed in the memory material! The shape or the L-shaped junction material _) may include, for example, titanium, crane, titanium nitride, titanium crane ^ = (Tlxsly), titanium nitride (TixA1yNz) or a combination thereof, and other similar materials are typically used in the embodiment. The conductive material may include ~, deposited by a hetero process, having a thickness of about 10 nm to 10 nm, and in one example being 4 〇〇 nm. Figure 23A illustrates the formation of a layer of electrically conductive material on the structure of Figure 22A which may include a polycrystalline stone, a crane, a copper, a shaft alloy, a stellite copper composite, or other similar material. In a typical embodiment, the hopper 700 may comprise a surface-deposited crane having a thickness of about 1 leg to the material of FIG. 23B. The formation of a layer of electrically conductive material on the structure of FIG. 22B may be as described above. The method is formed. Fig. 24 is not shown in Fig. 23. After the structure is engraved (step ι 5), the vertical line 13: ^ _ face view ‘that is, the hatching system corresponding to Fig. 24 is perpendicular to the 12_! 2 of the figure. In addition, the structure of the Tujia structure (step Qingmai 19 1280635 can also have a similar cross-sectional structure as in Fig. 24. By the etching step of the structure of Figs. 23A and 23B, the top conductive member or the word line can be self-aligned with the I shape or The L-shaped contact structure 400 or 410 in which the button is stopped on the upper surface of the bottom conductive member 200 to form a word line and an Afe cell. In a modified embodiment in which the access element is not used, the last name can be continuously passed to The I-shaped or L-shaped contact structure 400 or 410, or can continue to pass through the bottom conductive member. According to a typical embodiment, the width of the top conductive member 700 is about 75 丨; between 10 nm and 1 μm; In an example, it is approximately. The word line width 750 determines the I-shaped and L-shaped contact structures 4〇〇 and 41〇.

—一一 一〜…〈役刺頂囟主動面積的 厚度彻與寬度750的方法可用以形成截面積相對小的工 形^ L形接觸結構。例如,#薄膜層之寬度45〇約Μ· 且寬度750約l〇〇nm時,每一 j形或L形接觸結構的截面 主動面積即約25(W。此面積對應圓形接觸結構的約 的直徑’或是正方形接騎構的約5()_的寬度。因 此’本發日狀方法可得的朗面積卿地小於習知多種方 法所得者,故其微影製程限制較少。The method of thickness and width 750 of the active area of the spur top can be used to form a relatively small cross-sectional area. For example, when the width of the film layer is 45 〇 且 and the width 750 is about 10 〇〇 nm, the active area of the cross section of each j-shaped or L-shaped contact structure is about 25 (W. This area corresponds to the circular contact structure. The diameter 'is a width of about 5 () _ of the square riding structure. Therefore, the ampere-area method can obtain a smaller area than the conventional method, so the lithography process is less restricted.

此記憶胞的構件即包括頂導電構件或字 《I形接觸結構的實施 構件或字元線870、記 20 1280635 12300twf.doc/g 憶材料860、I形接觸結構850、接觸插塞840、底導電構 件或位元線830、摻雜矽區820與810,以及基底800。同 樣地,圖25B之立體圖顯示包含電晶體以作為存取元件或 操控構件之形成L形接觸結構的實施例。此記憶胞的構件 即包括頂導電構件或字元線870、記憶材860、L形接觸結 構855、接觸插塞840、底導電構件或位元線83〇、摻雜矽 區820與810,以及基底8〇〇。 綜上所述,習知此技藝者應可瞭解本發明之方法可使 半導體元件更容易形成,此種元件一般是唯讀記憶元件, 而特別是在積體電路中使用相變材料的唯讀記憶元件。 雖然本發明已以較佳實施例揭露如上,然其並非用以 P艮=本發日月,任何熟習此技藝者,在不本發明之精神 =範圍内,當可作些許之更動與潤飾,因此本發明之保護 範圍當視後附之申請專利範圍所界定者為準。 【圖式簡單說明】 圖1為上有蜂多晶方之晶圓的上視平面圖。 圖2為在晶方之—部分上包含—記憶胞陣列的基底的 不\各方塊圖。 記憶胞所構成的記憶 做之I形接觸結構記 圖3為以本發明之方法所製造的 胞陣列的一部分的電路簡圖。 圖4A為依本發明一實施例所製 憶胞的立體圖。 圖4B為依本發明另一 記憶胞的立體圖。 實施例所製做之L形接觸結構 21 1280635 1230〇twf.doc/g 圖5為本發明實施例之記憶胞製造方法的流程圖。 圖6為本發明實施例之I形或L形接觸結構記憶胞的 製造方法的前段步驟進行之後,半導體基底的部分剖面圖。 圖7接續圖6,其氧化層已有部分被移除。 圖8接續圖7,其已形成第一層的導電材料。 圖9接績圖8 ’其導電材料已有部分被移除,而形成 底導電構件。 圖10接續圖9 ’其已形成第一層摻雜石夕材,此第一層 摻雜矽材稍後將被定義成二極體存取元件的一部分。曰 圖11接續圖10,其已形成第二層摻雜矽材,此第二 層摻雜矽材稍後將被定義成二極體存取元件的另一部分。 圖12接續圖11,其已經蝕刻而形成二極體存取元件。 圖13為圖12結構的平面圖。 圖14接續圖13,其已形成一層氧化材料。 圖15接續圖14,顯示再經化學機械研磨後的結構。 圖16接續圖15,其已形成另一層氧化材料。 圖17接續圖16,其已經蝕刻而形成一支撐結構。 圖18接續目Π,其已形成覆蓋支撐結構的導電材料 層或記憶材料層。 圖19Α接續圖18,其已經非等向餘刻而形成!形接觸 、名吉構。 圖1犯亦接續圖is,其更在導電或記憶材料層上形成 4匕層。 圖19C接續® 19Β,其已經非等向性_而形成L形 22 1280635 12300twf.doc/g 接觸結構。 形接觸結構上方形成一 形接觸結構上方形成— 圖20A接續圖19a,其已在i 層絕緣材料。 圖20B接續圖19c,其已在l 層絕緣材料。 形接觸 形接觸 圖21A接續圖20A,其已經CMP而;φ 結構的頂面。 保路出1The components of the memory cell include a top conductive member or a word "I-shaped contact structure implementation member or word line 870, note 20 1280635 12300 twf.doc / g memory material 860, I-shaped contact structure 850, contact plug 840, bottom Conductive member or bit line 830, doped germanium regions 820 and 810, and substrate 800. Similarly, the perspective view of Fig. 25B shows an embodiment in which an L-shaped contact structure is formed including a transistor as an access element or a manipulation member. The components of the memory cell include a top conductive member or word line 870, a memory material 860, an L-shaped contact structure 855, a contact plug 840, a bottom conductive member or bit line 83A, doped germanium regions 820 and 810, and The substrate is 8 inches. In summary, it is understood by those skilled in the art that the method of the present invention can make semiconductor components easier to form. Such components are generally read-only memory components, and in particular, read-only materials are used in integrated circuits. Memory component. Although the present invention has been disclosed in the above preferred embodiments, it is not intended to be used in the context of the present invention. Any person skilled in the art may make some modifications and refinements without departing from the spirit of the present invention. Therefore, the scope of the invention is defined by the scope of the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a top plan view of a wafer having a bee polycrystal. Figure 2 is a block diagram of the substrate of a memory cell array on a portion of the crystal. Memory composed of memory cells I-shaped contact structure is shown in Fig. 3 is a circuit diagram of a portion of a cell array fabricated by the method of the present invention. 4A is a perspective view of a memory cell made in accordance with an embodiment of the present invention. Fig. 4B is a perspective view of another memory cell in accordance with the present invention. L-shaped contact structure made by the embodiment 21 1280635 1230〇twf.doc/g FIG. 5 is a flow chart of a method for manufacturing a memory cell according to an embodiment of the present invention. Fig. 6 is a partial cross-sectional view showing the semiconductor substrate after the previous step of the method for fabricating the I-shaped or L-shaped contact structure memory cell according to the embodiment of the present invention. Figure 7 continues with Figure 6, where the oxide layer has been partially removed. Figure 8 continues with Figure 7, which has formed a first layer of electrically conductive material. Fig. 9 shows that the conductive material has been partially removed to form a bottom conductive member. Figure 10 continues with Figure 9 'which has formed a first layer of doped stone, which will later be defined as part of the diode access element. Figure 11 continues with Figure 10, which has formed a second layer of doped coffin, which will later be defined as another portion of the diode access element. Figure 12 continues with Figure 11 which has been etched to form a diode access element. Figure 13 is a plan view of the structure of Figure 12. Figure 14 continues with Figure 13 which has formed a layer of oxidized material. Figure 15 continues with Figure 14 showing the structure after chemical mechanical polishing. Figure 16 continues with Figure 15 which has formed another layer of oxidized material. Figure 17 continues with Figure 16 which has been etched to form a support structure. Figure 18 continues to show the formation of a layer of conductive material or layer of memory material covering the support structure. Figure 19 is continued from Figure 18, which has been formed by non-isotropic engraving! Shape contact, famous structure. Figure 1 is also a continuation of the figure is, which further forms a 4 匕 layer on the conductive or memory material layer. Figure 19C continues with the Β 19 Β , which has been anisotropic — and forms an L-shaped 22 1280635 12300 twf.doc/g contact structure. A contact structure is formed over the shape of the contact structure formed above - Fig. 20A is continued from Fig. 19a, which is already in the i layer of insulating material. Fig. 20B is continued from Fig. 19c, which is already in a layer of insulating material. Contact Contact Figure 21A is continued from Figure 20A, which has been CMP; the top surface of the φ structure. Bao Lu out 1

圖21B接續圖2〇β,其已經CMP而裰^ + 結構的頂面。 稞路出L 圖22A接續圖21A,其顯示形成㈣接觸結 在沉積記憶材料後的情形。 9衣毛 圖22B接續圖21B,其顯示形成L形接觸 在沉積記憶材料後的情形。 再幻衣秦 圖23A接續圖22A,其顯示形成丨形接觸 在形成頂層導電材料後的情形。 衣右 圖23B接續圖22B,其顯示形成L形接觸結構的製卷 在形成頂層導電材料後的狀態。 少圖24繪示圖23A或23B之結構經過蝕刻定義後的情 形,其觀視方向係與圖23A及23B之觀視方向垂直。 圖25A為以本發明其他實施例之方法所製造的I形接 觸結構記憶胞的立體圖。 圖25B為以本發明其他實施例之方法所製造的l形接 觸結構記憶胞的立體圖。 、 【主要元件符號說明】 23 1280635 12300twf.doc/g 10 :晶圓 14 : IC記憶體 18 ·導線 22 :記憶胞 26 :字元線 148 :半導體基板 175 :溝渠 225 :第一層摻雜矽材 275 :第二氧化層 310 :支撐結構 400 : I形接觸結構 410 ·· L形導電結構 500 :絕緣材料 700 :頂導電構件 800 :基底 830 :底導電構件或位元線 850 : I形接觸結構 860 :記憶材料 12: 1C晶方 16 :控制電路 20 :記憶胞陣列 24 :位元線 30、35···、105 ·•步驟標號 150 :第一氧化層 200:底導電構件 250 :第二層摻雜矽材 300 :墊材料層 395 :薄膜層 405 :氧化層 450 ··導電結構厚度 600 :記憶材料 750 :字元線寬度 810、820 :摻雜矽區 840 :接觸插塞 855 : L形接觸結構 870 :字元線 24Figure 21B is continued from Figure 2, 〇β, which has been CMP and the top surface of the structure.稞路出L Figure 22A continues with Figure 21A, which shows the formation of (iv) contact junctions after deposition of memory material. 9 garments Fig. 22B is continued from Fig. 21B, which shows the formation of an L-shaped contact after depositing a memory material. Fig. 23A continues with Fig. 22A, which shows the formation of a dome contact after the formation of the top conductive material. The right side Fig. 23B is continued from Fig. 22B, which shows the state in which the roll forming the L-shaped contact structure is formed after the formation of the top conductive material. Figure 24 is a diagram showing the structure of Figure 23A or 23B after etching definition, the viewing direction being perpendicular to the viewing direction of Figures 23A and 23B. Figure 25A is a perspective view of a memory cell of an I-shaped contact structure fabricated by a method in accordance with another embodiment of the present invention. Figure 25B is a perspective view of a 1-shaped contact structure memory cell fabricated by the method of other embodiments of the present invention. [Main component symbol description] 23 1280635 12300twf.doc/g 10 : Wafer 14 : IC memory 18 · Wire 22 : Memory cell 26 : Word line 148 : Semiconductor substrate 175 : Ditch 225 : First layer doping 矽Material 275: second oxide layer 310: support structure 400: I-shaped contact structure 410 · L-shaped conductive structure 500: insulating material 700: top conductive member 800: substrate 830: bottom conductive member or bit line 850: I-shaped contact Structure 860: Memory Material 12: 1C Crystal 16: Control Circuit 20: Memory Cell Array 24: Bit Lines 30, 35, . . . , 105 • Step Number 150: First Oxide Layer 200: Bottom Conductive Member 250: Two-layer doped coffin 300: pad material layer 395: film layer 405: oxide layer 450 · conductive structure thickness 600: memory material 750: word line width 810, 820: doped germanium region 840: contact plug 855: L-shaped contact structure 870: word line 24

Claims (1)

1280635 12300twf.doc/g 十、申請專利範圍·· ^一種接觸結構的製造方法,包括: 在具有一下導電結構之一基底上方沉積一墊材料; 蝕刻该墊材料以形成具多個側壁的至少一支撐結構; 於該至少一支撐結構上方沉積一層第一材料;、u ’ 些惻==至少-1形接觸結構,其係位於該 的,且具有與該下導電結構電性連接 下為及^亥下端相對的-上端;以及 係與=J二構上方形成一上導電結構,其 上形接觸結構的該上端電性連接。 法圍第1項所述之接觸結構的製造方 構包括至二位^構包括至少—字元線,且該下導電結 法,3二!請專鄕圍第2項所述之接觸結構的製造方 該至;一位::極體配置於該至少-1形接觸結構與 生,請專利範圍第1項所述之接觸結構的製造方 部:=形成之該至少—1形接觸結構在其下端有一足 和而成為^-L形接觸結構。 5·如申明專利範圍第4項所述之接觸結構的製造方 ^中&quot;亥上導電結構包括至少一字元線,且該下導電结 構包括至少一位元線。 法,=如申請專利範圍第5項所述之接觸結構的製造方 〆其中有至少—二極體配置於該至少一 l形接觸結構與 25 1280635 12300twf.doc/g 該至少一位元線之間。 7·如申請專利範圍第5項所述之接觸結構的製造方 法,其中有至少一電晶體配置於該至少一 L形接觸結構與 該至少一位元線之間。 、8·如申請專利範圍第1項所述之接觸結構的製造方 法’其使該第一材料形成至少一 I形接觸結構的方法包括: 名虫亥“亥至夕、一支撐結構上的該第一材料,以除去該第 -材料的多個水平部分,並留下位在該至少_ .蠢 該些侧壁中的至少一者上的該第〆材料;妨、、、口構 層第該至少-娜構及該— ㈣t坦化該第二材料以暴露出該至少—支撐結構,並形 成忒至少一I形接觸結構。 法,第4項所述之接騎構的製造方 /、使=弟一材料形成至少一 L形接觸結構的方法包括. 在該第一材料形成後,於該基底上方形成—第二材料;· 、姓刻該第:材料,以除去該第二材料的多個水平邻 並留了位在該至少一支撐結構之該些側壁中的至少二 者上的該第二材料; 吴底=一=、該第二材料、該至少一支撐結構及該 I底上配置一層第三材料;以及 平坦化該第三材料以暴露出該至少一支 成該至少-L形接觸結構。 構亚形 1〇·如申請專利範圍第1〜9項中任一項所述之接觸結 26 1280635 12300twf.doc/g 構的製过方法,其中該第—材料包括—層導電材料,且該 上導電結構包括一層記憶材料。 、I1·如申睛專利範圍第10項所述之接觸結構的製造方 法,其中該記憶材料包括一硫族材料。 12·如申請專利範圍第卜9項中任一項所述之接觸結 構的製造方法,其中該第—_包括-記騎料。 13=申請專利範圍第12項所述之接觸結構的製造方 / ,八中該§己憶材料包括一硫族材料。 14·一種半導體裝置,包括: 具有一下導電結構之一基底; 具有多個側壁的至少—士特 -支撐結構,位於該基底上; 祕觸、、,。構’係位於該些側壁中的至少—上, 的該ΙΪ電結構電性連接的—下端及與該下端相對 方,位在該至少- ^形接觸結構的上 15二種半導體以H構㈣上端紐連接。 具有一下導電結 具有多個侧壁的至y|、 ^ -L形接觸結構二支撐結構,位於該基底上; 上,且具有與該下導電、纟/、係位於該些側壁中的至少一者 相對的一上端;以及&quot;構電性連接的一下端及與該下端 一上導電結構,其传 方,且與該至少一L·氷虹立在該至少一L形接觸結構的上 ’觸結構的該上端電性連接。 271280635 12300twf.doc/g X. Patent Application Scope A method for manufacturing a contact structure, comprising: depositing a pad material over a substrate having a lower conductive structure; etching the pad material to form at least one of a plurality of sidewalls a support structure; depositing a first material over the at least one support structure; and u ' some 恻 == at least -1 contact structure, which is located there, and has electrical connection with the lower conductive structure The upper end is opposite to the upper end; and the upper and lower sides of the system are formed with an upper conductive structure, and the upper end of the upper contact structure is electrically connected. The manufacturing structure of the contact structure described in the first item of the method includes: to the two-position structure including at least the word line, and the lower conductive junction method, 3 two! Please specialize in the contact structure described in item 2 The manufacturing side should; one: the polar body is disposed in the at least -1 contact structure and the raw, the manufacturing side of the contact structure described in the first item of the patent scope: = the at least one-shaped contact structure formed Its lower end has a foot and becomes a ^-L contact structure. 5. The manufacturer of the contact structure of claim 4, wherein the upper conductive structure comprises at least one word line, and the lower conductive structure comprises at least one bit line. The method of manufacturing a contact structure according to claim 5, wherein at least a diode is disposed in the at least one contact structure and the 25 1280635 12300 twf.doc/g of the at least one bit line between. 7. The method of fabricating a contact structure according to claim 5, wherein at least one transistor is disposed between the at least one L-shaped contact structure and the at least one bit line. 8. The method for manufacturing a contact structure according to claim 1, wherein the method for forming the first material to form at least one I-shaped contact structure comprises: a first material to remove a plurality of horizontal portions of the first material and leaving the second material on at least one of the at least one of the sidewalls; And at least - forming the second material to expose the at least-support structure and forming at least one I-shaped contact structure. The method of manufacturing the device according to the fourth item The method of forming a material into at least one L-shaped contact structure comprises: after the first material is formed, forming a second material over the substrate; and surname the material: to remove the second material Horizontally adjacent and retaining the second material on at least two of the sidewalls of the at least one support structure; Wu = one =, the second material, the at least one support structure, and the bottom Configuring a layer of third material; and planarizing the third material to expose The at least one of the at least one L-shaped contact structure is formed. The conformal structure of the contact junction 26 1280635 12300 twf.doc/g according to any one of claims 1 to 9 The first material includes a layer of a conductive material, and the upper conductive structure comprises a layer of a memory material. The method of manufacturing the contact structure according to claim 10, wherein the memory material comprises a chalcogen The method of manufacturing a contact structure according to any one of the preceding claims, wherein the first to include a bicycle. 13 = the contact structure of claim 12 The manufacturer/seven material includes a chalcogenide material. 14. A semiconductor device comprising: a substrate having a lower conductive structure; at least a stent-supporting structure having a plurality of sidewalls on the substrate The secret contact, the structure is located at least on the sidewalls, and the lower end of the electrical structure is electrically connected to the lower end and opposite the lower end, and is located on the upper surface of the at least --contact structure Two semiconductors H structure (four) upper end connection. The lower conductive layer has a plurality of sidewalls to the y|, ^ -L contact structure two support structure, located on the substrate; upper, and has the lower conductive, 纟 /, system located At least one of the sidewalls is opposite to an upper end; and a lower end of the electrically connected connection and an upper conductive structure with the lower end, the passer, and the at least one L. The upper end of the upper 'contact structure of the L-shaped contact structure is electrically connected.
TW93135393A 2004-11-18 2004-11-18 Memory element, array of memory cell, method of forming contact structure and apparatus and semiconductor device produced by the method TWI280635B (en)

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