KR100687755B1 - Phase change memory device having insulator nano-dots and method of manufacturing the same - Google Patents

Abstract

A phase-change memory device having insulator nano-dots and a method for manufacturing the same are provided to lower a value of current required to drive the memory device by reducing a contact area between a phase-change material layer and an electrode material. A heat-generating metal electrode layer(120) is formed on a first electrode layer. Insulation layer patterns(130,160) are formed on the heat-generating metal electrode layer, and an opening exposing a first region of the heating-generating metal electrode layer is formed on the pattern. Plural insulator nano-dots(140) are formed on a surface of the heat-generating metal electrode layer to prevent an electric contact between the heat-generating metal electrode layer and a phase-change material layer(150) which is formed on the nano-dots and the heat-generating metal electrode layer. A second electrode layer is formed opposite to the heat-generating metal electrode layer.

Description

Phase change memory device having an insulator nano dot and a method of manufacturing the same {Phase change memory device having insulator nano-dots and method of manufacturing the same}

1A through 1F are cross-sectional views illustrating a manufacturing method of a phase change memory device according to a preferred embodiment of the present invention in a process sequence.

2 is a flowchart for describing a method of manufacturing a phase change memory device according to an exemplary embodiment of the present invention.

3A to 3C are cross-sectional views illustrating a method of forming an insulator nano dot included in a phase change memory device according to an exemplary embodiment of the present invention, according to a process sequence.

4A and 4B are cross-sectional views illustrating a method of forming an insulator nano dot included in a phase change memory device according to a preferred embodiment of the present invention, according to a process sequence.

5A and 5B are schematic views showing an exemplary formation of an insulator nano dot structure that can be employed in the phase change memory device according to the present invention, respectively.

6 is a graph showing the change in the contact area size of the phase change material and the electrode material in the phase change memory device with respect to the size of the insulator nano dot formed according to the present invention.

<Explanation of symbols for the main parts of the drawings>

Reference Signs List 100: substrate, 110: lower electrode layer, 120: heat generating metal electrode layer, 130: first insulating film pattern, 130a: opening, 140: insulator nano dot, 150: phase change material layer, 160: second insulating film pattern, 160a: first 1 hole, 160b: second hole. 170: upper electrode layer, 310: metal layer, 312: metal nano dot, 312a: metal part, 312b: metal oxide part, 314: insulator nano dot, 410: silicon nano dot, 412: silicon nitride nano dot, 510, 520: gap part.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device using a phase change material and a method of manufacturing the same, and more particularly, to a phase change memory device controlling a contact area between a phase change material layer and an electrode layer using an insulator nano dot structure and a method of manufacturing the same. will be.

There are two types of semiconductor memory, volatile memory and nonvolatile memory. Volatile memory is memory that is lost when the power is turned off. On the other hand, the stored memory does not disappear even when the power is cut off in the nonvolatile memory. DRAM (Dynamic Random Access Memory) is a typical volatile memory and inevitably involves a refresh operation in its operation. The refresh operation refers to an operation of storing the stored information that is destroyed by the leakage current of the memory device again at regular intervals. In the past, where memory density was relatively low, the amount of power consumed by the refresh operation was not much of a problem for the overall DRAM operation. However, as the degree of integration of memory increases, when the current refresh rate corresponding to 1 to 10 ms / Mbit is applied, the entire DRAM consumes considerable energy. In other words, in the current DRAM of several gigabytes, the consumption of power consumed for the refresh operation has reached the degree of dominating the power consumption of the entire operation. Despite the problem of increased power consumption, DRAM is still the most used memory module to date because of its high speed and low cost.

If these volatile DRAMs can be replaced with non-volatile memory, not only power consumption but also significant reductions in start-up time can be expected, so that some non-volatile memory technologies are in the stage of active research and development. There is progress. Among these nonvolatile memories, the most technological development is in progress, and the most frequently used in the actual market is flash memory. However, flash memory is currently used exclusively for mobile devices such as digital cameras and mobile phones because of the disadvantage of slow speed and relatively high voltage.

On the other hand, one of the important performances that the memory should have is reliability of the rewrite operation. In the case of flash memory, the reliability of the rewrite operation is not very good, but if the use is limited only to the application to the mobile device represented by the personal information terminal, the standard of the number of rewritable times can be greatly reduced. However, it is a matter of course that a stable operation such as a general-purpose PC cannot be ensured with the reliability of the rewrite operation that is required in the mobile device.

In addition, in order to satisfy the memory specifications required by recent portable mobile devices and digital devices having a convergence function, a method of using a combination of DRAM / SRAM / flash memory, etc. in order to utilize all the advantages of each memory module. Is adopted. However, this method not only significantly increases the size of the entire memory chip, but also is a disadvantage in terms of cost. However, there is no memory that satisfies all the required specifications such as high speed, high density, and non-volatile, so it is a method that is unavoidably selected and is not an efficient method at all.

For these reasons, researchers and developers working in the memory field strongly demand the emergence of all-in-one integrated memory that can be reliably mounted in any device and application. It is necessary to provide a rewrite operation reliability and the like. However, to date, semiconductor memories with all these capabilities have not been commercialized. Accordingly, various nonvolatile memory technologies are currently being actively researched and developed, and at present, various stages of development and compatibility for each technology are being explored.

On the other hand, in the case of a nonvolatile memory called a phase-change memory (PRAM), a method of applying a current or voltage under an appropriate condition using a phase change material whose resistance value changes depending on a crystal state of the material is used. By selecting, the information is stored in a method of controlling the crystalline state of the material, and the memory operation is realized by reading the kind of stored information from the change of the resistance value according to the crystalline state of the material. At this time, the crystal state of the material has a low resistance characteristic, and the amorphous state has a high resistance characteristic. In the operation of a phase change memory device, an operation of changing from a high resistance amorphous state to a low resistance crystal state is called a SET operation, and resets an operation of changing from a low resistance crystal state to a high resistance amorphous state. It is called (RESET) operation.

On the other hand, in the fabrication of phase change memory, the phase change material of the chalcogenide metal alloy, which has been mainly used in optical storage information devices such as CD-RW and DVD, can be used as it is. It is well matched with the silicon-based device fabrication process, making it easy to achieve the same degree of integration as DRAM. On the other hand, in the case of magneto-resistive memory and ferroelectric memory competing with the phase change memory, the difficulty of the process increases rapidly or the performance of the device deteriorates due to the miniaturization of the device. There is a problem. Therefore, in view of the state of the art development up to now, phase change memory is the most promising next-generation nonvolatile memory candidate that can replace the current flash memory, and for this reason, it is a semiconductor memory technology attracting great attention.

However, in order to commercialize the phase change memory, it is necessary to greatly reduce the power consumption required for driving the memory device. As described above, the phase change memory consumes a relatively large amount of power because the memory element is driven by controlling the crystal state of the phase change material by using an electric joule-heat generated when a current flows through the resistor. There is a possibility. This problem is related to the fact that the phase change memory has recently gained great attention, although it has relatively advantageous advantages over other types of nonvolatile memory. In other words, the design rules used in the semiconductor process have been reduced by a constant scaling method, and when fabricating a phase change memory device using a conventional semiconductor process that manufactured a relatively large device, the entire system cannot afford it. Due to the problem of power and heat generation, it is impossible to realize a memory device having practical operating characteristics. However, with the continuous reduction of design rules, the size of the device itself is greatly reduced, and using the design rules of the semiconductor process that is currently used, the power consumption required for the operation of the phase change memory can be greatly reduced. .

On the other hand, efforts to reduce the amount of current for the operation of the phase change memory device continue to proceed, which is closely related to the higher density of the phase change memory. Development of low power consumption device structure is essential to ensure reliable memory operation of high density integrated phase change memory. This aims to reduce the absolute power consumption of the entire phase change memory array. On the other hand, the employment of a low power consumption device structure has another important purpose in addition to the reduction of the power consumption. That is, the heat generated during the memory operation of a particular device should not destroy or change the information stored in the adjacent memory device. In particular, the spacing of each device in the high density memory array is likely to be continuously reduced in the future, and in some cases, heat generated during a specific cell memory operation acts as a noise factor, which inhibits memory operation of adjacent cells. This can be

As a method for reducing the absolute current required for the operation of a phase change memory device, the following methods have been applied.

(1) It is a material approach.

In other words, by adopting a phase change material having a relatively low melting point, the temperature required for the phase transition is lowered, thereby reducing the current value required for the memory operation. This is a method of reducing the power consumption of the phase change memory by changing the phase change material itself regardless of the device structure.

(2) Device structural approach.

There are two recent trends in the structural approach of the device. The first method is to reduce the required current value by minimizing the phase change area, which is a key part of the operation of the phase change memory device. Since the phase change memory device experiences a phase transition state by using heat generated at the contact portion of the phase change material and the electrode material, it is a method of reducing power consumption of the phase change memory by minimizing the contact portion. At present, the method of minimizing the contact portion is the most commonly attempted approach. The second method is to optimize the structure of the memory device so that the thermal energy experienced by the phase change material located within the device can be used as fully as possible. That is, as in the first method, even if the phase change region is minimized to reduce the heat generated in the contact portion, it is because a relatively large current cannot be applied unless the heat energy itself is efficiently used. Therefore, in the second method, by providing an appropriate device structure, the heat applied to the phase change region can be used for the phase transition of the phase change material without leakage component, if possible, thereby reducing the power consumption of the entire phase change memory. It is a way.

Of course, if the phase change memory device is fabricated by using both of the methods described in (1) and (2) above, it is of course possible to maximize the reduction in the power consumption required for the operation of the phase change memory device.

On the other hand, in the fabrication of the phase change memory device using the first method of (2), various attempts have been made to reduce the contact portion between the phase change material and the electrode material. For example, by contacting a phase change material with an area in the lateral depth direction exposed by etching part of the electrode material previously formed, the contact area between the phase change material and the electrode material is (film thickness of the electrode material) × (phase change material). Has been proposed (YH Ha et al., Dig. Tech. Papers of VLSI Symp. 2003, pp. 173-176). This structure is referred to as a phase change memory device including edge contacts. Whereas the contact area of a conventional vertical phase change memory element is determined by the resolution of the lithography, which determines the size of the contact, the edge contact structure is generally formed of an electrode material that can be formed to be 1/10 or less than the lithography resolution. Since the film thickness is used as one side of the contact area, it is true that the contact area of the phase change memory element can be greatly reduced.

However, the phase change memory device including the edge contact is still limited in dramatically reducing the contact area since the other side is determined by the resolution of the lithography. In addition, since the device structure itself is complicated, not only one or two extra photo masks need to be manufactured in the manufacturing process of the phase change memory device, but also a separate dry etching process or the like is required. There is.

In addition, in the fabrication of the phase change memory device using the first method of (2), another attempt to reduce the contact portion between the phase change material and the electrode material is the shape of the electrode material in contact with the phase change material. Has been proposed in the form of a cone to theoretically construct a contact area between the phase change material and the electrode material in the form of a contact (US Pat. No. 5,687,112). The method has the advantage that the size of the phase change memory device can be made extremely small since the contact area can be reduced in the form of a point which theoretically does not have an area, and as a result, an ultrafine low power consumption phase change It is considered that the memory device can be realized.

However, in the manufacturing process of the actual device, a predetermined electrode material is processed into a cone shape, the peripheral region is filled with an insulating material, and then the electrode material region in the contact form is exposed to successfully contact the upper phase change material. Is a very difficult process. In addition, even if the process is performed successfully, it is more difficult to keep the contact area uniform in each device. If the process method is likely to cause a difference in contact area size over a certain distribution on a given substrate, it is difficult to employ such a process method in the fabrication of an actual memory device. The reason is that the phase change memory device including the conical electrode structure reduces the amount of current required for the memory operation only through the phase transition phenomenon of the phase change material present on the very small contact, and thus the contact of the conical electrode to be processed. The smaller the size, the more likely the distribution of current required for operation between the memory elements is to occur, and the more likely it is to cause different operation between the operating elements under the same operating current conditions, which is in contrast to the lower power consumption of the phase change memory element. Because it results.

The present invention is to solve the above problems in the prior art, by minimizing the phase change area for reducing the power of the phase change memory device and at the same time reducing the nonuniformity of the contact area between the electrode and the phase change material layer between the individual devices It is to provide a phase change memory device capable of realizing an ultra-fine low power consumption device without causing problems in the operation of the entire memory array.

Another object of the present invention is to minimize the phase change area for the low power of the phase change memory device, and to use a process that is easy to implement and has excellent reproducibility, thereby reducing the contact area between the electrode and the phase change material layer between the individual devices. It is to provide a method of manufacturing a phase change memory device that can reduce the nonuniformity.

In order to achieve the above object, the phase change memory device according to the present invention includes a heat generating contact region in a first electrode layer, a heat generating metal electrode layer formed on the first electrode layer, and a first area which is part of the heat generating metal electrode layer. And a phase change material layer in contact with the plurality of insulator nano dots interposed therebetween to limit the contact area between the exothermic metal electrode layer and the phase change material layer in the first region; And a second electrode layer in contact with an opposite side of the change material layer in contact with the heat generating metal electrode layer.

And an insulating film pattern interposed between the heat generating metal electrode layer and the phase change material layer, wherein the first region is defined by an opening formed in the insulating film pattern.

The exothermic metal electrode layer and the phase change material layer are in contact with each other at a portion of the plurality of insulator nano dots surrounded by adjacent insulator nano dots.

The insulator nano dot may be made of metal oxide or silicon nitride. Preferably, the plurality of insulator nano dots each have a hemispherical shape.

In order to achieve the above another object, in the method of manufacturing a phase change memory device according to the present invention, a substrate on which a first electrode layer is formed is prepared. A heat generating metal electrode layer is formed on the first electrode layer. An insulating layer pattern having an opening is formed on the heat generating metal electrode layer to expose a first region which is a part of the heat generating metal electrode layer. A plurality of insulator nano dots is formed on the heat generating metal electrode layer in the opening. In this case, the plurality of insulator nano dots are formed to expose the heat generating metal electrode layer between adjacent insulator nano dots among them. A phase change material layer covering a top surface of the heat generating metal electrode layer exposed between the adjacent insulator nano dots is formed on the first region. A second electrode layer is formed in contact with the top surface of the phase change material layer.

In the exemplary method of manufacturing a phase change memory device of the present invention, the forming of the plurality of insulator nano dots may include forming a metal layer on the heat generating metal electrode layer in the first region, and a nitrogen (N ₂ ) atmosphere. Forming a plurality of metal nano dots from the metal layer by a heat treatment at, and forming the plurality of insulator nano dots from the plurality of metal nano dots by heat treatment in an oxygen (O ₂ ) atmosphere. Can be.

In another exemplary method of manufacturing a phase change memory device of the present invention, the forming of the plurality of insulator nano dots may include forming a nano dot metal oxide film on the heating metal electrode layer in the first region by using an atomic layer deposition method. And depositing.

In another exemplary method of manufacturing a phase change memory device of the present invention, the forming of the plurality of insulator nano dots comprises forming a plurality of silicon nano dots on the heat generating metal electrode layer in the first region; The method may include forming a plurality of silicon nitride nano dots by nitriding the plurality of silicon nano dots.

In another exemplary method of manufacturing a phase change memory device of the present invention, the forming of the plurality of insulator nano dots may include forming a silicon nitride film in the form of nano dots using chemical vapor deposition.

According to the present invention, an ultrafine low power consumption phase change memory device can be easily manufactured. In addition, in the fabrication of fine contact regions, the contact area between the electrode and the phase change material layer can be greatly reduced as compared with the conventional manufacturing process of the phase change memory device. It is possible to effectively control the nonuniformity. Therefore, power consumption of the phase change memory device can be greatly reduced.

Next, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

In the present invention, an insulator nano dot structure is used to minimize the contact area between the phase change material and the exothermic metal electrode layer. In addition, the phase change memory device fabricated by including the insulator nano dot structure according to the present invention is a predetermined substrate including a silicon substrate or an insulating film formed on the silicon substrate, a lower electrode formed on the substrate, a lower electrode formed on the predetermined A heat generating metal electrode that generates heat when a current is supplied while having a resistance of 10, an insulator nano dot formed by an appropriate method on the heat generating metal electrode, and an image formed on the heat generating metal electrode having the insulator nano dot formed on an upper surface thereof. A change material layer and an upper electrode formed on the phase change material layer.

1A through 1F are cross-sectional views illustrating a manufacturing method of a phase change memory device according to a preferred embodiment of the present invention in a process sequence. 2 is a flowchart for describing a method of manufacturing a phase change memory device according to an exemplary embodiment of the present invention.

A method of manufacturing a phase change memory device according to a preferred embodiment of the present invention will be described with reference to FIGS. 1A to 1F and FIG. 2.

Referring to FIG. 1A, first, a substrate 100 is prepared. The substrate 100 may be formed of a semiconductor substrate made of silicon, or a substrate having a silicon oxide film formed on an upper surface thereof by thermally oxidizing a surface of the silicon substrate. Alternatively, when the phase change memory device to be formed is configured in the form of a memory array and integrated with a circuit module such as an XY decoder for driving a memory array, a sense amplifier, or the like, the substrate 100 includes a CMOS for configuring these circuits. The substrate may be any substrate on which transistors are arranged.

The lower electrode layer 110 and the heat generating metal electrode layer 120 are sequentially formed on the substrate 100. (Step 210 of Fig. 2)

The lower electrode layer 110 serves as a lower terminal of the phase change memory device and is formed of a low resistance metal electrode. For example, the lower electrode layer 110 may be made of a metal such as platinum (Pt), tungsten (W), titanium tungsten (TiW), or the like. The lower electrode layer 110 may be formed by a sputtering method, an electron beam metal deposition method, or the like, which is a commonly used metal electrode forming method. The thickness of the lower electrode layer 110 is preferably formed to a thickness sufficient to exhibit low resistance as a metal electrode, and in forming a stack structure constituting the phase change memory device, It is preferable not to form too thin or too thick in consideration of process convenience such as mechanical stress and etching process time.

The exothermic metal electrode layer 120 serves to generate sufficient heat to change the crystal state at the contact portion with the phase change material layer formed thereon in a subsequent process. This may be accomplished by the current supplied through the lower electrode layer 110. The resistance of the heat generating metal electrode layer 120 is higher than that of a general metal electrode. The selection of the material for constructing the heat generating metal electrode layer 120 is an important factor in determining the operation characteristics of the phase change memory device. Representative materials that can be used to form the heat generating metal electrode layer 120, titanium nitride (TiN), titanium oxynitride (TiON), titanium aluminum nitride (TiAlN), tantalum aluminum nitride (TaAlN), tantalum silicon nitride (TiSiN ) Is the same material. Like the lower electrode layer 110, the heat generating metal electrode layer 120 may be formed by a sputtering method or an electron beam metal deposition method, which is a metal electrode forming method that is commonly used. Since the thickness of the exothermic metal electrode layer 120 is one of important conditions for determining the resistance value of the exothermic metal electrode layer 120, it is preferable that the thickness of the exothermic metal electrode layer 120 be appropriately selected.

Referring to FIG. 1B, a first insulating layer pattern 130 is formed on the heat generating metal electrode layer 120. (Step 220 of FIG. 2)

In order to form the first insulating layer pattern 130, first, a first insulating layer is formed on the heat generating metal electrode layer 120, and then the first insulating layer is patterned to form a predetermined region of the heat generating metal electrode layer 120. The first insulating layer pattern 130 having the opening 130a exposing is formed. The first insulating layer pattern 130 serves to electrically or thermally insulate each memory device in the array structure of the entire phase change memory device. The first insulating layer pattern 130 may be formed of a commonly used insulating layer, for example, a silicon oxide layer or a silicon nitride layer. Alternatively, it may be made of an insulating film made of another material having similar performance in some cases. For example, when forming a silicon oxide film as the first insulating film pattern 130, it is common to form a silicon oxide film by chemical vapor deposition, and particularly preferably by a relatively low temperature process. . The reason is to prevent the heat generating metal electrode layer 120, which is a base film of the first insulating layer pattern 130, from being oxidized by a high temperature process. In addition, an appropriate device isolation process may be performed by forming the first insulating layer pattern 130. That is, when a silicon oxide film, which is commonly used, is used as the material for forming the first insulating layer pattern 130, a portion to be defined as a phase change memory device region, that is, the opening 130a region is secured through a dry or wet etching process. By doing this, each memory element portion can be separated. The exothermic metal electrode layer 120 and the phase change material layer formed in a subsequent process may be in contact with only some of them by the first insulating layer pattern 130.

Referring to FIG. 1C, an insulator nano dot 140 is formed on a surface of the heat generating metal electrode layer 120 exposed through the opening 130a of the first insulating layer pattern 130. (Step 230 of Fig. 2)

The insulator nano dot 140 is formed to further reduce the contact area between the heat generating metal electrode layer 120 and the phase change material layer formed in a subsequent process. The insulator nano dot 140 does not necessarily need to be selectively formed only on the heat generating metal electrode layer 120. Although not illustrated, the insulator nano dot 140 may be formed on the surface of the first insulating layer pattern 130, and the thickness of the insulator nano dot 140 is very thin compared to the thickness of the first insulating layer pattern 130. In addition, since the electrical characteristics have the same insulating properties as the first insulating film pattern 130, even when the insulator nanodots 140 are formed on the first insulating film pattern 130, they do not adversely affect subsequent processes. In addition, it does not have a special influence on the characteristics of the device.

As the method of forming the insulator nano dot 140, it is preferable to use an appropriate method for optimizing the characteristics of the phase change memory device to be formed in the present invention, and the details of the formation method will be described later.

On the other hand, the size and shape of the insulator nano dot 140 to be formed in the present invention is the most important condition in optimizing the characteristics of the phase change memory device according to the present invention. In order to solve the technical problem of the present invention and to realize an ultrafine low power consumption phase change memory device, several insulator nano dots 140 are formed on a exposed portion of the heat generating metal electrode layer 120 in a very dense shape. It is preferable to be. At this time, the relationship between the size of the insulator nano dot 140 and the shape of the formed structure, and the contact area between the phase change material layer (formed in a subsequent process) of the phase change memory device and the heat generating metal electrode layer 120. A more detailed description thereof will be given later.

Meanwhile, according to the related art, an area of the heat generating metal electrode layer 120 exposed through the opening 130a of the first insulating layer pattern 130 is a phase change material layer and a heat generating metal electrode layer in the phase change memory device. It becomes the contact area with 120). Therefore, in the related art, the current value required for the operation of the phase change memory device may be reduced by reducing the area of the heat generating metal electrode layer 120 exposed through the opening 130a as much as possible. However, it is very difficult to ensure a contact area of 50 nm or less even when using the present most advanced lithography technology in reducing the area of the opening 130a. On the other hand, in the structure of the phase change memory device including the insulator nano dot 140 according to the present invention, by optimizing the formation method of the insulator nano dot 140, minute gaps between adjacent insulator nano dots 140 are formed. The area of the exothermic metal electrode layer 120 exposed through the control is controlled. Since the area of the exposed portion of the exothermic metal electrode layer 120 becomes the contact area between the phase change material layer and the exothermic metal electrode layer 120, the contact area determined by the lithography technique as in the conventional method. A much smaller contact area can be formed, and very fine contact areas that have not been achieved so far can be realized.

In addition, in the structure of a conventional phase change memory device, a technique for easily forming a phase change material layer through a subsequent process inside a fine hole having a high aspect ratio formed in a square pillar shape has been reported. There is no bar. In contrast, the insulator nano dot 140 employed in the present invention has a characteristic of being formed in a hemispherical shape, and due to this structure, the phase change material layer and the exothermic metal electrode layer are formed when the phase change material layer is formed in a subsequent process. Contact with 120 may be facilitated.

Referring to FIG. 1D, a phase change material is formed to cover an upper surface of the heat generating metal electrode layer 120 exposed at an upper portion of the insulator nano dot 140 exposed through the opening 130a and a gap portion therebetween. After deposition, it is patterned to form a phase change material layer 150 filling the opening 130a. (Step 240 of FIG. 2)

The phase change material layer 150 may be made of an alloy of chalcogenide-based metal elements. The phase change material layer 150 has various phase change characteristics according to the constituent elements and the composition of the metal alloy, which plays a very important role in the operation of the phase change memory device. Typical examples of the chalcogenide-based metal elements constituting the phase change material layer 150 include Ge, Se, Sb, Te, Sn, As, and the like, and the chalcogenide phase change may be performed by appropriate combination of these elements. The material is formed. In addition, in order to improve the characteristics of the phase change material layer 150, in addition to the combination of the chalcogenide-based metal elements, elements such as Ag, In, Bi, and Pb may be mixed. Preferably, the phase change material layer 150 has Ge ₂ Sb ₂ Te ₅ (GST), which is a combination of Ge, Sb, and Te in a ratio of 2: 2: 5, and has been used as the most common material. As-Sb-Te based chalcogenide alloy material (see K. Nakayama et al., Jpn, J. Appl. Phys., Vol. 39, pp.6157-6161, 2000), or Se-Sb -Te based chalcogenide alloy material (see K. Nakayama et al., Jpn, J. Appl. Phys., Vol. 32, pp.404-408, 2003). In addition, binary chalcogenide materials other than ternary chalcogenide materials may also be used to construct the phase change material layer 150 of the phase change memory device according to the present invention. Examples of binary chalcogenide materials suitable for use in the present invention include Sb-Se based chalcogenide alloy materials (SM Yoon et al., Ext. Abst. International Conference on Solid State Device & Materials (SSDM) 2005, pp. 1050-1051), or an In-Se based chalcogenide alloy material (see H. Lee et al., Jpn, J. Appl. Phys., Vol. 44, pp.4759-4763, 2005). have. Preferably, the phase change material layer 150 is made of Sb-Se material in which the composition of Sb is controlled to 40 to 70 of the Sb-Se metal alloy.

In order to form the phase change material layer 150, for example, a sputtering film formation method or an electron beam deposition method may be used. At this time, the target of the raw material to be used may be prepared in the form of plural or unidirectional. After the phase change material is deposited using an appropriate method, the phase change material layer 150 is formed by patterning the phase change material using an appropriate etching process so that the material remains only at a predetermined position, that is, a position where the phase change memory device is to be manufactured. As the etching process, for example, a dry etching method using plasma may be used.

Referring to FIG. 1E, after depositing a second insulating film on the first insulating film pattern 130, patterning the second insulating film to form a first hole 160a exposing the top surface of the phase change material layer 150. The pattern 160 is formed. (Step 250 of FIG. 2) If necessary, a second hole 160b is formed to etch the second insulating film and the first insulating film pattern 130 below to expose the top surface of the heat generating metal electrode layer 120. Can be. In order to form the first hole 160a and the second hole 160b, a wet etching process or a dry etching process may be used.

The second insulating layer pattern 160 serves to electrically insulate the individual memory devices while allowing the phase change material layer 150 to contact only a portion of the upper electrode layer formed in a subsequent process.

The process of forming the second insulating film pattern 160 should be performed at a low temperature as much as possible. The reason for this is to prevent oxidation of the phase change material layer 150 and diffusion of components, and to not change the crystal state of the phase change material layer 150 significantly. The second insulating layer pattern 160 may be formed of a silicon oxide layer or a silicon nitride layer. The second insulating layer pattern 160 may be formed using a chemical vapor deposition method (ECR plasma chemical vapor deposition, ECRCVD) using a ECR plasma or a remote plasma, or a remote plasma. It is preferably formed by a nitriding (Remote Plasma Nitridation) process.

Referring to FIG. 1F, an upper electrode layer 170 in contact with the phase change material layer 150 is formed on the second insulating layer pattern 160. (Step 260 of FIG. 2) The upper electrode layer 170 is in contact with the phase change material layer 150 through the first hole 160a and the heat generating metal electrode layer 120 through the second hole 160b. It is formed to contact with.

The upper electrode layer 170 serves as an upper terminal of the phase change memory device. The upper electrode layer 170 is formed of a low resistance metal electrode like the lower electrode layer 110.

Between the phase change material layer 150 and the upper electrode layer 170 improves the contact characteristics between the upper electrode layer 170 and the phase change material layer 150 and may be unnecessary at the interface therebetween. In order to prevent the reaction, the movement of the element, etc., a separate metal layer (not shown) having a property of diffusion prevention may be inserted.

In order to form the upper electrode layer 170, a sputtering method, an electron beam metal deposition method, or the like may be used.

The specific structure and description thereof shown in the accompanying drawings for the phase change memory device according to the embodiment of the present invention described above are not intended to limit the present invention, and the general knowledge within the scope of the present invention may be understood. Various modifications and changes are possible to improve the characteristics of the phase change memory device according to the present invention.

3A to 3C are cross-sectional views according to a process sequence to explain an example of a method of forming an exemplary insulator nano dot suitable for use as the insulator nano dot 140 illustrated in FIGS. 1C to 1F. In Figs. 3A to 3E, the same reference numerals as in Figs. 1A to 1F refer to the same elements, and thus, detailed description thereof will be omitted here.

Referring to FIG. 3A, after the substrate on which the exothermic metal electrode layer 120 is exposed is prepared, a metal layer 310 having a relatively thin thickness of several nm to 10 nm is formed on the exothermic metal electrode layer 120. do. The metal layer 310 may be made of aluminum (Al), for example. The metal layer 310 may be formed using a conventional deposition method such as a sputtering method, a thermal evaporation method, or an atomic layer deposition method. In order to precisely control the thickness of the metal layer 310 to a desired thickness of several nm level, it is preferable to form by using an atomic layer deposition method.

Referring to FIG. 3B, the metal layer 310 is heat-treated in a nitrogen (N ₂ ) atmosphere at a temperature slightly lower than the melting point of the metal constituting the metal layer 310, and the metal nano dots on the exothermic metal electrode layer 120 are formed. Form 312. When the metal layer 310 is made of Al, the Al layer may be heat-treated at a temperature of, for example, about 400 to 600 ° C., and during heating, the Al layer has a property of agglomeration in the form of hemispherical dots. The Al layer changes to Al nano dots.

The metal nano dot 312 includes a metal portion 312a, which is a central portion of the hemispherical nano dots, and a metal oxide portion 312b constituting a surface of the metal nano dot 312 around the metal portion 312a. When the metal layer 310 is made of Al, the metal nano dots 312 may include an Al portion in the center and an aluminum oxide portion constituting the surface of the Al nano dots around it. In order to precisely control the size and density of the metal nano dot 312, it is necessary to appropriately adjust the heat treatment temperature and the heat treatment atmosphere.

Referring to FIG. 3C, the metal nano dots 312 are heat-treated in an oxygen (O ₂ ) atmosphere at a temperature slightly lower than the melting point of the material of the metal layer 310. When the metal layer 310 is made of Al, the Al nano dots may be heat-treated at a temperature of, for example, about 400 to 600 ° C. As a result, the metal part 312a, which is the central part of the metal nano dot 312, is completely oxidized, so that all parts of the metal nano dot 312 are changed to metal oxide, which is an insulator, thereby forming an insulator nano dot 314. . In the case of Al, all parts of the metal nano dots 312 are changed to aluminum oxide (Al ₂ O ₃ ) to form an insulator nano dot 314 made of Al ₂ O ₃ . At this time, in order to determine the size and density of the insulator nano dot 314, it is necessary to properly adjust the heat treatment temperature and the heat treatment atmosphere.

On the other hand, in the process of forming the insulator nano dot 314, by controlling the starting material and the deposition process conditions using the atomic layer deposition method, it is also possible to form a metal oxide film of the nano-dot form instead of the metal layer of the thin film form. In the case of using such a method, a predetermined surface pretreatment process for a substrate on which a metal oxide nano dot is to be formed may be separately required, in addition to control of starting materials and process conditions.

4A and 4B are cross-sectional views shown in order of process to explain another example of a method of forming an exemplary insulator nano dot suitable for use as the insulator nano dot 140 illustrated in FIGS. 1C-1F. In Figs. 4A and 4B, the same reference numerals as those in Figs. 1A to 1F refer to the same elements, and thus detailed description thereof is omitted here.

Referring to FIG. 4A, after the substrate on which the exothermic metal electrode layer 120 is exposed is prepared, a silicon nano dot 410 is formed on the exothermic metal electrode layer 120. The silicon nano dot 410 serves as a preparation layer for forming the insulator nano dot according to the present invention. In order to form the silicon nano dots 410, for example, a chemical vapor deposition method may be used. In this case, the silicon nano dot structure may be easily formed by appropriately controlling the starting materials and the deposition conditions.

Referring to FIG. 4B, the silicon nano dot 410 is nitrided using a nitriding process using nitrogen radicals to form silicon nitride nano dots 412. In this case, in order to completely nitride the silicon nano dots 410 to form silicon nitride nano dots 412 which are complete insulators, process conditions of the nitriding process using nitrogen radicals must be appropriately controlled.

In the process of forming the silicon nano dot 410 as described with reference to FIG. 4A, instead of the starting material for forming the silicon nano dot 410, the starting material for forming the silicon nitride nano dot 412 is optimized. The silicon nitride film in the form of a nano dot may be directly formed instead of the silicon nano dot 410 by supplying it on the exothermic metal electrode layer 120 under controlled conditions and controlling process conditions of a chemical vapor deposition method.

5A and 5B are schematic views showing an exemplary formation of an insulator nano dot structure suitable for use in the phase change memory device according to the present invention, respectively.

According to the present invention, the phase change material layer 150 (see FIG. 1F) and the heat generating metal electrode layer 120 (for manufacturing a phase change memory device including an insulator nano dot 140 (see FIG. 1F)) In order to minimize the contact area of FIG. 1F), as the insulator nano dot 140, a plurality of insulator nano dots 314 exemplarily illustrated in FIGS. 3A to 3C, or those manufactured in FIGS. 4A and 4B. As illustrated in FIG. 5A or FIG. 5B, the plurality of silicon nitride nano dots 412 illustrated in the process may be formed in a highly dense structure.

When the structure of the insulator nano dot 140 is formed in an arrangement as illustrated in FIG. 5A, the gap portion 510 surrounded by four nano dots 140a may have the phase change material layer 150 and the heat generation. The contact area with the metallic metal electrode layer 120 is determined.

When the structure of the insulator nano dot 140 is formed in the arrangement as illustrated in FIG. 5B, the gap portion 520 surrounded by three nano dots 140b may have the phase change material layer 150 and the heat generation. The contact area with the metallic metal electrode layer 120 is determined.

Here, the total contact area between the phase change material layer 150 and the heat generating metal electrode layer 120 may be defined by the opening of the gap portion 510 surrounded by four nano dots 140a as illustrated in FIG. 5A. The total area within 130a) or the total area within the opening 130a of the gap portion 520 surrounded by three nanodots 140b as illustrated in FIG. 5B is not determined. The reason for this is as follows. In the driving method of the phase change memory device illustrated in FIG. 1F, the phase change material layer 150 is formed through heat generated at a contact portion between the phase change material layer 150 and the heat generating metal electrode layer 120. The crystal state is changed, and the change in the crystal state of the phase change material layer 150 changes the resistance of the device and uses it as a memory. For this reason, each of the gap portions 510 or 520 surrounded by four or three nano dots 140a or 140b provided by the insulator nanodot structure according to the present invention illustrated in FIG. 5A or 5B are all in parallel. This is because it corresponds to a connected resistance element. That is, the minimum current required for the memory operation is sufficient to change the crystal state of the phase change material layer 150 present in one gap portion 510 or 520 surrounded by four or three nano dots. In other words, at this current value, the crystal state of the phase change material layer present in each gap portion 510 or 520 surrounded by four or three nano dots can be changed.

Of course, in the fabrication of the phase change memory device including the insulator nano dot structure according to the present invention, it cannot be expected that the insulator nano dot structure is always formed in the arrangement illustrated in FIG. 5A or 5B. For example, in the formation process of the said insulator nano dot, the structure which spaced apart each nano dot structure may not be closely contacted, and another layer of nano dots is formed on one layer of nano dot structure. May exist In the case of the former and the latter will be described in more detail as follows.

In the case of the former to form a structure in which the nano dot structures are not in close contact with each other, the phase change material layer 150 and the phase change material layer 150 may be formed using the insulator nano dot 140 structure in the phase change memory device according to the present invention. The purpose of the present invention, which is intended to minimize the contact area between the heat generating metal electrode layers 120, may not be sufficiently satisfied. That is, in the case where the nanodot structures are formed to be spaced apart from each other, the contact area between the phase change material layer 150 and the heat generating metal electrode layer 120 may be formed in the opening 130a. Is most likely determined by the sum of all parts where no nano dots are formed. In such a case, the characteristics of each phase change memory element constituting the memory array cannot be uniformly controlled because the contact area is likely to be determined differently for each element. Therefore, in order to fully utilize the advantages of the phase change memory device using the insulator nano dot according to the present invention, it is very important to sufficiently increase the density of the insulator nano dot 140 formed as illustrated in FIG. 5A or 5B. Do.

Also, even in the latter case in which another layer of nano dots is present on one layer of nano dot structure, the characteristics of the individual phase change memory devices cannot be uniformly controlled for the same reasons as described in the foregoing case. . Furthermore, in the latter case, the phase change material layer 150 to be formed on the insulator nano dot structure easily enters the gap between the adjacent nano dots due to the structure of the nano dots formed of two or more layers. It is likely to interfere.

In view of the above, in order to fully utilize the advantages of using insulator nano dots in the phase change memory device according to the present invention, as illustrated in FIG. 5A or 5B, a single layer of uniform insulator nano dot 140 structure is illustrated. It is very important to form.

6 is a graph showing the change in the contact area size of the phase change material and the electrode material in the phase change memory device with respect to the size of the insulator nano dot formed according to the present invention.

6, the X axis of the graph is the radius of the insulator nano dot formed by the method according to the invention, the Y axis is a phase change material in the phase change memory device structure according to the present invention including the insulator nano dot structure It is a contact size corresponding to the contact area of a layer and a heat generating metal electrode layer. The contact size of FIG. 6 represents the length of one side when it is assumed that the shape of the contact region between the phase change material layer and the heat generating metal electrode layer is square.

In Fig. 6, the line "A" is formed in the insulator nanodots formed by the method according to the present invention as shown in Fig. 5a very dense with each other so that the gap portion surrounded by the four nanodots contact the phase change memory device The relationship in the case of determining the area is shown. When the radius of one insulator nano dot is d ₁ , the contact area A ₁ may be represented by Equation 1.

A ₁ = (4-π) d ₁ ²

If the radius of the insulator nanodot (d ₁ ) is 5 nm, the length of one side of the square constituting the contact area A ₁ is 4.6 nm, and if the radius (d ₁ ) of the insulator nanodot is 10 nm, the contact area A _The length of one side of the square constituting ₁ is 9.3 nm. In other words, the radius (d ₁₎ there can be formed with the same structure as the insulator nanodots of about 10nm as presented in Figure 5a, it is a side can be manufactured of a phase change memory device having an ultra-fine contact area of about 9.3 nm.

In addition, in Fig. 6, the line "B", as shown in Fig. 5b is formed in a very dense insulator nano dot formed by the method according to the present invention so that the gap portion surrounded by the three nano dots of the phase change memory device The relationship in the case of determining the contact area is shown. When the radius of the insulator nano dot is d ₂ , the contact area A ₂ may be expressed by Equation 2.

A ₂ = (3 ^½ -π / 2) d ₂ ²

If the radius of the insulator nanodot (d ₂ ) is 5 nm, the length of one side of the square constituting the contact area A ₂ is 2.0 nm, and if the radius (d ₂ ) of the insulator nanodot is 10 nm, the contact area A _The side of the square which comprises ₂ is 4.0 nm in length. That is, if an insulator nano dot having a radius (d ₂ ) of about 10 nm can be formed as shown in FIG. 5B, it is possible to fabricate a phase change memory device having an ultra fine contact area having one side of about 4.0 nm. .

A phase change memory device according to the present invention includes a heat generating metal electrode layer formed on the first electrode layer and a phase change material layer in contact with the heat generating contact region in a first region which is a part of the heat generating metal electrode layer. A plurality of insulator nanodots are formed between the heat generating metal electrode layer and the phase change material layer to limit the contact area therebetween in the first region. The phase change memory device according to the present invention has an advantage of greatly reducing the value of a current required for driving the memory device by reducing the contact area between the phase change material layer and the electrode material to a nano size.

In the method of manufacturing a phase change memory device according to the present invention, in the fabrication of an ultrafine low power consumption phase change memory device including an insulator nano dot structure, a conventional method for forming a contact portion between a phase change material layer and an electrode material is used. Rather than performing top-down scaling using a lithography process, a bottom-up nano process is introduced to provide a phase change material layer and The contact area with the electrode material can be minimized. In addition, according to the method of manufacturing a phase change memory device according to the present invention, by using a plurality of insulator nano dot structures, it is possible to implement an extremely fine device of several nm size that cannot be realized by a conventional lithography process. Therefore, a low power consumption ultrafine phase change element can be easily manufactured by the method according to the present invention.

In addition, in the phase change memory device according to the present invention, the contact region between the phase change material layer and the electrode material provided through the plurality of insulator nano dots formed on the heat generating metal electrode layer is not composed of only one, but is a predetermined area. Since a plurality of nano dots are formed at the same time and the phase change material layer and the electrode material are in contact in a plurality of regions exposed between them, the nonuniformity of the contact area can be statistically reduced, resulting in power consumption of the phase change memory device. Can be greatly reduced.

In the above, the present invention has been described in detail with reference to preferred embodiments, but the present invention is not limited to the above embodiments, and various modifications and changes by those skilled in the art within the spirit and scope of the present invention. This is possible.

Claims (15)

A first electrode layer, A heat generating metal electrode layer formed on the first electrode layer, An insulating film pattern formed on the heat generating metal electrode layer and having an opening for exposing a first region which is a part of the heat generating metal electrode layer; A plurality of insulator nano dots formed on a surface of the heat generating metal electrode layer to prevent electrical contact between the heat generating metal electrode layer and the phase change material layer in a portion of the first region; A phase change formed on the plurality of insulator nano dots and the heat generating metal electrode layer in the opening and electrically contacting the heat generating metal electrode layer only in a contact region exposed between the plurality of insulator nano dots in the first region. Material layer, And a second electrode layer in contact with an opposite side of the phase change material layer in contact with the heat generating metal electrode layer. delete The method of claim 1, And the heat generating metal electrode layer and the phase change material layer are in contact with each other at a portion surrounded by adjacent insulator nano dots among the plurality of insulator nano dots. The method of claim 1, The insulator nano dot is a phase change memory device, characterized in that made of a metal oxide. The method of claim 1, The insulator nano dot is a phase change memory device, characterized in that made of silicon nitride. The method of claim 1, The plurality of insulator nano dots each have a hemispherical shape. The method of claim 6, The plurality of insulator nano dots each have a radius size of 10 nm or less. The method of claim 1, The phase change material layer is a phase change memory device, characterized in that made of an alloy of chalcogenide-based metal elements. Preparing a substrate having a first electrode layer formed on an upper surface thereof; Forming a heat generating metal electrode layer on the first electrode layer; Forming an insulating layer pattern on the heat generating metal electrode layer, the insulating layer pattern having an opening exposing a first region which is a part of the heat generating metal electrode layer; Forming a plurality of insulator nanodots on the heat generating metal electrode layer in the opening, and exposing the heat generating metal electrode layer in a contact region between adjacent insulator nano dots among the plurality of insulator nano dots. Forming nano dots, Forming a phase change material layer on the plurality of insulator nano dots and the heat generating metal electrode layer to enable electrical contact with the heat generating metal electrode layer only in the contact region; And forming a second electrode layer in contact with an upper surface of the phase change material layer. The method of claim 9, Forming a plurality of insulator nano dots Forming a metal layer on the heat generating metal electrode layer in the first region; Forming a plurality of metal nano dots from the metal layer by heat treatment in a nitrogen (N ₂ ) atmosphere, And forming the plurality of insulator nanodots from the plurality of metal nanodots by heat treatment in an oxygen (O ₂ ) atmosphere. The method of claim 10, The heat treatment in the nitrogen (N ₂ ) atmosphere and the heat treatment in the oxygen (O ₂ ) atmosphere are respectively performed at a temperature lower than the melting point of the constituent material of the metal layer. The method of claim 9, Forming a plurality of insulator nano dots And depositing a nano dot metal oxide layer on the exothermic metal electrode layer in the first region by using an atomic layer deposition method. The method of claim 9, Forming the plurality of insulator nano dots Forming a plurality of silicon nano dots on the heat generating metal electrode layer in the first region; And nitriding the plurality of silicon nano dots to form a plurality of silicon nitride nano dots. The method of claim 13, Method of manufacturing a phase change memory device, characterized in that for using the nitrogen radicals to nitride the plurality of silicon nano dots. The method of claim 9, Forming the plurality of insulator nano dots A method of manufacturing a phase change memory device comprising the step of forming a silicon nitride film in the form of a nano dot using chemical vapor deposition.

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