1279979 玖、發明說明： [發明所屬之技術領域] 本發明係關於一種電子音量裝置及該電 、 包丁曰I的測試太 法’邊夠提高出廠測試的效率。 [先前技術] 半導體元件的電子音量裝置已經普遍地作為類比音頻 號的音量調整用元件而受到使用。如圖u所示，電ϋ二 裝置為内建有類比電路的類比LSI;該類比電路係包本1里 複數個分接頭的可變電阻及放大器等，且該可變電二係有 分接頭信號（音量設定值）來連接複數個分接頭中的其中t 個。近年來的電子音量裝置的分接頭的分段數增加^多， 256段的分接頭也已經相當常見。 該電子音量裝置在製造時會接受出廠測試，而該出廠測 試中包含確保上述可變電阻的所有分接頭沒有短路等且正 常連接等測試。在該測試中，係如圖12(A)所示般地將邏輯 /貝J 4器連接於電子音f裝置LSI上，將一定之直流電壓（vh) 輸入電子音量裝置，藉由切換音量設定值來依序連接所有 等分接頭，依各音量設定值，以直流電壓測定電路來測定 有無對應於該音量設定值之正常等類比電壓V〇ut輸出。 [發明内容] 惟’對應於每一段的音量設定值之輸出電壓v〇ut的變化 置僅為數mV左右’為了能夠正確地加以測定，必須待輸出 電壓穩定後以高精確度的電壓測定電路進行測定，因此不 僅需對測定器的精確度進行要求，且如圖12(B)所示一般， 每一段的測定需費時數ms至數十ms的時間。為此，在採用 1279979 :實施256段的音量設定值控制的電子音量裝置時，為了對 每一段進行測試，不僅需時1秒至數秒，且如為音響用或多 聲道用的私子音量裝置時，會發生所需的測試時間會隨該 聲道的數目而增加的問題。 /鉍於此，本發明之目的在於提供一種電子音量裝置及 私子骨T測試方法，以解決上述課題，並提高電子音量裝 置在出廠時的測試效率。 申請專利範圍第1項之發明的特徵為包含：類比電路，其 二依複數&的目量设^值，對外部輸人之類比信號的信號 位準進行控制後，輸出為輸出信號；控制部，其係將外部 指示的音量設定值輸入至上述類比電路；測試電路，其係 在上述輸出信號輸人而有音量設定值輸人至類比電路時， 在對通骨1設定值輸入前後的上述輸出信號的信號位準大 J進行比較後’將比較結果以雙值的電壓值來輸出。 申請專利範圍第2項之發明的特徵為包含：複數個聲道份 ==路’其係依複純的音量設定值，對外部輸入之 二準進行控制後，輸出為輸出信號；控制 夕邵指不的各聲道之音量設定值輸入至對應聲 述類比電路；測試電路，其係對應於各聲道而設， 且在上述輸出信號輸入而有 ^ 眭，六孤士、、、、名曰直汉疋值輸入至類比電路 準幻量歧值輸人前後的上述輸出信號的信號位 小進行比較後，輸出比較結果；及編碼電;各 以 各聲道的比較結果進行邏輯 ’、.、 結果以雙值的電壓值來輸料和心，並將運算的 1279979 申g專利範圍弟3項之發明的特徵為上述測試電路係以 斬波型比車父器來對上述輸出信號的信號位準大小進行比 較0 申w專利範圍第4項之發明的特徵為一面對第i、2、或3 員、迅子㈢里裝置輸入指定電壓的直流信號作為上述類比 信號、，一面每次調降或調升一段來依序輸入音量設定值， 並監視對應於此而輸出的上述雙值電壓值，藉以判斷上述 電子音量裝置的良否。 匕私^目里裝置的測試方面’如上所述，係隨著輸入具有 田，私壓之直流#唬作為類比信號，依序輸入複數段的音 量設定值後，監視類线路有無輸w目對應之直流信號。 本：明係内建有測試電路’用以當有音量設定值由外部輸 ^時’依料量設定值來檢職比電路的輸出電壓有無正 常變化，並藉由輸出該檢測結果來提高該測試的效率。 在出廠測試巾’音量設定值係由最大值逐段下降至 ί由最小值逐段升高至最大值，使類比電路對應 值m认 因此在本發明中設有能夠對音量設定 值輸入則後的類比電路的輸 社mm 钿出电壓進行比較後輸出該比較 …果的測試電路，以針對音 相較於之前^每—段的輸出電壓 ，比lb 升’輸出比較結I :例如， 頟比私路所輸出的電壓比先 ，為高時輸出h(=5v)即可。以為低時輸叫=ov) 藉此’用以對該電子音香 面，由於可藉由^目Η裝置進行測試的測試裝置方 、"Α測試電路所輸出的雙值的電壓值 1279979 來進行測試，所以不僅可使用簡略的比較器，也可大幅縮 短測定時間。 此外’上述測試電路中已内建有電子音量裝置（LSI)，由 於配線所產生的浮游電容及電阻極小，因此輸出電壓能夠 迅速穩足且其精確度高。此外，由於並非測定出電壓的絕 對值，而係以先前的電壓與本次的電壓做比較，因此可簡 化電路的構造。 再者，測試電路的輸出係為類比電路的動作正常與否的 判定結果，因此即使測試對象為複數個聲道的電子音量裝 置，也旎夠同時對所有聲道進行測試：即，測試對象為複 數聲道的電子音量裝置時，如有任一聲道無法正常動作， 該電子音量裝置便屬不良，因此對所有聲道的判定結果進 行邏輯積運算（惟，比較結果的輸出係設定為正常=L時，依 電性在此則改採邏輯和運算），使得複數個聲道中任一聲道 不良時的輸出會反轉，便可一次對複數個聲道進行測試。 [實施方式] 以下將參照圖式，說明本發明之實施方式之電子音量裝 置（電子音量LSI)及其測試方法。 圖2為採用了相同之電子音量裝置（LSI) i的音訊放大器 之概略區塊圖。由CD唱盤及調諧器等之位於前段的電路所 輸入的類比音頻信號係介以緩衝器2而輸入至電子音量裝 置1的Vin端子。此外，緩衝器2為用以轉換阻抗的類比緩衝 放大器，在此並非必要者。電子音量裝置丨具有如圖丨所示 的構造，可藉由控制可變電阻丨丨及12，使得上述類比音頻 1279979 信號的信號位準受到調整後由V〇ut端子輸出。電子音量裝 置1輸出的類比音頻信號在經由功率放大器3的放大後，由 喇队4播放。 電子音量裝置1係連接有控制用的微電腦5。微電腦5能夠 輸出音量控制資料，該資料係用以對電子音量裝置進行類 比音頻信號的信號位準進行控制。該音量控制資料係在電 子音量裝置1内解碼為分接頭選擇信號後，輸入至可變電阻 11 及 12。 當音訊放大器的使用者操作旋轉編碼器6時，對應於該操 作的脈衝信號會輸入微電腦5 ;微電腦5會依該操作量來變 更音量設定值；當音量設定值變更時，該設定值會顯示於 顯示邵7，同時會產生對應於該音量設定值的音量控制資 料；微電腦5會以音量控制資料作為串行資料SDATAI，與序 列時脈信號SCLK同步地輸入電子音量裝置1;電子音量裝置 1在有序列信號輸入時，將電子音量裝置1的晶片選擇信號 CSN (有功低位準；active Low)設定為“L，，，而使串行資料的 輸入致能；接著，電子音量裝置丨在串行資料輸入之後，將 晶片選擇信號CSN設定為“H”時，電子音量裝置i會在信號升 起時對串行資料進行閃鎖，並依該資料（音量控制資料）來 對㉟比目頻仏號的信號位準進行控制。如此一來，對應於 使用者設定的音量設定值而產生的責量控制資料及上述分 接頭選擇信號會對應於本申請專利範圍各項的音量設定 值。 圖1為上述電子音量裝置1的内部區塊圖。該電子音量裝 1279979 置包含：可變電阻11及12、具有放大器13的類比電路9、控 制部10、解碼器14、零點觸發檢測電路15、振盪器16、解碼 器17、及S/P轉換電路18，且尚包含用以對上述類比電路9 進行測試的選擇器19及類比測試電路20。此外，外部輸出 入端子方面，則包含：類比信號輸入端子Vin、類比信號輸 出端子Vout、串行資料輸出端子SDATAO、晶片選擇信號輸 入端子CSN、序列時脈輸入端子SCLK、串行資料輸入端子 SDATAI、零點觸發控制端子ZCEN1及ZCEN2、測試模式設定 端子TEST—MODE。此外，如以從之說明，各端子的記號係 以表示各端子所輸出入的信號之記號來表示。 類比音頻信號係由類比信號輸入端子Vin輸入；該類比音 頻信號係供應至可變電阻11及零點觸發檢測電路。可變電 阻11及12方面，藉由兩者間的組合可提供256段的分接頭， 且能夠使藉由分接頭選擇信號TS1及TS2所選擇的任一組分 接頭連接於放大器13 :藉由從該選取的分接頭取出上述輸 入之類比音頻信號後，將該類比音頻信號輸入放大器13。 即，藉由選取之分接頭的位置，可調整類比音頻信號的衰 減量或放大量。該分接頭選擇信號TS1及TS2係上述微電腦5 所輸入之8位元音量控制資料經由解碼器14的解碼而成 者。藉由該8位元的音量控制資料，能夠在〇〇至+32 dB的範 圍内，對輸入之類比音頻信號的信號位準施以256段的控 制。 上述微電腦5所輸入的音量控制資料行資料）方面，當 S/P (串行/平行）轉換部18串晶片選擇端子CSN為“L”時，將讀 1279979 入作為與串行時脈SCLK同步地由串行資料輸入端子 SDATAI輸入的資料。尚且，當晶片選擇端子◦州為“η”時， 1買入的資料將受到閂鎖而傳送至控制部1〇。 控制部10中’ S/P轉換部18傳送來的音量控制資料將作為 分接頭選擇信號，經由解碼器14，而對可變電阻丨丨及^進行 汉定’惟在設定成不實施藉由零點觸發控制信號ZCEN1及 ZCEN2的組合所進行的零點觸發控制時，則設定成使s/p轉 換邵18傳送來的音量控制資料立即輸出至解碼器14後，解 碼器14依分接頭選擇選擇信號丁81及tS2來設定可變電阻u 及丨2 °另一方面，如設定成藉由零點觸發控制信號ZCEN1 及ZCEN2的組合進行的零點觸發控制時，係設定成在使s/p 轉換部18傳送來的音量控制資料在下一個緊接的零點觸發 時序時輸出至解碼器14，將分接頭選擇信號tsi及TS2設定 於可變電阻11及12。在此，零點觸發時序係指在振幅擴及+ 側及一側之兩側的輸入類比信號在通過〇 V時之時序，由於 使骨τ在該時序時變化也不致於使振幅波形不連續，因此 不會產生雜訊。為此，重視音質時，分接頭選擇信號TS1 及TS2係等待至此一時序時輸出。 零點觸發檢測電路15係對輸入類比信號與GNd電壓位準 (〇 V)進行比較以檢測出零點觸發時序（類比信號通過〇 V之 時序）後通知控制部10之電路。此外，振盪器16係藉由控制 部10而作為計時器來使用。亦即，如欲實施音量的零點觸 發控制時，音量控制資料在輸入後會等待零點觸發檢測電 路15輸入零點觸發檢測信號為止，惟等待時間超過指定時 -11 - 1279979 間後，如仍無零點檢測信號輸入時（例如DC偏移的小信號/ 等），當計時器的計時超過上述指定時間時，即使不在零點- 觸發時序，也施以音量控制。 此外，SDATAO為用以輸出S/P轉換邵18所儲存的设定資料 (上次輸入的資料）的端子。s/p轉換部18具有轉換暫存器， 用以緩衝由SDATAI輸入之串行資料’且介以SDATA〇依序將 先輸入的位元加以輸出。也可在該SDATA〇端子上以離菊鏈 連接方式連接其他同種的電子音量裝置SDATAI端子後’藉 _ 由圖2之微電腦5將複數個電子音量LSI份的晋量控制資料 加以_行輸出，對所有的電子音量LSI設定音量控制資料， 而實現多聲道控制。 如上所述，輸入之類比信號係藉由介以串行資料輸入端 ‘ 子SDATAI由外部輸入之音量控制資料’而受具有可變電阻 · 11及12以及放大器13的類比電路進行音量控制，惟該電子音 量裝置内建有類比測試電路20及選擇器19 ’用以測試該類 比電路（在此為可變電阻11及12)動作正常與否。當控制部10 _ 將測試模式信號TE輸出至類比測試電路20及選擇器19時 (測試模式設定端子TEST—MODE設為“H”時），實施測試模式 動作。 圖3及圖4為上述類比測試電路20之電路構造圖；圖5為電 子音量裝置出廠測試時之連線形態之圖；圖6為測試時之各 部信號之圖。 圖5中，出廠測試時，電子音量裝置1上連接有邏輯測試 器8。邏輯測試器8包含：探測信號驅動器（ping driver) 8a， -12- 1279979 其用以產生各種信號；及比較器8b，其用以判定輸入之電 壓係高於或低於指定之臨限值。探測信號驅動器8a連接於 Vin、CSN、SCLK、SDATAI、TEST_MODE。探測信號驅動器 8a係將TEST_MODE設定成能夠使控制部10在開始進行測試 時，將TE(用以指定測試模式之内部信號）設定為“H”，且將 TEST_MODE設定成能夠使控制部10在測試結束時，將TE設 定為“L” ；此外，當有指定的直流電壓（Vin)產生而輸入Vin 端子時，將音量控制資料SDATAI與晶片選擇信號CSN及串 行時脈信號SCLK同步地輸出。SDATAI係在每當有晶片選擇 信號CSN時，每次調降音量設定值一段。測試可對可變電阻 11及可變電阻分開來實施：在對可變電阻11進行測試時， 乃使可變電阻12的分接頭選擇信號TS2固定（固定成增益為 最大）後，藉由一段一段地調降可變電阻11之用以控制衰減 的分接頭選擇信號TS1，將音量控制資料輸入SDATAI;在對 可變電阻12進行測試時，乃使可變電阻11的分接頭選擇信 號TS1固定（固定成增益為最小）後，藉由一段一段地調降可 變電阻12之用以控制衰減的分接頭選擇信號TS2，將音量控 制資料輸入SDATAI 〇 對應於上述般的音量控制資料，電子音量裝置會如圖6(A) 所示一般，所輸出的輸出電壓Vout會相對於輸入電壓Vin— 段一段地逐段下降。惟，邏輯測試器8並非以上述Vout作為 觀察對象，而係藉由比較器8b對介以SDATAO輸出之類比測 試電路20之比較結果信號ATEST的“H/L”進行觀察。類比測 試電路20係如後所述般地在晶片選擇信號CSN由“L”上升至 1279979 “Η”時，即有新的音量控制資料輸入時，對類比電路之前後 的輸出電壓Vout進行比較，當目前的電壓比先前的電壓為 低時，輸出“L”作為ATEST，當輸出電壓Vout未下降時，貝《J 輸出“Η”作為ATEST。 邏輯測試器8之比較器8b能夠藉由判定該SDATAO為“Η” 或“L”，判定電子音量裝置有無正常動作，由於無需正確測 定出數mV的電壓，因此能夠在極短的時間（數百ns至數ps) 内，判定出一段的音量變化為正常或異常。 圖3中，電子音量裝置1内建的類比測試電路20具有由轉 換器31、P通路MOS電晶體32、及電容器33所構成之所謂的 斬波型比較電路30。即，轉換器31與P通路MOS電晶體32並 聯連接，當P通路MOS電晶體32上有閘極信號（一的閘極電壓） 輸入而成為開時，轉換器31的輸入側與輸出侧會短路。接 著，有放大器13之輸出的Vout介以電容器33((^)而供應至轉 換器31的輸入側上。尚且，在轉換器31的輸入侧配線圖案 與P通路MOS電晶體32之閘極側的配線圖案之間，產生有較 小的寄生電容（連接電容）Cs。上述電容器33的電容q係設 定成寄生電容Cs的數倍以上。 閘極信號形成電路29在有來自控制部10之測試模式設定 信號TE輸入時會致能，而與晶片選擇信號CSN之輸入同步 地輸出P通路閘極信號CNTP。 上述斬波型比較電路30中，當P通路閘極信號CNTP為“L” 時，P通路MOS電晶體32會成為開而使轉換器31的輸入侧與 輸出側短路。在此時，轉換器31的輸入端子的電位在由低 1279979 阻抗的輸出端子的電位所吸收後，輸入側及輸出側的電位 均會在轉換器31的臨限值Vti穩定下來。此時，當值為ν〇ι 之電壓輸入作為電壓Vout時，電容器33的電極間的電位差會 成為VcWti，而使該電位差份的電荷儲存於電容器33。由 於p通路閘極信號CNTP係與晶片選擇信號CSN同步地輸 出’因此音量控制資料會在轉換器31短路時輸入（晶片選擇 信號CSN為“L，，之區段中，SDATAI會輸入）。 隨後’晶片選擇信號CSN升起時，類比電路的輸出v〇ut 會依輸入的音量控制資料而變化成v〇2，同時p通路閘極信 號CNTP會成為“η”且p通路M〇S電晶體32成為關，使得該變 化之V〇ut=V〇2出現在電容器33的輸入侧的電極上。此時，電 春詻33具有之電位差為如上述之v〇i_Vti，因此電容器的轉 換器31侧上會出現V〇2_( v〇i_Vti)的電位；即，出現僅由轉換 器31的臨限值Vtl相差ν〇2_ν〇ι電位。若係依（由上述邏輯測試 器8輸入之）音量控制資料之控制而調降v〇ut—段時，v〇2_v〜 會為負值，而轉換器31會對應於此而輸出“H” ；另一方面， V〇2_V〇1會為正值時，轉換器31會輸出“L，，。因此，藉由將該 斬波型比較器30的輸出電壓作為ATEST信號而*sdatac^ 出，能夠對類比電路之輸出電壓v〇ut在音量控制資料產生 一段變化時之相對應變化，以“H/L”的雙值來加以輸出。 此外，如V〇2及V〇1具有相同電位而使ν〇^ν〇ι=(^，由於 不確定轉換器31的輸出電壓，“H/L”兩者均能輸出，因此分 接頭短路等情況中的CSN前後的電壓相同時，當時的判定結 果的可靠性會下降。為此，該斬波型比較器3〇中，乃積極 -15- 1279979 、用上述寄生電谷Cs，使得p通路MOS電晶體32為關時之 寄生包各csw包荷量之電壓施加於轉換器3ι，而產生如圖 ()斤π之偏置。藉此，轉換器3丨的輸出在預設上係向“L” 側偏置，僅在v〇2_ ν〇^生正常的電壓變化時，使轉換器^ 輸出“H”。 此外’轉換器34係一種電路，其係能夠配合比較器的臨 限值輸出而進行轉換，並且為能夠防止將斬波型比較器的 輸出保持在咼阻抗且連接於輸出側的電路所造成的影響。 圖3中，雖僅連接一段的斬波型比較器3〇，當轉換器“的 增益相對於輸入之電位差（ν〇2_ν〇ι)顯得不足時，轉換器31 的輸出不會具有“H/L”的整個振幅，而係在線性放大區域來 輸出中間值。在此情況中，如圖4所示一般，可藉由串聯兩 段的斬波型比較器30，使得輸出能夠進行“H/L，，的整個振幅 而實現雙值輸出。採用如圖4所示的構造時，由於增加“固 轉換器，輸出的電壓的“H/L”會反轉，然而藉由以非反轉的 緩衝器35來取代轉換器來作為最後一段的緩衝器，便可使 輸出的信號的極性能與圖3相同。 圖6(A)及（B)所示的ATEST及SDATAO的各信號為在如圖4 所示般地將2個斬波型比較器串聯時的波形。在該圖6(B) 中’晶片選擇仏號CSN(的L”區間）具有與串行時脈sCLk同 步之SDATAI的資料長度相當的位元長度，約數μ8左右。此 外，晶片選擇信號的間隔（CSN=“H，，的區間）則為數叩至1〇 μ8 左右。音量控制資料D則係與各晶片選擇信號同步地輸入。 該音量控制資料為如上述地每次調降音量1段的資料·。邏輯 -16- 1279979 測試器8的比較器在晶片選擇信號CSN上升成‘‘H，，後，將以數 — 百ns至數的時序來讀取SDATA0( ATEST信號），以檢測出該 電壓的“H/L”。此時，如該信號為“L”時，將判定電子音量 裝置在此段的動作屬正常；如該信號仍為“H”時，則判定該 電子音量裝置不合格。當電子音量裝置在所有階段的動作 均為正常時，則判定該電子音量裝置為合格品。 圖7及圖8為上述類比測試電路之其他實施方式之圖。在 該類比測試電路20,中，採用了 N通路MOS電晶體32,，取代 _ 圖3及圖4所示之斬波型比較器的p通路m〇s電晶體32。圖1 之類比測試電路20中，P通路MOS電晶體32的閘極配線圖案 為低電位動作者，因此寄生電容（^會供應正電荷至轉換器 31的輸入端子，使得轉換器31的輸入電壓ya朝正侧偏置； 惟，圖7的斬波型比較器中的n通路MOS電晶體32f的閘極配 ’ 線圖案為高電位動作者，寄生電容Cs，係將負電荷供應至轉 換器31的輸入端子，使轉換器31的輸入電壓％向負側偏 置。接著，該類比測試電路的閘極信號形成電路29,會與晶 籲 片選擇信號同步地輸出N通路閘極信號CNTN。該圖（A)所示 為該N通路型式之斬波型比較器3〇，僅設一段的例子；該圖 (B)所示為該N通路型式之斬波型比較器30,設有兩段的例 子。 圖8所示的為圖7(B)之内建有類比測試電路之電子音量 裝置在進行測試時之該類比測試電路及邏輯測試器之各部 份的信號：圖8(B)中，晶片選擇信號CSN的區間及晶片選擇 信號的間隔係與圖6(B)所示的情況相同。音量控制資料係 -17- 1279979 與各晶片選擇信號同步地輸入。該音量控制資料為逐次調 升音量1段的資料。邏輯測試器8的比較器在晶片選擇信號 CSN上升成“H”後，將以數百ns至數的時序來讀取SDATAO (ATEST信號），以檢測出該電壓的“H/L”。此時，如該信號 為“Η”時，將判定電子音量裝置在此段的動作屬正常；如該 信號降至“L”時，則判定該電子音量裝置不合格。當電子音 量裝置在所有階段的動作均為正常時，則判定該電子音量 裝置為合格品。 此外，圖9所示的為類比測試電路31之一例，其具有之斬 波至比較器30"係使Ρ通路MOS電晶體32及Ν通路MOS電晶體 32f雙方均連接於轉換器31。該類比測試電路之閘極信號形 成電路29"能夠輸出P通路閘極信號CNTP及N通路閘極信號 CNTN兩者，並依測試模式選擇信號TEST—MODEP的“H/L”來 選擇並輸出兩者的其中一方；圖1所示的TEST_MODEP便為 該測試模式選擇信號。TEST_MODEP能夠藉由圖1之解碼器 17的輸入TEST_MODE、ZCEN卜及ZCEN2的組合而由外部進 行設定；當輸入該組合之信號時，控制部10會將 TEST_MODEP向測試電路輸出。此外，也可設置2個 TEST_MODE端子。 測試模式設定信號TE為“H”時，如測試模式選擇信號 TEST一MODEP同時成為“H”的話，閘極信號形成電路29"會將 N通路閘極信號CNTN固定成“L”且將P通路閘極信號與晶片 選擇信號同步進行輸出；藉此，可如圖6所示一般地逐段調 降Vout以進行測試。相反地，測試模式設定信號TE為“H” 1279979 時，如測試模式選擇信號TEST_MODEP為“L”的話，閘極信 號形成電路29"會將P通路閘極信號CNTN固定成“H”且將N 通路閘極信號與晶片選擇信號同步進行輸出；藉此，可如 圖8所示一般地逐段調升Vout以進行測試。 此實施方式中，雖採在外部設置測試模式設定端子 TEST_MODE，以在測試模式設定端子TEST—MODE的電位上 升為“H”時進入測試模式，惟也可在有特別的串行資料輸入 至SDATAI時，使控制部10對應於此而在内部將TE設為“H” ： 如此一來，能夠減少LSI的端子。此外，電子音量裝置在進 行實裝時，測試模式設定端子TEST-MODE在使用上係加以 接地（固定於“L”）。 上述說明内容中，為簡化說明，雖以類比電路為1聲道的 電子音量裝置來加以說明，惟本發明也同樣適用於内建有 複數個聲道之類比電路的電子音量裝置。在此情況中，如 圖10所示一般，將複數聲道之類比電路9-1至η個別設於類比 測試電路20-1至η，使各類比測試電路的輸出ATEST1至η在編 碼器40整合成1個信號ATEST後，輸出至選擇器19即可：測 試模式中，如欲使類比測試電路20在Vout正常地下降或上升 時輸出“H”時，將編碼器40設為AND電路，使其僅在所有的 類比測試電路20輸出“H”時輸出“H” ；測試模式中，如欲使 類比測試電路20在Vout正常地變化時輸出“l”時，將編碼器 40設為OR電路（低電位動作的AND電路），使其僅在所有的類 比測試電路輸出“L”時輸出“L”。此外，使編碼器40能夠依 上述TEST一MODEP信號在AND電路及OR電路間進行切換即 1279979 可° 上述只施例中，雖然類比測試電路2〇係内建於電予音量 裝置1内，然而也可將類比測試電路20與電子音量裝置^分 開來設置。 如上述般，依本實施方式，由於利用用以輸出串行資料 之SDATAO端子來輸出類比測試電路2〇的比較結果信號 ATEST ’ g[此能夠省下所需的端子數。1279979 玖, invention description: [Technical field to which the invention pertains] The present invention relates to an electronic volume device and the test method of the electric and the packaged one, which is sufficient to improve the efficiency of the factory test. [Prior Art] An electronic volume device of a semiconductor element has been commonly used as a volume adjustment element of an analog audio number. As shown in FIG. u, the second device is an analog LSI with an analog circuit built in; the analog circuit is a variable resistor and an amplifier of a plurality of taps in the first embodiment, and the variable electric second has a tap. The signal (volume set value) is used to connect t of the plurality of taps. In recent years, the number of segments of taps of electronic volume devices has increased, and 256-segment taps have become quite common. The electronic volume device is subjected to a factory test at the time of manufacture, and the factory test includes a test for ensuring that all of the taps of the variable resistor are not short-circuited or the like and are normally connected. In this test, as shown in FIG. 12(A), a logic/shell device is connected to the electronic sound device LSI, and a certain DC voltage (vh) is input to the electronic volume device by switching the volume setting. The value is connected to all the aliquots in sequence, and the DC voltage measuring circuit determines whether there is a normal analog voltage V〇ut output corresponding to the volume setting value according to each volume setting value. [Explanation] Only the change of the output voltage v〇ut corresponding to the volume setting value of each segment is only about several mV. In order to be able to be accurately measured, it is necessary to stabilize the output voltage with a high-accuracy voltage measuring circuit. The measurement is not only required for the accuracy of the measuring device, but as shown in Fig. 12(B), the measurement of each segment takes a time of several ms to several tens of ms. For this reason, when using 1279979: an electronic volume device controlled by a volume setting of 256 segments, in order to test each segment, it takes not only 1 second to several seconds, but also a private volume for audio or multi-channel. When the device is installed, the problem that the required test time increases with the number of channels occurs. Accordingly, it is an object of the present invention to provide an electronic volume device and a private bone T test method for solving the above problems and improving the test efficiency of the electronic volume device at the time of shipment. The invention of claim 1 is characterized in that it comprises: an analog circuit, wherein the value of the complex number is set according to the multiplicity & and the signal level of the analog signal of the external input is controlled, and the output is an output signal; And inputting the volume setting value of the external indication to the analog circuit; the test circuit is configured before the output signal is input and the volume setting value is input to the analog circuit, before and after the input of the setting value of the bone 1 After the signal level of the above output signal is large J, the comparison result is output as a double-valued voltage value. The invention of claim 2 of the patent scope is characterized in that: a plurality of channel parts == roads are selected according to the volume setting value of the complex pure, and after outputting the second input of the external input, the output is an output signal; The volume setting value of each channel is not input to the corresponding voice analog circuit; the test circuit is set corresponding to each channel, and the input signal is input and there are ^ 眭, 六孤士,,,,,,曰 疋 疋 输入 输入 输入 类 类 类 类 类 类 类 类 类 类 类 类 类 类 类 类 类 类 类 类 类 类 类 类 类 类 类 类 类 类 类 类 类 类 类 类 类 类 类 类 类 类 类 类 类The result is a double-valued voltage value for the feed and the heart, and the invention of the invention of the third aspect of the operation is characterized in that the test circuit is a signal of the output signal by a chopper type than the parent device. Comparison of the level of the size 0 The invention of the fourth aspect of the patent scope is characterized by a DC signal input to a specified voltage in the device of the i, 2, or 3, and the third (3) device as the analog signal, each time Down or down Period of the double-voltage value sequentially input to the volume setting value, and monitors the output in response thereto, whereby the nondefective determination of the electronic volume apparatus. In the test aspect of the device in the private sector, as described above, with the input of the DC, the private voltage of the direct current #唬 as the analog signal, sequentially input the volume setting value of the complex segment, the monitoring line has no corresponding DC signal. This: The built-in test circuit of the Ming system is used to check whether the output voltage of the circuit is normal or not when the volume setting value is externally input, and the output voltage of the circuit is improved by outputting the detection result. The efficiency of the test. In the factory test towel, the volume setting value is decreased from the maximum value to the gradual increase from the minimum value to the maximum value, so that the analog circuit corresponding value m is recognized. Therefore, in the present invention, the volume setting value can be input. Comparing the input voltage of the analog circuit with the output voltage of the analog output, the output of the comparison circuit is compared with the output voltage of the previous section, and the output voltage is compared with the output voltage of lb liters: for example, the ratio is The voltage output by the private road is higher than the first, and when it is high, it can output h (= 5v). I think that the low-level input = ov) is used to use the two-valued voltage value of 1279979 for the electronic sound-scented surface, which can be tested by the test device, and the test circuit. Tests are performed, so not only can you use a simple comparator, but you can also shorten the measurement time. In addition, the electronic sound volume (LSI) is built in the above test circuit. Since the floating capacitance and the resistance generated by the wiring are extremely small, the output voltage can be quickly stabilized and its accuracy is high. Further, since the absolute value of the voltage is not measured, the previous voltage is compared with the current voltage, so that the structure of the circuit can be simplified. Furthermore, the output of the test circuit is the result of the normal operation of the analog circuit, so even if the test object is an electronic volume device of a plurality of channels, it is sufficient to test all the channels simultaneously: that is, the test object is When the electronic volume device of the multi-channel is not working properly, the electronic volume device is defective, so the logical product is calculated for the judgment results of all the channels (however, the output of the comparison result is set to normal) When =L, the power is changed here to take the logical sum operation), so that the output of any of the plurality of channels is reversed, and the plurality of channels can be tested at one time. [Embodiment] Hereinafter, an electronic volume device (electronic volume LSI) and a test method thereof according to an embodiment of the present invention will be described with reference to the drawings. Fig. 2 is a schematic block diagram of an audio amplifier using the same electronic volume device (LSI) i. The analog audio signal input from the circuit in the preceding stage, such as a CD player and a tuner, is input to the Vin terminal of the electronic volume device 1 via the buffer 2. Further, the buffer 2 is an analog buffer amplifier for converting impedance, which is not necessary here. The electronic volume device has a configuration as shown in FIG. ,, and the variable level resistors 12 and 12 are controlled so that the signal level of the analog audio 1279979 signal is adjusted and outputted by the V〇ut terminal. The analog audio signal output from the electronic volume device 1 is played by the racquet 4 after being amplified by the power amplifier 3. The electronic volume device 1 is connected to a microcomputer 5 for control. The microcomputer 5 is capable of outputting volume control data for controlling the signal level of the analog audio signal to the electronic volume device. The volume control data is decoded into a tap selection signal in the electronic volume device 1 and input to the variable resistors 11 and 12. When the user of the audio amplifier operates the rotary encoder 6, the pulse signal corresponding to the operation is input to the microcomputer 5; the microcomputer 5 changes the volume setting value according to the operation amount; when the volume setting value is changed, the setting value is displayed. When the Shao 7 is displayed, the volume control data corresponding to the volume setting value is generated at the same time; the microcomputer 5 inputs the electronic volume device 1 with the volume control data as the serial data SDATAI in synchronization with the sequence clock signal SCLK; the electronic volume device 1 When the sequence signal is input, the chip selection signal CSN (active low level; active low) of the electronic volume device 1 is set to "L," to enable the input of the serial data; then, the electronic volume device is placed in the string After the line data is input, when the wafer selection signal CSN is set to "H", the electronic volume device i flashes the serial data when the signal rises, and compares the frequency according to the data (volume control data). The signal level of the nickname is controlled. In this way, the ruling control data corresponding to the volume setting value set by the user and the above tap selection The number corresponds to the volume setting value of each of the patent claims. Fig. 1 is an internal block diagram of the electronic volume device 1. The electronic volume device 1279979 includes: variable resistors 11 and 12, analog circuit with amplifier 13 9. The control unit 10, the decoder 14, the zero trigger detection circuit 15, the oscillator 16, the decoder 17, and the S/P conversion circuit 18, and further includes a selector 19 and an analogy for testing the analog circuit 9 described above. The test circuit 20. In addition, the external input and output terminals include: analog signal input terminal Vin, analog signal output terminal Vout, serial data output terminal SDATAO, wafer selection signal input terminal CSN, serial clock input terminal SCLK, serial The data input terminal SDATAI, the zero trigger control terminals ZCEN1 and ZCEN2, and the test mode setting terminal TEST_MODE. Further, as described above, the symbols of the respective terminals are indicated by symbols indicating the signals input from the respective terminals. Analog audio The signal is input by the analog signal input terminal Vin; the analog audio signal is supplied to the variable resistor 11 and the zero point trigger detecting circuit. In terms of the variable resistors 11 and 12, a 256-segment tap can be provided by a combination of the two, and any one of the component taps selected by the tap select signals TS1 and TS2 can be connected to the amplifier 13: After the selected tap takes out the analog audio signal of the input, the analog audio signal is input to the amplifier 13. That is, by selecting the position of the tap, the attenuation or amplification of the analog audio signal can be adjusted. The signals TS1 and TS2 are obtained by decoding the 8-bit volume control data input by the microcomputer 5 via the decoder 14. The volume control data of the 8-bit can be in the range of 〇〇 to +32 dB. A 256-segment control is applied to the signal level of the analog audio signal of the input. In the volume control data line data input by the microcomputer 5, when the S/P (serial/parallel) conversion unit 18 serial chip selection terminal CSN is "L", the read 1279979 is read as being synchronized with the serial clock SCLK. The data input by the serial data input terminal SDATAI. Moreover, when the wafer selection terminal Cangzhou is "n", 1 bought data will be latched and transmitted to the control unit 1〇. The volume control data transmitted from the 'S/P conversion unit 18' in the control unit 10 is used as a tap selection signal, and the variable resistors 丨丨 and ^ are set to be determined by the decoder 14 but are not implemented by When the zero point trigger control by the combination of the zero trigger control signals ZCEN1 and ZCEN2 is set, the volume control data transmitted by the s/p conversion Shao 18 is immediately output to the decoder 14, and the decoder 14 selects the selection signal according to the tap. D1 and tS2 are used to set the variable resistors u and 丨2 °. On the other hand, if the zero-point trigger control by the combination of the zero-trigger control signals ZCEN1 and ZCEN2 is set, the s/p conversion unit 18 is set. The transmitted volume control data is output to the decoder 14 at the next immediately zero-trigger timing, and the tap selection signals tsi and TS2 are set to the variable resistors 11 and 12. Here, the zero-trigger timing refers to the timing of the input analog signal on the side of the amplitude spread + side and the side of the one side passing through 〇V. Since the change of the bone τ at this timing does not cause the amplitude waveform to be discontinuous, Therefore, no noise is generated. For this reason, when the sound quality is emphasized, the tap selection signals TS1 and TS2 wait for output to this timing. The zero point trigger detecting circuit 15 compares the input analog signal with the GNd voltage level (?V) to detect the zero point trigger timing (the analog signal passes through the timing of 〇V), and then notifies the circuit of the control unit 10. Further, the oscillator 16 is used as a timer by the control unit 10. That is, if the zero-point trigger control of the volume is to be implemented, the volume control data will wait for the zero-point trigger detection circuit 15 to input the zero-point trigger detection signal after input, but if the waiting time exceeds the specified time between -11 - 1279979, if there is still no zero point When detecting signal input (such as small signal of DC offset / etc.), when the timer counts above the specified time, even if it is not at the zero-trigger timing, the volume control is applied. In addition, SDATAO is a terminal for outputting the setting data (the last input data) stored in the S/P conversion port 18. The s/p conversion unit 18 has a conversion register for buffering serial data input by SDATAI and outputting the first input bit in sequence via SDATA. It is also possible to connect the SDATAI terminal of the same kind of electronic volume device to the SDATA terminal by daisy chain connection, and then use the microcomputer 5 of FIG. 2 to output the quantity control data of the plurality of electronic volume LSI copies. Multi-channel control is implemented by setting volume control data for all electronic volume LSIs. As described above, the analog signal of the input is controlled by the analog circuit having the variable resistors 11 and 12 and the amplifier 13 by means of the serial data input terminal 'sub SDATAI externally input volume control data', but The electronic volume device has an analog test circuit 20 and a selector 19' built therein to test whether the analog circuit (here, the variable resistors 11 and 12) operates normally or not. When the control unit 10_ outputs the test mode signal TE to the analog test circuit 20 and the selector 19 (when the test mode setting terminal TEST_MODE is set to "H"), the test mode operation is performed. 3 and 4 are circuit diagrams of the analog test circuit 20; Fig. 5 is a diagram showing the connection form of the electronic volume device at the time of factory test; and Fig. 6 is a diagram showing signals of each part during the test. In Fig. 5, a logic tester 8 is connected to the electronic volume device 1 at the time of factory test. The logic tester 8 includes a ping driver 8a, -12-1279979 for generating various signals, and a comparator 8b for determining that the input voltage is above or below a specified threshold. The probe signal driver 8a is connected to Vin, CSN, SCLK, SDATAI, TEST_MODE. The probe signal driver 8a sets TEST_MODE so that the control unit 10 can set TE (internal signal for specifying the test mode) to "H" when starting the test, and set TEST_MODE to enable the control unit 10 to test. At the end, TE is set to "L". Further, when a designated DC voltage (Vin) is generated and input to the Vin terminal, the volume control data SDATAI is output in synchronization with the wafer selection signal CSN and the serial clock signal SCLK. SDATAI adjusts the volume setting value each time there is a wafer selection signal CSN. The test can be implemented by separately dividing the variable resistor 11 and the variable resistor: when the variable resistor 11 is tested, the tap selection signal TS2 of the variable resistor 12 is fixed (fixed to a maximum gain) by a section. The tap selection signal TS1 for controlling the attenuation of the variable resistor 11 is turned off one by one, and the volume control data is input to the SDATAI; when the variable resistor 12 is tested, the tap selection signal TS1 of the variable resistor 11 is fixed. After being fixed to the minimum gain, the volume control data is input to SDATAI 〇 corresponding to the above-mentioned volume control data by electronically decreasing the tap selection signal TS2 for controlling the attenuation of the variable resistor 12 for a period of time. As shown in Figure 6(A), the output voltage Vout will be decreased step by step with respect to the input voltage Vin. However, the logic tester 8 does not observe the Vout as the observation target, but observes the "H/L" of the comparison result signal ATEST of the analog test circuit 20 via the comparator 8b by the comparator 8b. The analog test circuit 20 compares the output voltage Vout before and after the analog circuit when the wafer selection signal CSN rises from "L" to 1279979 "Η" as described later, that is, when a new volume control data is input, When the current voltage is lower than the previous voltage, "L" is output as ATEST, and when the output voltage Vout is not decreased, "J output "Η" is taken as ATEST. The comparator 8b of the logic tester 8 can determine whether the electronic volume device is operating normally by determining whether the SDATAO is "Η" or "L", and it is possible to detect the voltage of several mV correctly, so that it can be in a very short time (number Within a hundred ns to several ps), it is determined that the volume change of a section is normal or abnormal. In Fig. 3, the analog test circuit 20 built in the electronic volume device 1 has a so-called chopper type comparison circuit 30 composed of a converter 31, a P-channel MOS transistor 32, and a capacitor 33. That is, the converter 31 is connected in parallel with the P-channel MOS transistor 32. When the gate signal (the gate voltage of one) is input to the P-channel MOS transistor 32, the input side and the output side of the converter 31 are turned on. Short circuit. Next, Vout having the output of the amplifier 13 is supplied to the input side of the converter 31 via the capacitor 33 ((^). Further, on the input side wiring pattern of the converter 31 and the gate side of the P path MOS transistor 32 A small parasitic capacitance (connection capacitance) Cs is generated between the wiring patterns. The capacitance q of the capacitor 33 is set to be several times or more the parasitic capacitance Cs. The gate signal forming circuit 29 is tested by the control unit 10. When the mode setting signal TE is input, the P-channel gate signal CNTP is output in synchronization with the input of the wafer selection signal CSN. When the P-channel gate signal CNTP is "L" in the chopping type comparison circuit 30, The P-channel MOS transistor 32 is turned on to short-circuit the input side and the output side of the converter 31. At this time, the potential of the input terminal of the converter 31 is absorbed by the potential of the output terminal having a low impedance of 1,279,979, and the input side. The potential on the output side is stabilized at the threshold value Vti of the converter 31. At this time, when the voltage input is ν〇ι as the voltage Vout, the potential difference between the electrodes of the capacitor 33 becomes VcWti, and Electricity The differential charge is stored in the capacitor 33. Since the p-channel gate signal CNTP is output in synchronization with the wafer selection signal CSN, the volume control data is input when the converter 31 is short-circuited (the wafer selection signal CSN is "L," In the segment, SDATAI will input.) Then, when the wafer selection signal CSN rises, the output of the analog circuit v〇ut will change to v〇2 according to the input volume control data, and the p-channel gate signal CNTP will become “η”. And the p-channel M〇S transistor 32 is turned off, so that the change V〇ut=V〇2 appears on the electrode on the input side of the capacitor 33. At this time, the electric spring 33 has a potential difference as described above. 〇i_Vti, therefore, the potential of V〇2_(v〇i_Vti) appears on the converter 31 side of the capacitor; that is, the potential difference ν〇2_ν〇ι appears only by the threshold value Vtl of the converter 31. When the above-mentioned logic tester 8 inputs the volume control data to control the v〇ut-segment, v〇2_v~ will be a negative value, and the converter 31 will output "H" corresponding thereto; on the other hand, When V〇2_V〇1 is positive, converter 31 will output “L, Therefore, by outputting the output voltage of the chopper-type comparator 30 as an ATEST signal, the output voltage v〇ut of the analog circuit can be changed correspondingly when the volume control data changes. In addition, if V〇2 and V〇1 have the same potential, ν〇^ν〇ι=(^, since the output voltage of the converter 31 is uncertain, “H/L "Either both can be output. Therefore, when the voltages before and after the CSN in the case where the tap is short-circuited or the like are the same, the reliability of the judgment result at that time is lowered. Therefore, in the chopper type comparator 3, it is active -15-1279979, and the parasitic electric valley Cs is used, so that the voltage of each csw package of the parasitic package of the p-channel MOS transistor 32 is applied to the conversion. The device 3ι, and produces the offset of the figure ) π. Thereby, the output of the converter 3丨 is biased toward the "L" side by a preset, and the converter ^ is output "H" only when a normal voltage change occurs. Further, the 'converter 34 is a circuit that can be converted in accordance with the threshold output of the comparator, and is a circuit that can prevent the output of the chopper-type comparator from being held at the 咼 impedance and connected to the output side. influences. In Fig. 3, although only one segment of the chopper type comparator 3 is connected, when the gain of the converter "the potential difference with respect to the input (ν〇2_ν〇ι) appears insufficient, the output of the converter 31 does not have "H/". The entire amplitude of L" is in the linear amplification area to output the intermediate value. In this case, as shown in Fig. 4, the output can be "H/" by the two-stage chopper type comparator 30 in series. L,, the entire amplitude of the two-value output. When the configuration shown in FIG. 4 is adopted, the "H/L" of the output voltage is inverted due to the addition of the "solid converter", but the converter is replaced by the non-inverted buffer 35 as the last segment. The buffer can make the output signal have the same performance as that of Figure 3. The signals of ATEST and SDATAO shown in Figures 6(A) and (B) are two chopping types as shown in Figure 4. The waveform when the comparators are connected in series. In Fig. 6(B), the 'wafer selection code CSN (L' interval) has a bit length corresponding to the data length of the SDATAI synchronized with the serial clock sCLk, which is about several μ8. Further, the interval of the wafer selection signal (the interval of CSN = "H,") is about several 叩 to about 1 〇 μ 8. The volume control data D is input in synchronization with each wafer selection signal. The volume control data is as described above. Sub-adjustment of the volume 1 data. Logic-16-1279979 The comparator of the tester 8 reads the SDATA0 at the timing of the number-100 ns to the number when the wafer selection signal CSN rises to ''H'. ATEST signal) to detect the "H/L" of the voltage. At this time, if the signal is "L", it will be determined that the operation of the electronic volume device in this segment is normal; if the signal is still "H" And determining that the electronic volume device is unqualified. When the operation of the electronic volume device is normal at all stages, determining that the electronic volume device is a good product. FIGS. 7 and 8 are diagrams of other embodiments of the analog test circuit. In the analog test circuit 20, an N-channel MOS transistor 32 is used instead of the p-channel m〇s transistor 32 of the chopper-type comparator shown in FIGS. 3 and 4. The analogy test of FIG. In the circuit 20, the gate wiring of the P-channel MOS transistor 32 The pattern is a low potential actor, so the parasitic capacitance (^ will supply a positive charge to the input terminal of the converter 31 such that the input voltage ya of the converter 31 is biased toward the positive side; however, in the chopper type comparator of Figure 7 The gate of the n-channel MOS transistor 32f is a high-potential, and the parasitic capacitance Cs supplies a negative charge to the input terminal of the converter 31, and the input voltage % of the converter 31 is biased to the negative side. Then, the gate signal forming circuit 29 of the analog test circuit outputs the N-channel gate signal CNNT in synchronization with the crystal chip selection signal. The (N) type chopper type comparator 3 is shown in the figure (A). 〇, only one example is shown; the figure (B) shows the N-channel type chopper type comparator 30, which is provided with two examples. Figure 8 shows the built-in of Figure 7(B). The electronic volume device of the analog test circuit is used to test the signal of each part of the test circuit and the logic tester: in FIG. 8(B), the interval of the wafer selection signal CSN and the interval of the wafer selection signal are as shown in FIG. The situation is the same as shown in (B). Volume control data is -17-1279979 Each of the wafer selection signals is input synchronously. The volume control data is data of one stage of the volume up. The comparator of the logic tester 8 will have a timing of several hundred ns to several after the wafer selection signal CSN rises to "H". To read SDATAO (ATEST signal) to detect the "H/L" of the voltage. At this time, if the signal is "Η", it will be determined that the action of the electronic volume device in this segment is normal; if the signal is dropped When it is "L", it is determined that the electronic volume device is unsatisfactory. When the operation of the electronic volume device is normal at all stages, it is determined that the electronic volume device is a good product. In addition, the analog test circuit shown in FIG. In one example of 31, the chopper-to-comparator 30" is configured such that both the NMOS via transistor MOS transistor 32 and the NMOS via transistor MOS transistor 32f are connected to the converter 31. The gate signal forming circuit 29" of the analog test circuit can output both the P-channel gate signal CNTP and the N-channel gate signal CNNT, and select and output two according to the "H/L" of the test mode selection signal TEST_MODEP. One of the parties; TEST_MODEP shown in Figure 1 selects the signal for the test mode. TEST_MODEP can be externally set by the combination of the inputs TEST_MODE, ZCENb, and ZCEN2 of the decoder 17 of Fig. 1. When the combined signal is input, the control unit 10 outputs TEST_MODEP to the test circuit. In addition, two TEST_MODE terminals can be set. When the test mode setting signal TE is "H", if the test mode selection signal TEST_MODEP becomes "H" at the same time, the gate signal forming circuit 29" fixes the N-channel gate signal CNNT to "L" and sets the P path. The gate signal is output in synchronization with the wafer selection signal; thereby, Vout can be generally adjusted step by step as shown in FIG. 6 for testing. Conversely, when the test mode setting signal TE is "H" 1279979, if the test mode selection signal TEST_MODEP is "L", the gate signal forming circuit 29" fixes the P-channel gate signal CNNT to "H" and sets N The pass gate signal is output in synchronization with the wafer select signal; thereby, Vout can be generally ramped up by section as shown in FIG. In this embodiment, although the test mode setting terminal TEST_MODE is externally set, the test mode is entered when the potential of the test mode setting terminal TEST_MODE rises to "H", but special serial data can be input to SDATAI. In response to this, the control unit 10 sets TE to "H" internally: In this way, the terminals of the LSI can be reduced. In addition, when the electronic volume device is mounted, the test mode setting terminal TEST-MODE is grounded (fixed to "L") in use. In the above description, for the sake of simplification of description, the analog sound circuit is described as a one-channel electronic volume device, but the present invention is also applicable to an electronic volume device in which an analog circuit of a plurality of channels is built. In this case, as shown in FIG. 10, the analog circuits 9-1 to n of the complex channels are individually provided to the analog test circuits 20-1 to η so that the outputs ATEST1 to η of the various types of ratio test circuits are in the encoder. 40 is integrated into one signal ATEST, and then output to the selector 19: in the test mode, if the analog test circuit 20 is to output "H" when Vout normally drops or rises, the encoder 40 is set to an AND circuit. So that it outputs "H" only when all the analog test circuits 20 output "H"; in the test mode, if the analog test circuit 20 is to output "1" when Vout changes normally, the encoder 40 is set to The OR circuit (AND circuit of low potential operation) causes it to output "L" only when all analog test circuits output "L". In addition, the encoder 40 can be switched between the AND circuit and the OR circuit according to the TEST-MODEP signal, that is, 1279979. In the above embodiment, although the analog test circuit 2 is built into the electric volume device 1, The analog test circuit 20 can also be set separately from the electronic volume device. As described above, according to the present embodiment, since the comparison result signal ATEST ' g of the analog test circuit 2 is output by the SDATAO terminal for outputting the serial data [this can save the required number of terminals.
此外’在此實施万式中，由於係將類比測試電路内建於 私子曰I裝置《内’並對音量設定前後的電壓進行比較: 因此能夠實現穩^、迅速、且誤差小的測試。料， 行對音量Μ的其他幾個點進行ν_的絕對值的測定，= 可進一步提高測試精確度。 游 里施以複數 依上述之本發明，將可有效率地對能夠對音 段控制的電子音量裝置進行測試。 [圖式簡單說明] 圖1為本發明之實施方式之電子 圖2為採用上述電子音 《區塊圖。 ㈣上音頻放大器之區塊圖。 心子音量裝置之類比測試電路之區塊圖。 、于曰里裝置《類比測試電路之區換 圖5為上述雷子立香# $ 尾圖。 子曰夏奴置與邏輯測試器之 圖6(A)(B)為t田 運接万式又圖 之圖 圖“子骨量裝置在進行測試時之各部二 圖 圖 π〜π a电峪之其他例子之圖。 )為以關_試電路進行測簡之各部信號之 -20- 1279979 圖。 圖9為類比測試電路之另外其他例子之圖。 圖10為多聲道電子音量裝置之類比測試電路之連接方式 之圖。 圖11(A)至（C)為一般電子音量裝置内部構造之圖。 圖12(A)(B)為以往之電子音量裝置之測試之說明圖。 [圖式代表符號說明] 1 電子音量裝置 2 輸入緩衝器 3 功率放大器 4 喻J 口八 5 微電腦 6 旋轉編碼器 7 顯示部 8 邏輯測試器 8a 探測信號驅動器 8b 比較器 9 類比電路 10 控制部 11、12 可變電阻 13 放大器 14 解碼器 15 零點觸發檢測電路 16 振盪器In addition, in the implementation of this type, since the analog test circuit is built in the "inside" of the device and the voltages before and after the volume setting are compared: Therefore, it is possible to achieve a stable, rapid, and small error test. Material, the line determines the absolute value of ν_ for several other points of the volume ,, = can further improve the test accuracy. Applying the plural in the game According to the present invention described above, the electronic volume device capable of controlling the segment can be efficiently tested. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is an electron according to an embodiment of the present invention. Fig. 2 is a block diagram using the above electronic sound. (4) Block diagram of the upper audio amplifier. A block diagram of the analog test circuit, such as the heart volume device. In the Yuli device, the area of the analog test circuit is changed. Figure 5 shows the above-mentioned Leizi Lixiang # $ tail image. Fig. 6(A)(B) of the sub-Xia Nuo and logic tester is a diagram of the t-field transport and the diagram of the figure. “The sub-bone device is in the second part of the test. π~π a Figure -20-1279979 of the various signals for the calibration of the test circuit. Figure 9 is a diagram of another example of the analog test circuit. Figure 10 is an analogy of the multi-channel electronic volume device. Figure 11 (A) to (C) are diagrams showing the internal structure of a general electronic volume device. Figure 12 (A) (B) is an explanatory diagram of a test of a conventional electronic volume device. Representative symbol description] 1 Electronic volume device 2 Input buffer 3 Power amplifier 4 Yu J port 8 5 Microcomputer 6 Rotary encoder 7 Display unit 8 Logic tester 8a Detection signal driver 8b Comparator 9 Analog circuit 10 Control unit 11, 12 Variable Resistor 13 Amplifier 14 Decoder 15 Zero Trigger Detection Circuit 16 Oscillator
-21 - 1279979-21 - 1279979
17 解碼器 18 S/P轉換器 19 選擇器 20 類比測試電路 29 ^ 29’、29’’閘極信號形成電路 30、 30’、30"斬波型比較器 31 轉換器 32 P通路MOS電晶體 32f N通路MOS電晶體 33 電容器 34 轉換器 35 緩衝器 40 編碼器17 Decoder 18 S/P Converter 19 Selector 20 Analog Test Circuit 29^29', 29'' Gate Signal Forming Circuit 30, 30', 30" Chopper Type Comparator 31 Converter 32 P-Channel MOS Transistor 32f N-channel MOS transistor 33 capacitor 34 converter 35 buffer 40 encoder
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