200405656 玖、發明說明： [發明所屬之技術領域] 本發明係關於一種電子音量裝置及該電子音量的剛試方 法’能夠提高出廠測試的效率。 [先前技術] 半導體元件的電子音量裝置已經普遍地做為類比音頻^ 號的音量調整用元件而受到使用。如圖11所示，電子立及 裝置為内建有類比電路的類比LSI ;該類比電路係白今m ^ 、 ^ ^具有 複數個分接頭的可變電阻及放大器等，且該可變電阻係依 为接頭#號（音量設定值）來連接複數個分接頭中的其中_ 個。近年來的電子音量裝置的分接頭的分段數增加許多， 256段的分接頭也已經相當常見。 孩電子音量裝置在製造時會接受出廠測試，而該出廠測 試中包含確保上述可變電阻的所有分接頭沒有短路等且正 常連接等測試。在該測試中，係如圖12( A)所示般地將邏輯 測試器連接於電子音量裝置LSI上，將一定之直流電壓（ν^) 輸入電子晋量裝置，藉由切換音量設定值來依序連接所有 等分接頭，依各音量設定值，以直流電壓測定電路來測定 有典對應於該音量設定值之正常等類比電壓v〇ut輸出。 [發明内容] 惟’對應於每一段的音量設定值之輸出電壓v〇ut的變化 里僅為數mV左右，為了能夠正確地加以測定，必須待輸出 電壓穩定後以高精確度的電壓測定電路進行測定，因此不 僅需對測定器的精確度進行要求，且如圖12(b)所示一般， 每一段的測定需費時數咖至數十㈣的時間。為此，在採用 200405656 可實施256段的音量設定值控制的電子音量裝置時，為了對 每—段進行測試’不僅需時冰至數秒，且如為音響用或多 W用的電子音量裝„ ’會發生所需的測試時間會隨該 聲迢的數目而增加的問題。 +有鑑於此，本發明之目的在於提供一種電子音量裝置及 電子音量測試方法，以解決上述課題，並提高電子音量裝 置在出廠時的測試效率。 申請專利範圍第1項之發明的特徵為包含：類比電路，立 係依複數段的音量設定值，部輸入之類比信號的信號 電平進行控制後，冑出為輸出信號；控制部，其係將外部 指示的音量設定值輸入至上述類比電路；測試電路，其係 在上述輸出信號輸人而有音量設定值輸人至類比電路時， 在對該音量設定值輸人前後的上述輸出信號的信號電平大 小進行比較後，將比較結果以雙值的電壓值來輸出。 申請專利範圍第2項之發明的特徵為包含：複數個聲道份 的類比電m依複數段的音量設定值，對外部輸入之 類比信號的信號電平進行控制後，輸出為輸出信號；控制 邵，其係將外部指示的各聲道之音量設定值輸入至對應聲 迢的上述類比電路；測試電路’其係對應於各聲道而設， 且在上述輸出信號輸入而有音量設定值輸入至類比電路 時’在對該音量設定值輸人前後的上述輸幻线的信號電 平，小進行比較後，輸出比較結果；及解碼電$,其係以 各聲道的比較結果進行邏輯積或邏輯和運算，並將運赏的 結果以雙值的電壓值來輸出。 # 200405656 申請專利範圍第3項之發明的特徵為上述測試電路係以 斬波型比較器來對上述輸出信號的信號電平大小進行比 較0 申請專利範圍第4項之發明的特徵為一面對第丨、2、或3 項，電子音量裝置輸入指定電壓的直流信號做為上述類比 仏唬，一面每次碉降或調升一段來依序輸入音量設定值， 並監視對應於此而輸出的上述雙值電壓值，藉以判斷上述 電子音量裝置的良否。 二：晋量裝置的測試方面，如上所述，係隨著輸入具有 2疋兒壓〈直流信號做為類比信？虎，依序輸入複數段的音 ::疋值後，監視類比電路有無輸出相對應之直流信號： :明係，建有測試電路，用以#有音量設定值由外部輸 ^ a *该首！設足值來檢測類比電路的幸命出電壓有盔正 吊^匕，並藉由輸出該檢測結果來提高該測試的效率^ 一般在出廠測試中，音香&今# ^ ,曰 田 I叹疋值係由取大值逐段下降至 取小值，或由最小值逐段升古 1山十， 又升同至瑕大值，使類比電路薪麻 於此來輸出電壓。因此，户女政。丄 兒々對應 /古於X二 在本發明中設有能夠對音量設定 值輸入珂後的類比電路 — ^ ? 7翰出电壓進行比較後輸出該比畤 結不的測試電路，以針對立旦Μ * — 〜比丁乂 相較於之义& f f Θ里卩又疋值之母一段的輸出電壓 ^ Τ乂 Κ 4月丨J的電壓為下隆 土 類比電跋觫 二升，輸出比較結果··例如， ，為合咕认 受比先則的電壓為低時輸出L ( = 〇 v) 為呵時輸出H(=5V)即可。 1 U V) 藉此，用以對該電子立旦 面’由於可夢由的項μ、曰，里裝置進行測試的測試裝置方 θ ^?述測試電路所輸出的雙值的電壓值 200405656 也可大幅縮 來進行測試，所以不僅可使用簡略的比較器 短測定時間。 此外，上述測試電路中已内建有電子音量裝置AW)，由 於配線所產生的浮游電容及電阻極小，因此輸出電壓能夠 迅速穩足且其精確度高。此夕卜，由於並非測定出電壓的絕 對值，而係以先前的電壓與本次的電壓做比較，因此可簡 化電路的構造。 再者，測試電路的輸出係為類比電路的動作正常與否的 判足結果，因此即使測試對象為複數個聲道的電子音量裝 置，也旎夠同時對所有聲道進行測試：即，測試對象為複 數聋道的笔子晋量裝置時，如有任一聲道無法正常動作， 該電子音量裝置便屬不良，因此對所有聲道的判定結果進 行邏輯積運异（惟’比較結果的輸出係設定為正常=L時，依 電性在此則改採邏輯和運算），使得複數個聲道中任一聲道 不良時的輸出會反轉，便可一次對複數個聲道進行測試。 [貫施方式] 以下將參照圖式，說明本發明之實施方式之電子音量裝 置（電子晋量LSI)及其測試方法。 圖2為採用了相同之電子音量裝置（LSI) 1的音訊放大器 之概略區塊圖。由CD唱盤及調諧器等之位於前段的電路所 輸入的類比音頻信號係介以緩衝器2而輸入至電子音量裝 置1的Vin端子。此外，緩衝器2為用以轉換阻抗的類比緩衝 放大器，在此並非必要者。電子音量裝置1具有如圖丨所示 的構造’可藉由控制可變電阻丨丨及12，使得上述類比音頻 200405656 信號的信號電平受到調整後由v。，子輸出。電子立量裝 置1輸出的類比晋頻信號在、經由 3 喇，八4播放。 +攻大备3的放大後，由 電子音量裝置Η系連接有控制用的微電心微 輸出音量控制資料，該資料佴 此夠 、行係用以對電子音量裝置進 比音頻信號的信號電平進行批制 、、、 ^ 仃&制。孩骨量控制資料係在雷 子音量裝置1内解碼為分接頭選擇信號後，輸入至可變電阻 11 及 12。 當音訊放大器的使用者操作旋轉編碼器6時，對應於該操 作的脈衝信號會輸入微電腦5;微電腦5會依該操作量來變 更音量設足值；當晋量設定值變更時，該設定值會顯示於 顯示部7’同時會產生對料該音量設定值的音量控制資 料；微電腦5會以音量控制資料做為串行資料sdatai，與序 列時脈信號SCLK同步地輸人電子音量裝置1;電子音量裝置 1在有序列信號輸入時1電子音量裝置丄的晶片選擇信號 CSN (有功低位# ; active Low)設定為“L”，而使串行資料的 輸入致能；接著，電子音量裝置丨在_行資料輸入之後，將 晶片選擇信號CSN設定為“H”時，電子音量裝置丨會在信號升 起時對串行資科進行問鎖，並依該資料（音量控制資料）來 對類比音頻信號的信號電平進行控制。如此一來，對應於 使用者設定的音量設定值而產生的音量控制資料及上^分 接頭選擇信號會對應於本申請專利範圍各項的音量設定 值。 該電子音量裝 圖1為上述電子音量裝置1的内部區塊圖。 200405656 置包含·可’交電阻11及12、具有放大器丨3的類比電路9、控 制部10、解碼器14、零點觸發檢測電路15、振盪器16、解碼 器17、及S/P轉換電路18，且尚包含用以對上述類比電路9 進行測試的選擇器19及類比測試電路2〇。此外，外部輸出 入端子方面，則包含··類比信號輸入端子vin、類比信號輸 出端子Vout、串行資料輸出端子SData〇、晶片選擇信號輸 入端子CSN、序列時脈輸人端子S(：LK、串行資料輸入端子 SDATAI、令點觸發衩制端子沈咖及沈㈣、測試模式設定 ㈤子TEST—MODE。此外，如以從之說明，纟端子的記號係 以表示各端子所輸出入的信號之記號來表示。 類比音頻信號係由類卜彳含 • v匕4 5虎丁則入^子Vin輸入；該類比音 頻信號係供應至可變兩伽， 包阻11及夺點觸發檢測電路。可變電 阻11及12方面，藉由兩去 即巿者間的組合可提供256段的分接頭， 且能夠使藉由分接頭遝指1二 、必 、 、、擇k唬TS1及丁S2所選擇的任一組分 接頭連接於放大器13 .获士 //U、、 、、， ·精由仗孩選取的分接頭取出上述輸 入之類比音頻信號後， 曰 ^ 知孩頰比晋頻信號輸入放大器13 〇 即，精由選取之分接頭 旦十^ i 、力位置，可碉整類比音頻信號的衰 減！或放大量。該分接 ^ ^ 丟〜選擇仏唬TS1及TS2係上述微電腦5 •所輸入足8位元音量扣 去益山、、 I抆制資料經由解碼器14的解碼而成 者。猎由该8位兀的音量# 圍肉， 、 里拴市J貝枓，旎夠在a至+32 dB的範 国内對輸入芡類比音箱产％ μ ^上 制 Λ、仏號的信號電平施以256段的控 上述微電腦5所輸Λ S/P (串行/平行）轉換部 的音量控制資料（串行資料）方面，當 18串晶片選擇端子CSN為“L”時，將讀 -10- 200405656 入做為與串行時脈SCLK同步地由串行資料輸入端子 SDATAm入的資料。尚且，當晶片選擇端子csn為“ h，，時， 讀入的資料將受到問鎖而傳送至控制部1〇。 控制部10中，S/P轉換部18值#亦A人上 丨U傳运來的首量控制資料將做為 分接頭選擇信f虎，經由解碼器14, ％對可變電阻M12進行 設足’惟在設定成不實施藉由零點觸發控制信號z咖及 ZCEN2的組合所進行的零點觸發控制時，則設定成使^轉 換部18傳送來的音量控制資料立即輸出至解碼器⑷麦，解 碼器14依分接頭選擇選擇信號TS1及TS2來設定可變電阻工丄 及12。另一方面，如設定成藉由零點觸發控制信號ζ(：ενι 及ZCEN2的組合進行的零點觸發控制時，係設定成在使s/p 轉換部18傳送來的音量控制資料在下_個緊接的零點觸發 時序時輸出至解碼器14，將分接頭選擇信號TS1及ts2設定 於可變電阻11及12。在此，零點觸發時序係指在振幅擴及+ 側及一側之兩侧的輸入類比信號在通過〇 V時之時序，由於 使音量在該時序時變化也不致於使振幅波形不連續，因此 不k產生减訊。為此，重視首質時，分接頭選擇信號TS i 及TS2係等待至此一時序時輸出。 令點觸發檢測電路15係對輸入類比信號與GND電壓位準 (0 v)進行比較以檢測出零點觸發時序（類比信號通過〇 Vi 時序）後通知控制部10之電路。此外，振盪器16係藉由控制 邵10而做為計時器來使用。亦即，如欲實施音量的零點觸 發控制時，音量控制資料在輸入後會等待零點觸發檢測電 路15輸入零點觸發檢測信號為止，惟等待時間超過指定時 200405656 間後，如仍無零點檢測信號輸入時（例如DC偏移的小信號 等）’當計時器的計時超過上述指定時間時，即使不在零點 觸發時序，也施以音量控制。 此外’ SDATAO為用以輸出S/P轉換部〗8所儲存的設定資料 (上次輸入的資料）的端子。s/p轉換部18具有轉換暫存器， 用以緩衝由SDATAI輸入之串行資料，且介以SDATA〇依序將 - 先輸入的位元加以輸出。也可在該SDATA〇端子上以離菊鏈 連接方式連接其他同種的電子音量裝置SDATAI端子後，藉 由圖2之微電腦5將複數個電子音量LSI份的音量控制資料 鲁 加以串行輸出，對所有的電子音量LSI設定音量控制資料， 而貫現多聲道控制。 如上所述，輸入之類比信號係藉由介以_行資料輸入端 子SDATAI由外邵輸入之音量控制資料，而受具有可變電阻 11及12以及放大器π的類比電路進行音量控制，惟該電子音 量裝置内建有類比測試電路20及選擇器19，用以測試該類 比電路（在此為可變電阻丨丨及丨幻動作正常與否。當控制部ι〇 將測4模式h號TE輸出至類比測試電路20及選擇器19時 鲁 (測試模式設定端子TEST—MODE設為‘Ή，，時），實施測試模式 — 動作。 _ 圖3及圖4為上述類比測試電路2〇之電路構造圖；圖$為電 子音量裝置出廠測試時之連線形態之圖；圖6為測試時之各 邵信號之圖。 圖5中，出廠測試時，電子音量裝置丨上連接有邏輯測試 器8。邏輯測試器8包含··探測信號驅動器（ping dHver)〜， -12 · 200405656 其用以產生各種信號；及比較器8b，其用以判定輸入之電 壓係高於或低於指定之臨限值。探測信號驅動器8a連接於 Vin、CSN、SCLK、SDATAI、TEST_M〇DE。探測信號驅動器 8a係將TEST_M〇DE設定成能夠使控制部10在開始進行測試 時，將TE(用以指定測試模式之内部信號）設定為“H”，且將 TES丁一MODE設定成能夠使控制部10在測試結束時，將丁Ξ設 定為“L” ；此外，當有指定的直流電壓（Vin)產生而輸入Vin 端子時，將音量控制資料SDATAI與晶片選擇信號CSN及串 行時脈信號SCLK同步地輸出。SDATAI係在每當有晶片選擇 信號CSN時，每次調降音量設定值一段。測試可對可變電阻 11及可變電阻分開來實施：在對可變電阻11進行測試時， 乃使可變電阻12的分接頭選擇信號TS2固定（固定成增益為 最大）後，藉由一段一段地調降可變電阻11之用以控制衰減 的分接頭選擇信號TS1，將音量控制資料輸入SDATAI ;在對 可變電阻12進行測試時，乃使可變電阻11的分接頭選擇信 號丁S1固定（固定成增益為最小）後，藉由一段一段地調降可 變電阻12之用以控制衰減的分接頭選擇信號TS2，將音量控 制資料輸入SDATAI。 對應於上述般的音量控制資料，電子音量裝置會如圖6(A) 所示一般，所輸出的輸出電壓Vout會相對於輸入電壓Vin — 段一段地逐段下降。惟，邏輯測試器8並非以上述Vout做為 觀察對象，而係藉由比較器8b對介以SDATAO輸出之類比測 試電路20之比較結果信號ATEST的“H/L”進行觀察。類比測 試電路20係如後所述般地在晶片選擇信號CSN由“L”上升至 200405656 “Η”時，即有新的音量控制資料輸入時，對類比電路之前後 的輸出電壓Vout進行比較，當目前的電壓比先前的電堡為 低時，輸出“L”做為ATEST，當輸出電壓Vout未下降時，貝|J 輸出“Η”做為ATEST。 邏輯測試器8之比較器8b能夠藉由判定該SDATAO為 或“L”，判定電子音量裝置有無正常動作，由於無需正確測 定出數mV的電壓，因此能夠在極短的時間（數百ns至數ps) 内，判定出一段的音量變化為正常或異常。 圖3中，電子音量裝置1内建的類比測試電路20具有由轉 換器31、P通路MOS電晶體32、及電容器33所構成之所謂的 斬波型比較電路30。即，轉換器31與P通路MOS電晶體32並 聯連接，當P通路MOS電晶體32上有閘極信號（一的閘極電壓） 輸入而成為開時，轉換器31的輸入側與輸出侧會短路。接 著，有放大器13之輸出的Vout介以電容器33((^)而供應至轉 換器31的輸入側上。尚且，在轉換器3 1的輸入側配線圖案 與P通路MOS電晶體32之閘極側的配線圖案之間，產生有較 小的寄生電容（連接電容）Cs。上述電容器33的電容C!係設 定成寄生電容Cs的數倍以上。 閘極信號形成電路29在有來自控制部10之測試模式設定 信號TE輸入時會致能，而與晶片選擇信號CSN之輸入同步 地輸出P通路閘極信號CNTP。 上述斬波型比較電路30中，當P通路閘極信號CN丁P為“L” 時，P通路MOS電晶體32會成為開而使轉換器3 1的輸入側與 輸出側短路。在此時，轉換器31的輸入端子的電位在由低 -14 - 200405656 阻抗的輸出端子的電位所吸收後，輸入側及輸出側的電位 均會在轉換器31的臨限值Vtj|定下來。此時，當值為Vo! 之電壓輸入做為電壓Vout時，電容器33的電極間的電位差會 成為Vo^Vt!，而使該電位差份的電荷儲存於電容器33。由 於P通路閘極信號CNTP係與晶片選擇信號CSN同步地輸 出，因此音量控制資料會在轉換器3 1短路時輸入（晶片選擇 信號CSN為“L”之區段中，SDATAI會輸入）。 隨後，晶片選擇信號CSN升起時，類比電路的輸出Vout 會依輸入的音量控制資料而變化成Vo2，同時P通路閘極信 號CNTP會成為“H”且P通路MOS電晶體32成為關，使得該變 化之Vout=V〇2出現在電容器33的輸入側的電極上。此時，電 容器33具有之電位差為如上述之VorVt!，因此電容器33的轉 換器31側上會出現Vo2-( Voi-VtD的電位；即，出現僅由轉換 器3 1的臨限值VU相差Vo^Voi電位。若係依（由上述邏輯測試 器8輸入之）音量控制資料之控制而調降V〇Ut—段時，V02-V0! 會為負值，而轉換器31會對應於此而輸出“H” ；另一方面， Vo2-V〇1會為正值時，轉換器31會輸出“L”。因此，藉由將該 斬波型比較器30的輸出電壓做為ATEST信號而由SDATAO輸 出，能夠對類比電路之輸出電壓Vout在音量控制資料產生 一段變化時之相對應變化，以“H/L”的雙值來加以輸出。 此夕卜，如V〇2及Vo!具有相同電位而使Vc^-VofO時，由於 不確定轉換器3 1的輸出電壓，“H/L”兩者均能輸出，因此分 接頭短路等情況中的CSN前後的電壓相同時，當時的判定結 果的可靠性會下降。為此，該斬波型比較器30中，乃積極 200405656 .地利用上述寄生電扣’使得p通路Μ 寄生電容Cs的電荷量之泰壓兒日日姐32為關時之 6(A)所亍夕僬w , 、和换备31，而屋生如圖 ()所不之偏置。精此，轉換器31的 口 側偏置，僅在V〇2-V〇i產生正 "彡又上係向“L” 輸出“H，，。 1屋生正吊的電壓變化時’使轉換器31 此外’轉換器34係一種電路，並 限值輸出而進行轉換，並且…^配合比較器㈣ ^ώ^ ' 、為此夠防止將斬波型比較器的200405656 (1) Description of the invention: [Technical field to which the invention belongs] The present invention relates to an electronic volume device and a test method for the electronic volume ', which can improve the efficiency of factory testing. [Prior Art] Electronic volume devices of semiconductor elements have been generally used as analog volume adjustment elements. As shown in FIG. 11, the electronic stand-alone device is an analog LSI with an analog circuit built in; the analog circuit is Bai Jin m ^, ^ ^ a variable resistor and an amplifier with a plurality of taps, and the variable resistor system Connect _ of the multiple taps according to the connector # number (volume setting value). In recent years, the number of segments of the taps of electronic volume devices has increased a lot, and 256-segment taps have become quite common. When the electronic volume device is manufactured, it undergoes the factory test, and this factory test includes tests to ensure that all taps of the variable resistor are not short-circuited and connected properly. In this test, a logic tester is connected to an electronic volume device LSI as shown in FIG. 12 (A), and a certain DC voltage (ν ^) is input to the electronic volume device, and the volume setting value is switched by Connect all equal taps in sequence, and according to each volume setting value, use a DC voltage measurement circuit to measure the normal analog voltage vout that corresponds to the volume setting value. [Disclosure of the Invention] The change in the output voltage v0ut corresponding to the volume setting value of each stage is only a few mV. In order to accurately measure it, it is necessary to perform the measurement with a highly accurate voltage measurement circuit after the output voltage is stabilized. For the measurement, not only the accuracy of the measuring device is required, but as shown in FIG. 12 (b), the measurement of each segment takes several hours to several tens of millimeters. For this reason, when using an electronic volume device that can implement a volume setpoint control of 256 segments in 200405656, in order to test each segment, not only it takes time to freeze to a few seconds, but also an electronic volume device for audio or multi-watts. 'There will be a problem that the required test time will increase with the number of sounds. + In view of this, the object of the present invention is to provide an electronic volume device and an electronic volume test method to solve the above problems and improve the electronic volume The test efficiency of the device when it leaves the factory. The invention of item 1 of the scope of patent application is characterized by including: an analog circuit, which is based on the volume setting value of a plurality of segments, and the signal level of the analog signal input by the external control is An output signal; a control unit that inputs an externally-indicated volume setting value to the analog circuit; a test circuit that is configured to input a volume setting value to the analog circuit when the output signal is input to the analog circuit After the signal levels of the above-mentioned output signals before and after the input are compared, the comparison result is output as a double-valued voltage value. The invention of the second item of the scope is characterized in that: the analogue electric m of the plurality of channel parts is controlled by the volume setting value of the plurality of segments, and the output signal is output after controlling the signal level of the externally input analog signal; It is to input the volume setting value of each channel indicated externally to the aforementioned analog circuit corresponding to the sound; the test circuit 'is designed to correspond to each channel, and there is a volume setting value input to the analog in the above output signal input At the time of the circuit, the signal level of the above-mentioned magic line before and after the input of the volume setting value is compared, and the comparison result is output; and the decoded electric value is a logical product or logic based on the comparison result of each channel. And 2004, and the result of the reward is output as a double-valued voltage. # 200405656 The third invention of the scope of patent application is characterized in that the test circuit uses a chopper-type comparator to compare the signal level of the output signal. Compare the size 0 The invention of item 4 of the scope of patent application is characterized by facing the item 丨, 2, or 3, and the electronic volume device inputs a DC signal of a specified voltage as the above analogy Frighten, while lowering or increasing one segment at a time, input the volume setting value in sequence, and monitor the above-mentioned two-valued voltage value corresponding to this, so as to judge the goodness of the electronic volume device. In terms of the aspect, as mentioned above, with the input having a DC voltage of 2 〈DC signal as an analog signal? Tiger, after inputting the complex number of sounds in sequence :: 疋 values, monitor the analog circuit to output the corresponding DC signal:: Ming Department, built a test circuit to # have a volume set value input from the outside ^ a * the first! Set a sufficient value to detect the analog circuit circuit fortunately the voltage has a helmet hanging dagger, and by outputting the detection result To improve the efficiency of the test ^ Generally, in the factory test, the sound of the fragrant sound & present # ^, the field I sigh value is decreased from the large value to the small value, or from the minimum value to the ancient mountain. Tenth, the same value is raised to the maximum value, so that the analog circuit can output a voltage here. Therefore, the household daughter.丄 儿 々 correspondence / ancient X X. In the present invention, an analog circuit capable of inputting a volume setting value to Ke is provided. A test circuit that outputs the ratio after comparing the output voltage is used for Lidan. Μ * — ~ The output voltage of 比 乂 于 compared to the meaning of & ff Θ Θ 卩 卩 卩 卩 卩 ^ ^ 乂 乂 乂 丨 The voltage in April 丨 J is two liters of the electric analog of the Halong soil, the output comparison Result ... For example, it is sufficient to output L (= OV) when the voltage of the receiver is lower than the previous one, and output H (= 5V) when the voltage is low. 1 UV) With this, the test device used to test the electronic surface "because of the dream item μ," said the double voltage value 200405656 output by the test circuit may also be The test is greatly reduced, so not only the measurement time can be shortened by using a simple comparator. In addition, the above-mentioned test circuit has an electronic volume device (AW) built in. Because the floating capacitance and resistance generated by the wiring are extremely small, the output voltage can be quickly and sufficiently stable with high accuracy. In addition, since the absolute value of the voltage is not measured, the previous voltage is compared with the current voltage, so the circuit structure can be simplified. In addition, the output of the test circuit is the result of determining whether the analog circuit operates normally. Therefore, even if the test object is an electronic volume device with multiple channels, it is not enough to test all channels at the same time: that is, the test object. When the pen volume measuring device for plural deaf channels does not operate normally on any of the channels, the electronic volume device is defective. Therefore, the judgment results of all channels are logically different (except for the output of the comparison result). When the system is set to normal = L, logic and operation are used here depending on the electrical properties), so that when any one of the multiple channels is defective, the output will be reversed, and the multiple channels can be tested at one time. [Performance Mode] An electronic volume device (electronic gain LSI) and a test method thereof according to an embodiment of the present invention will be described below with reference to the drawings. Fig. 2 is a schematic block diagram of an audio amplifier using the same electronic volume device (LSI) 1. An analog audio signal inputted from a circuit located in the front stage, such as a CD player and a tuner, is input to the Vin terminal of the electronic volume device 1 via the buffer 2. In addition, the buffer 2 is an analog buffer amplifier for converting impedance, and it is not necessary here. The electronic volume device 1 has a structure as shown in FIG. 丨. By controlling the variable resistors and 12, the signal level of the above-mentioned analog audio 200405656 signal is adjusted by v. , Child output. The analog frequency signal output by the electronic constant volume device 1 is played at 3, 8 and 4. + After the amplification of Dabei 3, the electronic volume device is connected with the micro-controller's micro-output volume control data for control. This data is sufficient and the line is used to input the electronic volume device to the audio signal signal. Flat batch ,,, ^ 仃 & system. The bone weight control data is decoded into the tap selection signal in the lightning volume device 1 and input to the variable resistors 11 and 12. When the user of the audio amplifier operates the rotary encoder 6, the pulse signal corresponding to the operation will be input to the microcomputer 5; the microcomputer 5 will change the volume setting value according to the operation amount; when the setting value of the volume is changed, the setting value Will be displayed on the display 7 'while generating volume control data for the volume setting value; the microcomputer 5 will use the volume control data as serial data sdatai, synchronized with the serial clock signal SCLK input to the electronic volume device 1; When the electronic volume device 1 has a serial signal input, the chip selection signal CSN (active low #; active Low) of the electronic volume device 1 is set to "L" to enable the input of serial data; then, the electronic volume device 丨After the input of the _ line data, when the chip selection signal CSN is set to “H”, the electronic volume device 丨 will lock the serial assets when the signal rises, and use the data (volume control data) to compare the analog The signal level of the audio signal is controlled. In this way, the volume control data and the upper tap selection signal generated corresponding to the volume setting value set by the user will correspond to the volume setting values of the items in the scope of this patent. This electronic volume device FIG. 1 is an internal block diagram of the electronic volume device 1 described above. 200405656 includes: AC resistor 11 and 12, analog circuit 9 with amplifier, 3, control unit 10, decoder 14, zero trigger detection circuit 15, oscillator 16, decoder 17, and S / P conversion circuit 18 It also includes a selector 19 and an analog test circuit 20 for testing the analog circuit 9 described above. In addition, the external input and output terminals include: analog signal input terminal vin, analog signal output terminal Vout, serial data output terminal SData〇, chip selection signal input terminal CSN, serial clock input terminal S (: LK, Serial data input terminal SDATAI, order point trigger control terminal Shenka and Shenyang, test mode setting ㈤ TEST_MODE. In addition, as explained from this, the symbol of 纟 terminal is used to indicate the signal output by each terminal The analog audio signal is input by analogy, including: • v d 4 4 5 hu Ding is input to the child Vin; this analog audio signal is supplied to a variable two-gamma, including 11 and capture point trigger detection circuit. In terms of variable resistors 11 and 12, a 256-segment tap can be provided through a combination of two to go, and the tap can be used to select TS1 and D2. The connector of any component selected is connected to the amplifier 13. 获 // U ,, ,,, · After the analog audio signal of the above input is taken out by the tap selected by Zhanyi, it will be referred to as the frequency signal input. Amplifier 13 〇 That is, fine The selected taps can be used to adjust the attenuation of the analog audio signal or the amount of amplification! This tap ^ ^ is lost ~ Select TS1 and TS2 to be the above microcomputers 5 • Input 8 bits The volume is deducted from Yishan, and the I-manufactured data is decoded by the decoder 14. Hunting for the 8-bit Wu's volume # ， 肉,, Lishui City J Bei 枓, enough to range from a to +32 dB Domestically, the input signal level of the analog 音箱 analogue speakers is% ^. The signal levels of the Λ and 仏 signals are controlled by 256 segments of the volume control data of the Λ S / P (serial / parallel) conversion section of the microcomputer 5 (serial In terms of data), when the 18-string chip selection terminal CSN is "L", read -10- 200405656 will be used as the data input by the serial data input terminal SDATAm in synchronization with the serial clock SCLK. Also, when the chip is selected When the terminal csn is "h,", the read-in data will be interlocked and transmitted to the control unit 10. In the control unit 10, the S / P conversion unit 18 value # is also the first amount transmitted by the person. The control data will be used as a tap to select the signal, and the variable resistor M12 will be set via the decoder 14.%. When the zero-point trigger control by the combination of the zero-point trigger control signal zca and ZCEN2 is not implemented, it is set to make the volume control data sent by the ^ conversion section 18 be output to the decoder mai immediately, and the decoder 14 according to the tap Select the selection signals TS1 and TS2 to set the variable resistor operation and 12. On the other hand, if it is set to zero trigger control by the combination of the zero trigger control signal ζ (: ενι and ZCEN2, it is set to make s The volume control data transmitted by the / p conversion section 18 is output to the decoder 14 at the next next zero trigger timing, and the tap selection signals TS1 and ts2 are set to the variable resistors 11 and 12. Here, the zero-trigger timing refers to the timing when the input analog signal whose amplitude is extended to both the + side and one side passes through 0V. Since the volume is changed at this timing, the amplitude waveform is not discontinuous, so Does not produce mitigation. Therefore, when the first quality is valued, the tap selection signals TS i and TS2 are output while waiting for this timing. The command point trigger detection circuit 15 is a circuit that notifies the control section 10 after comparing the input analog signal with the GND voltage level (0 v) to detect the zero trigger timing (the analog signal passes through the 0 Vi timing). In addition, the oscillator 16 is used as a timer by controlling Shao 10. That is, if the zero-point trigger control of the volume is to be implemented, the volume control data will wait for the zero-trigger detection circuit 15 to input the zero-trigger detection signal after inputting, but after the waiting time exceeds 200405656 times, if there is still no zero-trigger signal input Time (such as small signal of DC offset, etc.) 'When the timer counts above the specified time, the volume control is applied even if the timing is not triggered at zero. In addition, 'SDATAO' is a terminal for outputting the setting data (the data input last time) stored in the S / P conversion section. The s / p conversion section 18 has a conversion register for buffering the serial data input by the SDATAI, and sequentially outputs the-input bits through SDATA0. It is also possible to connect other SDATAI terminals of the same type of electronic volume device to the SDATA0 terminal in a daisy chain connection mode, and then use the microcomputer 5 in FIG. 2 to serially output the volume control data of a plurality of electronic volume LSI components, All electronic volume LSIs set volume control data, and now implement multi-channel control. As mentioned above, the input analog signal is the volume control data inputted by the Shao through the data input terminal SDATAI, and is controlled by the analog circuit with variable resistors 11 and 12 and the amplifier π, but the electronic volume An analog test circuit 20 and a selector 19 are built in the device to test the analog circuit (here, the variable resistors 丨 and 丨 the magic action is normal or not. When the control section ι〇 outputs the TE number 4 in the test mode h to Analog test circuit 20 and selector 19 (Test mode setting terminal TEST_MODE is set to 'Ή ,,), implement test mode-action. _ Figures 3 and 4 are circuit diagrams of the analog test circuit 20 above. ; Figure $ is the connection form of the electronic volume device during the factory test; Figure 6 is a diagram of each signal during the test. In Figure 5, during the factory test, the electronic volume device is connected with a logic tester 8. Logic The tester 8 includes a probe signal driver (ping dHver) ~, -12 · 200405656, which is used to generate various signals; and a comparator 8b, which is used to determine whether the input voltage is above or below a specified threshold value The sounding signal driver 8a is connected to Vin, CSN, SCLK, SDATAI, and TEST_M0DE. The sounding signal driver 8a is set to TEST_M0DE so that when the control unit 10 starts the test, the TE (for specifying the internal of the test mode) (Signal) is set to "H", and TES Ding Yi Mode is set to enable the control unit 10 to set Ding Ding to "L" at the end of the test; In addition, when a specified DC voltage (Vin) is generated, input Vin When the terminal is connected, the volume control data SDATAI is output in synchronization with the chip selection signal CSN and the serial clock signal SCLK. SDATAI is used to lower the volume setting value for a period of time each time the chip selection signal CSN is present. The resistor 11 and the variable resistor are implemented separately: When the variable resistor 11 is tested, the tap selection signal TS2 of the variable resistor 12 is fixed (fixed to the maximum gain), and then can be adjusted by lowering it step by step. The tap selection signal TS1 of the variable resistor 11 for controlling attenuation is input into the volume data SDATAI; when the variable resistor 12 is tested, the tap selection signal D1 of the variable resistor 11 is made After being fixed (fixed to a minimum gain), the volume control data is input to SDATAI by adjusting the tap selection signal TS2 of the variable resistor 12 for controlling attenuation step by step. Corresponding to the above-mentioned volume control data, electronic The volume device will be as shown in Fig. 6 (A), and the output voltage Vout will decrease step by step with respect to the input voltage Vin —. However, the logic tester 8 does not use the above Vout as an observation object, but rather The comparator 8b observes the "H / L" of the comparison result signal ATEST of the analog test circuit 20 output via the SDATAO. The analog test circuit 20 compares the output voltage Vout before and after the analog circuit when the chip selection signal CSN rises from “L” to 200405656 “Η”, that is, when new volume control data is input. When the current voltage is lower than the previous power source, the output "L" is used as ATEST, and when the output voltage Vout has not fallen, the output | "J" is used as ATEST. The comparator 8b of the logic tester 8 can determine whether the SDATAO is "L" to determine whether the electronic volume device is operating normally. Because it does not need to measure the voltage of several mV, it can be used in a very short time (hundreds of ns to Within a few ps), it is determined that the volume change of a segment is normal or abnormal. In Fig. 3, the analog test circuit 20 built in the electronic volume device 1 includes a so-called chopper-type comparison circuit 30 composed of a converter 31, a P-channel MOS transistor 32, and a capacitor 33. That is, the converter 31 is connected in parallel with the P-channel MOS transistor 32. When the gate signal (a gate voltage of one) is input to the P-channel MOS transistor 32 and becomes ON, the input side and the output side of the converter 31 will Short circuit. Next, Vout having the output of the amplifier 13 is supplied to the input side of the converter 31 through a capacitor 33 ((^). Moreover, the wiring pattern on the input side of the converter 31 and the gate of the P-channel MOS transistor 32 A small parasitic capacitance (connection capacitance) Cs is generated between the wiring patterns on the side. The capacitance C! Of the capacitor 33 is set to be a multiple of the parasitic capacitance Cs or more. The test mode setting signal TE is enabled when it is input, and the P-channel gate signal CNTP is output in synchronization with the input of the chip selection signal CSN. In the above-mentioned chopper-type comparison circuit 30, when the P-channel gate signal CN but P is " When “L”, the P-channel MOS transistor 32 will be turned on and short-circuit the input side and output side of converter 31. At this time, the potential of the input terminal of converter 31 is at the output terminal with low -14-200405656 impedance. After being absorbed by the potential, the potentials on the input and output sides are set at the threshold Vtj | of the converter 31. At this time, when the voltage input with the value Vo! Is used as the voltage Vout, the voltage between the electrodes of the capacitor 33 The potential difference will become Vo ^ Vt !, so that The electric charge of this potential difference is stored in the capacitor 33. Since the P-channel gate signal CNTP is output in synchronization with the chip selection signal CSN, the volume control data will be input when the converter 31 is short-circuited (the chip selection signal CSN is "L" In the section, SDATAI will be input.) Then, when the chip selection signal CSN rises, the output Vout of the analog circuit will change to Vo2 according to the input volume control data, and the P-channel gate signal CNTP will become "H" and P The pass MOS transistor 32 is turned off so that the changed Vout = V〇2 appears on the input side electrode of the capacitor 33. At this time, the potential difference of the capacitor 33 is VorVt! As described above, so the converter 31 of the capacitor 33 The potential Vo2- (Voi-VtD) appears on the side; that is, the Vo ^ Voi potential differs only by the threshold VU of the converter 31 1. If it is based on the volume control data (input by the above-mentioned logic tester 8) V02-V0! Will be a negative value when the V〇Ut-step is controlled down, and converter 31 will output "H" corresponding to this; on the other hand, when Vo2-V〇1 is a positive value, the conversion The device 31 will output "L". Therefore, by setting The output voltage of the chopper-type comparator 30 is used as the ATEST signal and output by SDATAO. It can change the corresponding output voltage Vout of the analog circuit when there is a change in the volume control data, and use the double value of “H / L” to add it. In addition, if Vc2 and Vo! Have the same potential and Vc ^ -VofO, because the output voltage of converter 31 is uncertain, both "H / L" can be output, so the tap is shorted. When the voltages before and after the CSN in the case are the same, the reliability of the judgment result at that time will decrease. For this reason, the chopper-type comparator 30 actively uses the above-mentioned parasitic electric buckle to make the p-channel M parasitic capacitance Cs's charge voltage of the day and day sister 32 to 6 (A) when it is closed.亍 夕 僬 w,, and reserve 31, and the house is not biased as shown in (). As a result, the port-side bias of the converter 31 only generates a positive " " output to H only when V0-V0i is turned on. Converter 31 In addition, 'Converter 34 is a circuit that converts with a limited output, and ... ^ cooperates with the comparator ㈣ ^ ώ ^', which is enough to prevent the
㈣出保持在高阻抗且連接於輸域的電路所造成的影響 圖3中’雖僅連接一段的斬波型比較器3〇,當轉換器η的 增-相對於輸入之電位差(〜ν〇ι)顯得不足時，轉換哭3] 的輸出不會具有“H/L”的整個振幅，而係在線性放大區域來 ，出中間值。在此情況中’如圖4所示一般，可藉由串聯兩 故的τ斤波型比較备30，使得輸出能夠進行“H/L，，的整個振幅 而實現雙值輸出。採用如圖4所示的構造時，由於增加1個 轉換器，輸出的電壓的“H/L”會反轉，然而藉由以非反轉的 ’爰衝斋3 5來取代轉換器來做為最後一段的緩衝器，便可使 輸出的信號的極性能與圖3相同。 圖6(A)及（B)所示的八丁£訂及SDaTA〇的各信號為在如圖4 所示般地將2個斬波型比較器串聯時的波形。在該圖6(b) 中’晶片選擇信號CSN(的“L”區間）具有與串行時脈SCLK同 步之SDATAI的資料長度相當的位元長度，約數μ3左右。此 外’晶片選擇信號的間隔（CSN=“H，，的區間）則為數ps至10 w 左右。音量控制資料D則係與各晶片選擇信號同步地輸入。 該音量控制資料為如上述地每次調降音量1段的資料。邏輯 -16- 200405656 測試器8的比較器在晶片選擇信號CSN上升成“Η”後，將以數 百ns至數ps的時序來讀取SDATAO(ATEST信號），以檢測出該 電壓的“H/L”。此時，如該信號為“L”時，將判定電子音量 裝置在此段的動作屬正常；如該信號仍為“H”時，則判定該 電子音量裝置不合格。當電子音量裝置在所有階段的動作 均為正常時，則判定該電子音量裝置為合格品。 圖7及圖8為上述類比測試電路之其他實施方式之圖。在 該類比測試電路20'中，採用了 N通路MOS電晶體32’，取代 圖3及圖4所示之斬波型比較器的P通路MOS電晶體32。圖1 之類比測試電路20中，P通路MOS電晶體32的閘極配線圖案 為低電位動作者，因此寄生電容Cs會供應正電荷至轉換器 3 1的輸入端子，使得轉換器3 1的輸入電壓Va朝正侧偏置； 惟，圖7的斬波型比較器中的N通路MOS電晶體32’的閘極配 線圖案為高電位動作者，寄生電容Csf係將負電荷供應至轉 換器31的輸入端子，使轉換器31的輸入電壓Va向負側偏 置。接著，該類比測試電路的閘極信號形成電路2V會與晶 片選擇信號同步地輸出N通路閘極信號CNTN。該圖（A)所示 為該N通路型式之斬波型比較器30f僅設一段的例子；該圖 (B)所示為該N通路型式之斬波型比較器30'設有兩段的例 子。 圖8所示的為圖7(B)之内建有類比測試電路之電子音量 裝置在進行測試時之該類比測試電路及邏輯測試器之各部 份的信號：圖8(B)中，晶片選擇信號CSN的區間及晶片選擇 信號的間隔係與圖6(B)所示的情況相同。音量控制資料係 200405656 與各晶片選擇信號同步地輸入。該音量控制資料為逐次調 升音量1段的資料。邏輯測試器8的比較器在晶片選擇信號 CSN上升成“H”後，將以數百ns至數ps的時序來讀取SDATAO (ATEST信號），以檢測出該電壓的“H/L”。此時，如該信號 為“H”時，將判定電子音量裝置在此段的動作屬正常；如該 信號降至“L”時，則判定該電子音量裝置不合格。當電子音 量裝置在所有階段的動作均為正常時，則判定該電子音量 裝置為合格品。 此外，圖9所示的為類比測試電路3 1之一例，其具有之斬 波至比較器30"係使？通路MOS電晶體32及N通路MOS電晶體 32·雙方均連接於轉換器31。該類比測試電路之閘極信號形 成電路29’’能夠輸出P通路閘極信號CNTP及N通路閘極信號 CNTN兩者，並依測試模式選擇信號TEST_MODEP的“H/L”來 選擇並輸出兩者的其中一方；圖1所示的TEST_M〇DEP便為 該測試模式選擇信號。TEST_M〇DEP能夠藉由圖1之解碼器 17的輸入TEST_MODE、ZCEN：l、及ZCEN2的組合而由外部進 行設定；當輸入該組合之信號時，控制部10會將 TEST—MODEP向測試電路輸出。此外，也可設置2個 TEST_MODE端子。 測試模式設定信號TE為“H”時，如測試模式選擇信號 TEST—MODEP同時成為“H”的話，閘極信號形成電路29"會將 N通路閘極信號CNTN固定成“L”且將P通路閘極信號與晶片 選擇信號同步進行輸出；藉此，可如圖6所示一般地逐段調 降Vout以進行測試。相反地，測試模式設定信號TE為 -18- 200405656 時，如測試模式選擇信號TEST_M〇DEP為“L”的話，閘極信 號形成電路29，，會將P通路閘極信號CNTN固定成“H”且將N 通路閘極信號與晶片選擇信號同步進行輸出；藉此，可如 圖8所示一般地逐段調升Vout以進行測試。 此實施方式中，雖採在外部設置測試模式設定端子 TEST_M〇DE，以在測試模式設定端子丁EST_M〇DE的電位上 升為“H”時進入測試模式，惟也可在有特別的串行資料輸入 至SDATAI時，使控制部10對應於此而在内部將TE設為： 如此一來，能夠減少LSI的端子。此外，電子音量裝置在進 行實裝時，測試模式設定端子test_mode在使用上係加以 接地（固定於“L”）。 上述說明内容中，為簡化說明，雖以類比電路為1聲道的 電子音量裝置來加以說明，惟本發明也同樣適用於内建有 複數個聲道之類比電路的電子音量裝置。在此情況中，如 圖10所示一般，將複數聲道之類比電路9-1至η個別設於類比 測試電路20-1至η，使各類比測試電路的輸出ATEST1至η在編 碼器40整合成1個信號ATEST後，輸出至選擇器19即可··測 試模式中，如欲使類比測試電路20在Vout正常地下降或上升 時輸出Η時’將編碼為40设為AND電路，使其僅在所有的 類比測試電路20輸出“H”時輸出“H” ；測試模式中，如欲使 類比測試電路20在Vout正常地變化時輸出“L”時，將編碼器 40設為OR電路（低電位動作的AND電路），使其僅在所有的類 比測試電路輸出“L”時輸出“L”。此外，使編碼器4〇能夠依 上述丁EST-MODEP信號在AND電路及〇R電路間進行切換即 -19- 200405656 可。 上述實施例中，雖然類比測試電路2〇係内建於電子音量 裝置1内，然而也可將類比測試電路2〇與電子音量裝置i分 開來設置。 、如上逑般，依本實施方式，由於利用用以輸出_行資料 、 A〇鲕子來輻出類比測試電路20的比較結果信號 ATEST，因此能夠省下所需的端子數。 不此外，在此實施方式中，由於係將類比測試電路内建於 電子音量裝置之内，並對音量設^前後的電壓進行比幹 因此=實現衫、迅速、且誤差小的測試。料，:另 仃對首量設定的其他幾個點進行v〇uU々絕對值的測定，夕 可進一步提高測試精確度。 知 複數 依上述之本發明，將可有效率地對能夠對音量施以 段控制的電子音量裝置進行測試。 [圖式簡單說明] _ i為本發明之實施方式 〜衮置之应塊圖。 上述電子音量裝置之音頻放大器之區塊圖。 為逑電子音量裝置之類比測試電路之區塊圖。 圖4為上述電子音量裝置之類比測試電路之區塊圖。 圖5為上述電子音量裝置與邏輯測試器之 圖6(A)(B)為上述泰子立音裝晉卢、彳、 要万式又圖 之圖。 “子曰篁裝置在進行測試時之各部信彳 圖7(A)(B)為類比測試電路之其他例子之圖。 信號之 圖8 (A K B)為以該類比測試電路進行測試時之各部 -20- 200405656 圖。 圖9為類比測試電路之另外其他例子之圖。 圖10為多聲道電子音量裝置之類比測試電路之連接方式 之圖。 圖11(A)至（C)為一般電子音量裝置内部構造之圖。 圖12(A)(B)為以往之電子音量裝置之測試之說明圖。 [圖式代表符號說明] 1 電子音量裝置 2 輸入緩衝器 3 功率放大器 4 σ刺口八 5 微電腦 6 旋轉編碼器 7 顯示部 8 邏輯測試器 8a 探測信號驅動器 8b 比較器 9 類比電路 10 控制部 11、12 可變電阻 13 放大器 14 解碼器 15 零點觸發檢測電路 16 振盪器 200405656 17 解碼器 18 S/P轉換器 19 選擇器 20 類比測試電路 29 ^ 29'、29"閘極信號形成電路 30、 3(V、30M斬波型比較器 31 轉換器 32 P通路MOS電晶體 32， N通路MOS電晶體 33 電容器 34 轉換器 35 緩衝器 40 編碼器 -22-Figure out the effect caused by the circuit that is maintained at high impedance and connected to the output domain. Although the chopped comparator 3 is connected to only one section in Figure 3, when the converter η increases-the potential difference with respect to the input (~ ν〇 ι) When it appears to be insufficient, the output of Conversion Cry 3] will not have the entire amplitude of "H / L", but will be in the linearly amplified region to give an intermediate value. In this case, 'as shown in Figure 4, in general, you can compare two types of τ Jin wave type 30 in series, so that the output can achieve the entire amplitude of "H / L," to achieve a dual value output. Use Figure 4 In the structure shown, the output voltage “H / L” will be inverted due to the addition of one converter. However, the non-inverted “爰 冲 扎 3 5” is used instead of the converter as the last section. The buffer can make the extreme performance of the output signal the same as that in Fig. 3. Each of the signals of SD and TADa shown in Figs. 6 (A) and (B) is as shown in Fig. 4. The waveform of the chopper-type comparator in series. In Figure 6 (b), the 'chip selection signal CSN' ("L" section) has a bit length equivalent to the data length of the SDATAI synchronized with the serial clock SCLK. μ3. In addition, the interval of the chip selection signal (CSN = “H ,,” is about several ps to 10 w. The volume control data D is input in synchronization with each chip selection signal. The volume control data is data for turning down the volume one step at a time as described above. Logic-16- 200405656 The comparator of tester 8 will read SDATAO (ATEST signal) at a timing of hundreds of ns to several ps after the chip selection signal CSN rises to "Η" to detect the "H / L ". At this time, if the signal is "L", it is judged that the electronic volume device is normal in this section; if the signal is still "H", it is judged that the electronic volume device is unqualified. When the electronic volume device operates normally in all stages, the electronic volume device is judged to be a qualified product. 7 and 8 are diagrams of other embodiments of the analog test circuit. In this analog test circuit 20 ', an N-channel MOS transistor 32' is used instead of the P-channel MOS transistor 32 of the chopper type comparator shown in Figs. 3 and 4. In the analog test circuit 20 of FIG. 1, the gate wiring pattern of the P-channel MOS transistor 32 is a low-potential actuator, so the parasitic capacitance Cs will supply a positive charge to the input terminal of the converter 31, so that the input of the converter 31 1 The voltage Va is biased toward the positive side; however, the gate wiring pattern of the N-channel MOS transistor 32 'in the chopper type comparator of FIG. 7 is a high-potential operator, and the parasitic capacitance Csf supplies a negative charge to the converter 31. , The input terminal Va of the converter 31 is biased toward the negative side. Next, the gate signal forming circuit 2V of the analog test circuit outputs the N-channel gate signal CNTN in synchronization with the wafer selection signal. The figure (A) shows an example where the N-channel type chopper-type comparator 30f is provided with only one stage; the figure (B) shows the N-channel type chopper-type comparator 30 'with two stages. example. Figure 8 shows the signals of various parts of the analog test circuit and logic tester of the electronic volume device with an analog test circuit built in Figure 7 (B) during the test: in Figure 8 (B), the chip The interval of the selection signal CSN and the interval of the wafer selection signal are the same as those shown in FIG. 6 (B). The volume control data is 200405656 input in synchronization with each chip selection signal. The volume control data is data for successively increasing the volume by one step. The comparator of the logic tester 8 reads the SDATAO (ATEST signal) at a timing of hundreds of ns to several ps after the chip selection signal CSN rises to "H" to detect the "H / L" of the voltage. At this time, if the signal is "H", it will be judged that the electronic volume device's action in this section is normal; if the signal drops to "L", it will be judged that the electronic volume device is unqualified. When the operation of the electronic volume device is normal in all stages, the electronic volume device is judged to be a qualified product. In addition, FIG. 9 shows an example of the analog test circuit 31, which has the function of chopping to the comparator 30. Both the pass MOS transistor 32 and the N pass MOS transistor 32 are connected to the converter 31. The gate signal forming circuit 29 "of this analog test circuit can output both the P-channel gate signal CNTP and the N-channel gate signal CNTN, and select and output both according to the" H / L "of the test mode selection signal TEST_MODEP. One of them; TEST_MODEP shown in Figure 1 selects the signal for this test mode. TEST_M0DEP can be set externally by a combination of the inputs TEST_MODE, ZCEN: 1, and ZCEN2 of the decoder 17 in FIG. 1; when a signal of the combination is input, the control section 10 outputs TEST_MODEP to the test circuit . In addition, two TEST_MODE terminals can be set. When the test mode setting signal TE is "H", if the test mode selection signal TEST_MODEP becomes "H" at the same time, the gate signal forming circuit 29 " will fix the N-channel gate signal CNTN to "L" and the P-channel The gate signal is output in synchronization with the chip selection signal; as a result, Vout can be generally lowered segment by segment for testing as shown in FIG. 6. Conversely, when the test mode setting signal TE is -18-200405656, if the test mode selection signal TEST_MODEP is "L", the gate signal forming circuit 29 will fix the P-channel gate signal CNTN to "H" In addition, the N-channel gate signal is output in synchronization with the chip selection signal; thus, Vout can be generally increased step by step for testing as shown in FIG. 8. In this embodiment, although the test mode setting terminal TEST_MODE is set externally to enter the test mode when the potential of the test mode setting terminal DEST_MODE rises to "H", special serial data can also be used. When inputting to SDATAI, the control unit 10 is made to correspond to this and TE is internally set to: In this way, the number of LSI terminals can be reduced. In addition, when the electronic volume device is installed, the test mode setting terminal test_mode is grounded when used (fixed to "L"). In the above description, for the sake of simplicity, although the analog volume circuit is an electronic volume device with one channel for explanation, the present invention is also applicable to an electronic volume device with an analog circuit having a plurality of channels. In this case, as shown in FIG. 10, the analog circuits 9-1 to η of the complex channel are individually set to the analog test circuits 20-1 to η, so that the outputs ATEST1 to η of the various analog test circuits are provided in the encoder. After 40 is integrated into one signal ATEST, it can be output to the selector 19. In the test mode, if you want the analog test circuit 20 to output when Vout drops or rises normally, set the code to 40 as the AND circuit. Make it output "H" only when all analog test circuits 20 output "H"; in test mode, if you want to make analog test circuit 20 output "L" when Vout changes normally, set encoder 40 to OR Circuit (AND circuit operating at low potential) so that it outputs "L" only when all analog test circuits output "L". In addition, the encoder 40 can switch between the AND circuit and the OR circuit according to the above-mentioned EST-MODEP signal, that is, -19-200405656. In the above embodiment, although the analog test circuit 20 is built in the electronic volume device 1, the analog test circuit 20 may be set separately from the electronic volume device i. As above, according to the present embodiment, since the comparison result signal ATEST of the analog test circuit 20 is radiated by using the output line data and A0, the required number of terminals can be saved. In addition, in this embodiment, since the analog test circuit is built in the electronic volume device, and the voltage before and after the volume setting is compared, the test is quick, and the error is small. It is expected that the absolute value of v〇uU will be measured at several other points set by the first volume, which can further improve the test accuracy. Known plural According to the present invention described above, an electronic volume device capable of segment control of a volume can be efficiently tested. [Brief description of the drawings] _i is a block diagram of an embodiment of the present invention. Block diagram of the audio amplifier of the electronic volume device. This is a block diagram of an analog test circuit for an electronic volume device. FIG. 4 is a block diagram of the analog test circuit of the electronic volume device. Fig. 5 is the above electronic volume device and logic tester. Fig. 6 (A) (B) is the diagram of the above-mentioned Taizi Liyin Jinlu, 彳, Yaowan, and other pictures. "Figures 7 (A) (B) of the other parts of the device when the device is being tested. Figure 7 (A) (B) is a diagram of another example of the analog test circuit. Figure 8 of the signal (AKB) is the parts of the test when the analog test circuit is used- 20- 200405656 Figure. Figure 9 is a diagram of another example of an analog test circuit. Figure 10 is a diagram of a connection method of an analog test circuit of a multi-channel electronic volume device. Figures 11 (A) to (C) are general electronic volumes Diagram of the internal structure of the device. Figure 12 (A) (B) is an explanatory diagram of the test of the conventional electronic volume device. [Description of the representative symbols of the figure] 1 Electronic volume device 2 Input buffer 3 Power amplifier 4 σ 刺 口 八 5 Microcomputer 6 Rotary encoder 7 Display section 8 Logic tester 8a Detection signal driver 8b Comparator 9 Analog circuit 10 Control section 11, 12 Variable resistor 13 Amplifier 14 Decoder 15 Zero trigger detection circuit 16 Oscillator 200405656 17 Decoder 18 S / P converter 19 selector 20 analog test circuit 29 ^ 29 ', 29 " gate signal forming circuit 30, 3 (V, 30M chopper type comparator 31 converter 32 P-channel MOS transistor 32 N channel MOS transistor 33 capacitor 34 converter 35 the encoder buffer 40 -22-