1279572 九、發明說明： 【發明所屬之技術領域】 一本發明係有關容易進行使用電流邏輯信號之試驗之 半導體積體電路以及半導體積體電路測試系統。 【先前技術】1279572 IX. Description of the Invention: [Technical Field] The present invention relates to a semiconductor integrated circuit and a semiconductor integrated circuit test system which are easy to perform tests using a current logic signal. [Prior Art]
ic測試器係如下述專利文獻丨所示，對半導體積體電 路施加試驗信號，而根據半導體積體電路之輸出，進行是 否良好之判定。並且，半導體積體電路之邏輯電路，一般 為電壓輸入以及電壓輸出，IC測試器也藉由以電壓賦值之 信號來進行試驗。但是，近年來隨著半導體積體電路之高 速化，為防止雜訊之影響，對邏輯信號開始使用電流信號。 進行這種試驗之情況，參照第2圖進行說明。 [專利文獻1]日本專利特開2002-292500號公報 如第2圖所示，在Ic測試器i中設置多個電子端腳 (pin_electronics) n。在各電子端腳u中設有驅動器 (driver)、比較器（comparat〇r)、直流測定部等。開關 至SW3，其一端連接於IC測試器J之電子端腳^。在開 關SW1之另一端，連接有V/I變換器2之輸入端子。而在 開關SW2之另一端，連接有I/v變換器3之輪出端子。在 V/I變化器2之輸出端子，連接有開關SW4之一端。在 變換器3之輸入端子，連接有開關SW5之一端。在開關 SW6之一端，則連接有開關sw3之另一端。 半導體積體電路（以下稱[DUTD4係為例如經級聯連 接（cascade connected)之液晶驅動器。DUT4有多個信號端 316743修正本 6 1279572 腳41、42,多個開關43、44,以及邏輯電路45，並輸出 多階電壓。在信號端腳4!、42，連接有開關SW4至SW6 之另一端。信號端腳41為輸入側時，信號端腳42成為輸 出側，k號端腳41為輸出側時，信號端腳42成為輸入侧。 在開關43、44之另一端，連接有信號端腳41、42。在邏 •輯電路45,連接有開關43、44之另一端。邏輯電路45係 根據由電流賦值之邏輯信號而動作，若為級聯連接之液晶 >驅動器時，輸入顯示資料，則且驅動器本身之資料除外， 將顯示資料輸出至級聯連接之液晶驅動器。 以下對前述說明之測試系統之動作進行說明。首先， 扣測試器1係從未圖示之電子端腳輸出控制信號，使開關 SW3、SW6導通（ON)，並使其他開關SW1、SW2、請4、 SW5不導通（0FF)。並且，IC測試器i係從未圖示之電子 端腳輪出控制信號，使開關43或開關44的其中之一導通。 在這種狀態下，設置於電子端腳u之未圖示之直流測定部 1將進行DUT4之直流特性試驗。 〇接著’IC：測試器1係從未圖示之電子端腳輸出控制信 號，在使信號端腳41側之開關SW1、SW4導通，使其他 開關SW2、SW3、SW5、SW6不導通之同時，使信號端腳 42侧之開關SW2、SW5導通，使其他開關swm SW4、SW6不導通。並且’ Ic測試器1係未圖示之卯 之端腳上，；k未圖不之電子端腳輸人控制信號，在使信號 端腳41侧之開關43導通，使開關44不導通之同時，使信 號端腳42侧之開閾43不導通，使開關44導通。亦即，^ 316743修正本 7 1279572 測试裔1係將信號端腳41侧設定為輸入侧，將信號端腳 42侧設定為輸出侧。 並且’ 1C測試器1係從信號端腳41侧之電子端腳11 輸出由電壓賦值之電壓邏輯信號。該電壓邏輯信號係透過 開關S W1輪入至v/l變換器2。V/I變換器2係將電壓邏 輯信號變換為由電流賦值之電流邏輯信號，透過開關 ’ SW4、信號端腳41、開關43，將該電流邏輯信號輸出至邏 ‘輯電路45。邏輯電路45係根據輸入之信號，透過開關44、 信號端腳42、開關SW5，將電流邏輯信號輸出至;[/V變換 •器3。I/V變換器3係使電流邏輯信號變換為電壓邏輯信 • 號，透過開關SW2，將該電壓邏輯信號輸出至電子端腳 11。1C測試器1則比較所輸入之電壓邏輯信號與期待值， 進行是否良好之判定。 接著’ 1C測試器1係從未圖示之電子端腳輸出控制信 號，使信號端腳41側之開關SW2、SW5導通，使其他開 •關SW1、SW3、SW4、SW6不導通，同時，使信號端腳42 側之開關SWl、S W4導通，使其他開關s W2、S W3、S W5、 SW6不導通。並且，1C測試器1係對未圖示之DUT4之端 腳，從未圖示之電子端腳輸入控制信號，使信號端腳41 侧之開關43不導通，開關44導通，同時，使信號端腳42 側之開關43導通，開關44不導通。總之，1C測試器1係 將信號端腳41侧設定為輸出側，將信號端腳42侧設定為 輸入側。 同時’ 1C測試器1係從信號端腳42侧之電子端腳u 8 316743修正本 1279572 2出電壓邏輯信號。該電壓邏輯信號係透過開關SWl，輸 電^'V/I。變換器2°V/I變換器2係將電壓邏輯信號變換為 將:邏輯信號，透過開關SW4、信號端腳42、開關43， <邏輯^號輸出至邏輯電路45。邏輯電路45係根據 掏入之枯咕 電、☆ 桔琥’透過開關44、信號端腳41、開關SW5，將 .邏二，輯信號輸出至l/v變換器3。l/v變換器3係將電流 Y信號變換為電壓邏輯信號，透過開關SW2，將該電壓 、籲號輪出至電子端腳1WC測試器、1係比較所輸入之 --^左邏辑信號與期待值，以判定是否良好。 【發明内容】 發明欲解決之課題 來如此，1C測試器1為了利用電壓邏輯信號之輸入輸出 行減驗，以及對藉由電流邏輯信號而動作之DUT4進 f 4 ·驗’需要有V/I變換器2以及I/V變換器3。但是，由 鲁特電4邏輯信號，其位準微小且為高頻率，為確保充分之 〖生’必須將V/I變換器2以及I/V變換器3設置於DUT4 附近之探針卡（probe card)、DUT板（board)上。在此，所謂 才木針卡係指將晶圓狀之DUT4透過探針連接之印刷基板， 所谓DUT板係指將已封裝（package)之DUT4透過插座 (socket)連接之印刷基板。 但是，探針卡、DUT板有面積限制。為對所有信號端 腳41、42設置V/I變換器2以及Ι/ν變換器3，必須將搭 載有這些變換器之基板做成2層、3層，並且，由於亦介 有多數電繞（cable)、連接器（connect〇r)等，因此其維修性 9 316743修正本 !279572 變得極為困難。而UV變換器3由於電路規模大，因此輸 出侧之相位差（skew)之參差會變大。因此，無法容易地進 行利用電流邏輯信號之試驗。 目種可容易進行使用電流邏輯 信號之試驗之半導體積體電路以及半導體積體電路測試系 統0 ~解決課題之方法 I I發明係提供-種半—電路，係具備：用以輸 出電流邏輯信號之多個信號端腳；試驗時，AI/V變換器 電性連接之試驗端腳；從前述多個信號端腳中選擇一個信 號端腳’將前述-個信號端腳連接於前述試驗端腳之選擇 部；輸入用以控制前述選擇部之選擇信號之選擇端腳。 又，本發明提供-種半導體積體電路測試系統，係具 有：具備用以輸出電流邏輯信號之多個信號端腳，且從前 >述多個信號端腳中選擇-個信號端腳，將前述一個信號端 腳連接試驗端腳之半導體積體電路；試驗時，鱼前述半導 =體電路之前述試驗端腳相連接，且將從前述試驗端腳 輸出之電流邏輯信號變換為電壓邏輯信號之Ι/ν變換哭. ^輸入從前述Ι/ν變換器輪出之電壓邏輯信號之^試 亥半導體積體電路測試系統係具備將從前述IC測試 j出之電產邏輯信號變換為電流邏輯信號，且將該電流 遊輯信號輸出至前述半導體積體電路之V/I變換器。 而該半導體積體電路測試系統中，半導體積體電路係 316743修正本 10 1279572 為液晶驅動器。 (發明之效果） =，半導體積體電路以及前述半導體積體電路 由於從選擇部所選擇之信號端腳所連接之試驗 端腳對ι/ν變換哭於ψ堂、ώ、四处 之τ/v轉信號，因此將大電路規模 .ν，吏換裔之數量與以往作比較，可以減少其數量。因 t盖ΓΙ/ν變換11絲於半導體積體電路之附近，從而 f改…維修性。還可抑制輸出側相位差之參差不齊。其结 果’可容易進行使用電流邏輯信號之試驗。 /、 【實施方式】 …利用圖式詳細說明本發明。第i圖係本發明之一實施 形態之測試系統之構成圖。第i圖中，與第2圖所示之構 成要素：同之部分，使用同-符號，並省略其說明。 如弟1圖所示’本實施形態之Ic測試器1〇係具有多 個電：端腳…，、…、…。在各電子端腳中設置有 驅動益、比較益、直流測定部等。開關SW1、請3之一端 係’、1C測減為1 〇之電子端腳J Ja、】lb相連接。在開關 另一端，則連接有V/I變換器2之輸入端子。在ν/ι 交換器2之輸出端子係連接有開關SW4之一端。在開關 SW6之一端係連接有開關SW3之另一端。在開關sw7、 SW8之-端係連接有電子端腳HcciI/v變換器$係代替第 ^圖所示之I/V變換器3而設置。I/v變換器5之輸出端子 係連接於開關SW7之另一端，I/v變換器5之輸入端子係 連接於開關SW9之-端。開關SW1〇之—端係與開關_ 316743修正本 11 1279572 之另一端相連接。本實施形態之半導體積體電路（以下稱 ΡϋΤ])40係具有信號端腳41、42、試驗端腳46、選擇端 腳47、多工器（multiplexer)48以及邏輯電路45。試驗時， 試驗端腳46與開關SW9、SW10之各個另一端相連接。選 擇端腳47係連接於電子端腳lld。多工器48係為選擇部， 對應從選擇端腳47輸入之選擇信號，從信號端腳41、42 中選擇一個信號端腳，將該被選擇之信號端腳連接在試驗 ‘端腳40 〇 以下說明第1圖所示之測試系統之動作。首先，1C測 忒裔10係從未圖示之電子端腳輸出控制信號，使開關 SW3、SW6導通’其他開關swi、SW4不導通。並且，ic 測試器10係從未圖示之電子端腳輸出控制信號，使開關 43導通，使開關44不導通。在該狀態下，設置於電子端 腳11 a、1 lb之未圖示之直流測定部則進行DUT4〇之直流 特性試驗。 ® 然後，1C測試器10係從未圖示之電子端腳輸出控制 仏號，使開關SW8、SW10導通，使開關SW7、SW9不導 通。並且，1C測試器10係從未圖示之電子端腳輸出控制 信號，使開關43不導通，使開關44導通。而IC測試器 10係從f子端腳lid輸出選擇信號，該選擇信號係透過選 擇端腳47輸入至多工器48。多工器48係從信號端腳41、 42中，依序選擇-個信號端腳，當將該信號端腳連接在試 驗端腳46,設置於電子端腳llc之未圖示之直流測定部則 進行DUT40之直流特性試驗。 316743修正本 12 1279572 接著，1C測試器1 〇從未圖示之電子端腳輸出控制信 號，使信號端腳41侧之開關SW1、SW4導通’使開關SW3、 SW6不導通，同時使信號端腳42侧之開關SW1、SW3、 SW4、SW6不導通。而1C測試器10係從未圖示之電子端 腳輸出控制信號，在使開關SW7、SW9導通之同時，使開 關SW8、SW10不導通。於是，1C測試器1〇係對未圖示 -之DUT40之端腳，從未圖示之電子端腳輸入控制信號，使 鲁信號端腳41側之開關43導通，使開關44不導通，同時， 使信號端腳42侧之開關43不導通，使開關44導通。亦即， 1C測試器1〇係將信號端腳41侧設定為輸入側，將信號端 • 腳42側設定為輸出側。 1C測試器10係從信號端腳41側之電子端腳lla輸出 電壓邏輯信號。該電壓邏輯信號係透過開關SW1輸入至 V/I變換器2。V/I變換器2係使電壓邏輯信號變換為電流 邏輯信號，透過開關SW4、信號端腳41、開關43，對邏 •輯電路45輸出該電流邏輯信號。邏輯電路45係根據所輸 入之信號，輸出電流邏輯信號。而1C測試器1〇係從電子 端腳lid輸出選擇信號，該選擇信號則透過選擇端腳47 輸入至多工器48。輸入該選擇信號時，則多工器48係從 k號端腳42中依序選擇一個信號端腳，將該信號端腳連接 於試驗端腳46。其結果，從邏輯電路45輸出之電流邏輯 k唬係透過開關44、多工器48、試驗端腳46、開關SW9， 輸入至I/V變換器5。I/v變換器5係將輸入之電流邏輯信 號文換為電壓邏輯信號，透過開關SW7，將該電壓邏輯信 13 316743修正本 、1279572 a 號輸出至電子端腳llc<3lC測試器1〇係將輸入於電子端腳 11 c之電壓邏輯信號與期待值予以比較，以進行是否良好 之判定。 再者，1C測試器1 〇係從未圖示之電子端腳輸出控制 信號’在使信號端腳41側之開關SW1、SW3、SW4、SW6 不導通之同時，使信號端腳42侧之開關SW卜SW4導通， -使開關SW3、SW0不導通。並且，IC測試器1〇係在未圖 修示之DUT40之端腳上，從未圖示之電子端腳輸入控制信 號，使信號端腳42側之開關43導通，使開關44不導通。 亦即’ 1C測試器10係將信號端腳41侧設定為輸出側，將 '信號端腳42側設定為輸入侧。 而且，1C測試器1〇係從信號端腳42侧之電子端腳 iib輸出電壓邏輯信號。該電壓邏輯信號係透過開關swi 輸入至V/I變換器2。ν/Ι變換器2係將電壓邏輯信號變換 為電流邏輯信號，利用開關SW4、信號端腳42、開關43， 馨對邏輯電路45輸出該電流邏輯信號。邏輯電路45係根據 所輸入的信號，輸出電流邏輯信號。而1C測試器1〇係從 電子端腳lid輸出選擇信號，該選擇信號係透過選擇端腳 47輸入至多工器48。若輸入該選擇信號時，多工器48係 從信號端腳41中依序選擇一個信號端腳，將該信號端腳連 接於試驗端腳46。其結果，從邏輯電路45輸出之電流邏 輯4§唬係透過開關44、多工器48、試驗端腳46及開關 SW9,輸入至I/V變換器5qI/v變換器5係將輸入之電流 邏輯信號變換為電壓邏輯信號，該電壓邏輯信號係透過開 316743修正本 14 1279572 關SW7，輸出至電子端腳llc。Ic測試器1〇係將輸入至 電子知)腳11 c之電壓邏輯彳g號與期待值予以比較，以進行 是否良好之判定。 如此，在本實施形態中，多工器48係從輸出侧之信 號端腳41，42中依序選擇一個信號端腳，由於將從邏輯電 路45輸出之電流邏輯信號輸入至j/v變換器$，因此與以 往相比，可減少大電路規模之I/v變換器之數量。因此， 籲由於可將I/V變換器2、5安裝於DUT4〇之附近，從而改 善其維修性。並可抑制輸出側相位差之參差不齊。其結果， 可容易進行使用電流邏輯信號之試驗。 本么明並非限疋於别述之實施形態。前述實施形態係The ic tester, as shown in the following patent document, applies a test signal to the semiconductor integrated circuit, and determines whether or not it is good based on the output of the semiconductor integrated circuit. Moreover, the logic circuit of the semiconductor integrated circuit is generally a voltage input and a voltage output, and the IC tester is also tested by a voltage-valued signal. However, in recent years, with the increase in the speed of semiconductor integrated circuits, in order to prevent the influence of noise, a current signal is started for the logic signal. The case where such a test is performed will be described with reference to Fig. 2 . [Patent Document 1] Japanese Laid-Open Patent Publication No. 2002-292500 As shown in Fig. 2, a plurality of electronic pin pins (pin_electronics) n are provided in the Ic tester i. A driver, a comparator (comparat〇r), a DC measuring unit, and the like are provided in each of the electronic terminal pins u. Switch to SW3, one end of which is connected to the electronic terminal of IC tester J. At the other end of the switch SW1, an input terminal of the V/I converter 2 is connected. At the other end of the switch SW2, the wheel-out terminal of the I/V converter 3 is connected. One end of the switch SW4 is connected to the output terminal of the V/I variator 2. One end of the switch SW5 is connected to the input terminal of the converter 3. At one end of the switch SW6, the other end of the switch sw3 is connected. The semiconductor integrated circuit (hereinafter referred to as [DUTD4] is, for example, a cascade-connected liquid crystal driver. The DUT 4 has a plurality of signal terminals 316743 to correct the 6 1279572 pins 41 and 42, a plurality of switches 43, 44, and a logic circuit. 45, and output multi-level voltage. At the signal terminal 4!, 42, the other end of the switch SW4 to SW6 is connected. When the signal pin 41 is the input side, the signal pin 42 becomes the output side, and the k-end pin 41 is On the output side, the signal pin 42 becomes the input side. At the other end of the switches 43, 44, the signal pins 41, 42 are connected. In the logic circuit 45, the other ends of the switches 43, 44 are connected. It is operated according to the logic signal assigned by the current. If the liquid crystal is connected in cascade, the display data is input, and the data of the drive itself is output, and the display data is output to the liquid crystal driver connected in cascade. The operation of the test system will be described. First, the buckle tester 1 outputs a control signal from an electronic terminal (not shown), turns on the switches SW3 and SW6, and turns on the other switches SW1, SW2, 4, and SW5. Not guiding (0FF) Further, the IC tester i rotates a control signal from an electronic terminal (not shown) to turn on one of the switch 43 or the switch 44. In this state, the electronic terminal u is not shown. The DC measuring unit 1 is shown to perform the DC characteristic test of the DUT 4. Next, the IC: Tester 1 outputs a control signal from an electronic terminal (not shown), and turns on the switches SW1 and SW4 on the signal terminal 41 side. When the other switches SW2, SW3, SW5, and SW6 are not turned on, the switches SW2 and SW5 on the signal terminal 42 side are turned on, so that the other switches swm SW4 and SW6 are not turned on, and the 'Ic tester 1 is not shown. On the terminal pin, k does not indicate the electronic terminal input control signal, and the switch 43 on the signal terminal 41 side is turned on, so that the switch 44 is not turned on, and the open threshold 43 of the signal terminal 42 side is not turned on. , the switch 44 is turned on. That is, ^ 316743 correction 7 1279572 test 1 system sets the signal pin 41 side as the input side, the signal pin 42 side as the output side. And '1C tester 1 is from The electronic terminal 11 on the side of the signal terminal 41 outputs a voltage logic signal assigned by the voltage The voltage logic signal is transmitted to the v/l converter 2 through the switch S W1. The V/I converter 2 converts the voltage logic signal into a current logic signal assigned by the current, through the switch 'SW4, the signal pin 41. The switch 43 outputs the current logic signal to the logic circuit 45. The logic circuit 45 outputs the current logic signal to the switch 44, the signal pin 42 and the switch SW5 according to the input signal; [/V conversion • I. 3. The I/V converter 3 converts the current logic signal into a voltage logic signal, and outputs the voltage logic signal to the electronic terminal 11 through the switch SW2. The 1C tester 1 compares the input voltage logic. The signal and the expected value are judged whether it is good or not. Then, the 1C tester 1 outputs a control signal from an electronic terminal (not shown), and turns on the switches SW2 and SW5 on the signal terminal 41 side, so that the other on/off switches SW1, SW3, SW4, and SW6 are not turned on, and at the same time, The switches SW1 and S W4 on the signal terminal 42 side are turned on, so that the other switches s W2, S W3, S W5, and SW6 are not turned on. Further, the 1C tester 1 is connected to a terminal end of the DUT 4 (not shown), a control signal is input from an electronic terminal (not shown), the switch 43 on the signal terminal 41 side is not turned on, and the switch 44 is turned on, and at the same time, the signal terminal is turned on. The switch 43 on the side of the foot 42 is turned on, and the switch 44 is not turned on. In short, the 1C tester 1 sets the signal pin 41 side as the output side and the signal pin 42 side as the input side. At the same time, the 1C tester 1 corrects the voltage signal of the 1279572 2 from the electronic terminal u 8 316743 on the side of the signal terminal 42. The voltage logic signal is transmitted through the switch SW1 to output ^'V/I. The converter 2°V/I converter 2 converts the voltage logic signal into a logic signal, which is output to the logic circuit 45 through the switch SW4, the signal terminal 42 and the switch 43, and the logic signal. The logic circuit 45 outputs a signal to the l/v converter 3 based on the input power, the ☆ orange husperium through the switch 44, the signal terminal 41, and the switch SW5. The l/v converter 3 converts the current Y signal into a voltage logic signal, and passes the switch SW2 to turn the voltage and the call number out to the electronic terminal 1WC tester, and the 1 system compares the input - the left logic signal And expect the value to determine whether it is good. SUMMARY OF THE INVENTION The problem to be solved by the invention is that the 1C tester 1 needs to have a V/I in order to utilize the input and output lines of the voltage logic signal to be decremented, and to operate the DUT 4 that is operated by the current logic signal. Inverter 2 and I/V converter 3. However, the signal of the Lut 4 logic signal is small and high frequency. In order to ensure sufficient [Voice], the V/I converter 2 and the I/V converter 3 must be placed near the DUT4 (probe). Card), DUT board (board). Here, the wood card refers to a printed circuit board that connects a wafer-shaped DUT 4 through a probe. The DUT board refers to a printed circuit board that connects a packaged DUT 4 through a socket. However, the probe card and DUT board have an area limitation. In order to provide the V/I converter 2 and the Ι/ν converter 3 for all of the signal pins 41 and 42, the substrate on which these inverters are mounted must be formed into two layers and three layers, and since most of the electric windings are also involved. (cable), connector (connect〇r), etc., so its maintainability 9 316743 revision! 279572 becomes extremely difficult. On the other hand, since the UV converter 3 has a large circuit scale, the phase difference of the output side (skew) becomes large. Therefore, the test using the current logic signal cannot be easily performed. The semiconductor integrated circuit and the semiconductor integrated circuit test system which can easily perform the test of the current logic signal can be easily used. The invention II provides a semi-circuit having a plurality of output logic signals. Signal pin; test end, test end of the AI/V converter electrically connected; select one of the plurality of signal pins to select the signal pin to connect the aforementioned signal pin to the test pin a selection terminal for controlling a selection signal of the selection unit. Moreover, the present invention provides a semiconductor integrated circuit test system having a plurality of signal terminals for outputting a current logic signal, and selecting one of the plurality of signal pins from the preceding > The signal terminal is connected to the semiconductor integrated circuit of the test terminal; during the test, the test terminal of the fish semi-conductor circuit is connected, and the current logic signal output from the test pin is converted into a voltage logic signal. Ι / ν change to cry. ^ Input voltage logic signal from the aforementioned Ι / ν converter ^ test semiconductor integrated circuit test system with the conversion of the electrical logic signal from the IC test j into current logic And outputting the current play signal to the V/I converter of the semiconductor integrated circuit. In the semiconductor integrated circuit test system, the semiconductor integrated circuit system 316743 is modified as a liquid crystal driver. (Effects of the Invention) =, the semiconductor integrated circuit and the semiconductor integrated circuit are cried in the ι/, ώ, and τ/v by the test pin connected to the signal terminal selected from the selection unit. Turning the signal, so the number of large circuit scales. ν, 吏 吏 与 与 与 与 。 。 。 。 。 。 。 。 。 。 。 Since the t-cover/ν-transform 11 filament is in the vicinity of the semiconductor integrated circuit, f is changed to maintainability. It is also possible to suppress the jaggedness of the phase difference on the output side. The result 'can be easily tested using current logic signals. [Embodiment] The present invention will be described in detail using the drawings. Figure i is a block diagram of a test system in accordance with one embodiment of the present invention. In the first embodiment, the same components as those in the second embodiment are denoted by the same reference numerals, and the description thereof will be omitted. As shown in Fig. 1, the Ic tester 1 of the present embodiment has a plurality of electric powers: end legs ..., ..., .... A drive benefit, a comparison benefit, a DC measurement unit, and the like are provided in each of the electronic pins. The switches SW1 and 3 are connected to one of the ends, and the electronic terminals J Ja and lb of 1C are measured and reduced to 1 连接. At the other end of the switch, the input terminal of the V/I converter 2 is connected. One end of the switch SW4 is connected to the output terminal of the ν/ι converter 2. The other end of the switch SW3 is connected to one end of the switch SW6. An electronic terminal HcciI/v converter is connected to the end of the switches sw7 and SW8 in place of the I/V converter 3 shown in Fig. The output terminal of the I/V converter 5 is connected to the other end of the switch SW7, and the input terminal of the I/V converter 5 is connected to the terminal of the switch SW9. The switch SW1 is connected to the other end of the switch _ 316743 modification 11 1279572. The semiconductor integrated circuit (hereinafter referred to as ΡϋΤ) 40 of the present embodiment has signal terminals 41 and 42, a test terminal 46, a selection terminal 47, a multiplexer 48, and a logic circuit 45. During the test, the test leg 46 is connected to each of the other ends of the switches SW9 and SW10. The selection end leg 47 is connected to the electronic end leg 11d. The multiplexer 48 is a selection unit that selects a signal terminal from the signal pins 41 and 42 corresponding to the selection signal input from the selection terminal 47, and connects the selected signal pin to the test 'end 40 〇 The operation of the test system shown in Fig. 1 will be described below. First, the 1C measurement of the 10th generation of the genus 10 sets the control signal from the electronic terminal, so that the switches SW3 and SW6 are turned on. The other switches swi and SW4 are not turned on. Further, the ic tester 10 outputs a control signal from an electronic terminal (not shown) to turn on the switch 43 to make the switch 44 non-conductive. In this state, the DC measuring unit (not shown) provided at the electronic terminals 11a and 1b performs the DC characteristic test of the DUT4. ® Then, the 1C tester 10 outputs a control nickname from an electronic terminal that is not shown, so that the switches SW8 and SW10 are turned on, and the switches SW7 and SW9 are not turned on. Further, the 1C tester 10 outputs a control signal from an electronic terminal not shown, so that the switch 43 is not turned on, and the switch 44 is turned on. The IC tester 10 outputs a selection signal from the f sub-pin, which is input to the multiplexer 48 through the selection terminal 47. The multiplexer 48 selects a signal terminal from the signal pins 41 and 42 in sequence, and connects the signal pin to the test terminal 46, and is disposed in a DC measuring unit (not shown) of the electronic terminal block llc. Then, the DC characteristic test of the DUT 40 is performed. 316743 Amendment 12 1279572 Next, the 1C tester 1 outputs a control signal from an electronic terminal not shown, so that the switches SW1 and SW4 on the signal terminal 41 side are turned on 'to make the switches SW3 and SW6 non-conductive, and at the same time make the signal terminal The switches SW1, SW3, SW4, and SW6 on the 42 side are not turned on. The 1C tester 10 outputs a control signal from an electronic terminal (not shown), and turns on the switches SW7 and SW9 while turning off the switches SW8 and SW10. Then, the 1C tester 1 is connected to a terminal of the DUT 40 (not shown), and a control signal is input from an electronic terminal (not shown) to turn on the switch 43 on the side of the signal terminal 41, so that the switch 44 is not turned on. , the switch 43 on the signal pin 42 side is not turned on, and the switch 44 is turned on. That is, the 1C tester 1 sets the signal pin 41 side as the input side and the signal end side 42 side as the output side. The 1C tester 10 outputs a voltage logic signal from the electronic terminal 11a on the signal terminal 41 side. The voltage logic signal is input to the V/I converter 2 through the switch SW1. The V/I converter 2 converts the voltage logic signal into a current logic signal, and outputs the current logic signal to the logic circuit 45 through the switch SW4, the signal terminal 41, and the switch 43. The logic circuit 45 outputs a current logic signal based on the input signal. The 1C tester 1 outputs a selection signal from the electronic terminal pin, and the selection signal is input to the multiplexer 48 through the selection terminal 47. When the selection signal is input, the multiplexer 48 sequentially selects a signal terminal from the k-terminal 42 and connects the signal terminal to the test terminal 46. As a result, the current logic k唬 output from the logic circuit 45 is input to the I/V converter 5 through the switch 44, the multiplexer 48, the test terminal 46, and the switch SW9. The I/V converter 5 converts the input current logic signal signal into a voltage logic signal, and through the switch SW7, the voltage logic signal 13 316743 is corrected, and the 1279572 a is output to the electronic terminal pin <3lC tester 1 The voltage logic signal input to the electronic terminal 11c is compared with the expected value to determine whether it is good or not. In addition, the 1C tester 1 outputs a control signal from an electronic terminal (not shown). The switch SW1, SW3, SW4, and SW6 on the side of the signal terminal 41 are not turned on, and the switch on the signal terminal 42 side is turned on. SW SW4 is turned on, - the switches SW3, SW0 are not turned on. Further, the IC tester 1 is attached to the end of the DUT 40 which is not shown, and a control signal is input from an electronic terminal (not shown) to turn on the switch 43 on the signal terminal 42 side, so that the switch 44 is not turned on. In other words, the 1C tester 10 sets the signal pin 41 side as the output side and the 'signal pin 42 side as the input side. Further, the 1C tester 1 outputs a voltage logic signal from the electronic terminal iib on the side of the signal terminal 42. The voltage logic signal is input to the V/I converter 2 through the switch swi. The ν/Ι converter 2 converts the voltage logic signal into a current logic signal, and outputs the current logic signal to the logic circuit 45 by means of the switch SW4, the signal terminal 42 and the switch 43. The logic circuit 45 outputs a current logic signal based on the input signal. The 1C tester 1 outputs a selection signal from the electronic terminal pin, and the selection signal is input to the multiplexer 48 through the selection terminal 47. When the selection signal is input, the multiplexer 48 sequentially selects a signal pin from the signal pin 41 and connects the signal pin to the test pin 46. As a result, the current logic output from the logic circuit 45 is transmitted through the switch 44, the multiplexer 48, the test terminal 46, and the switch SW9, and is input to the I/V converter 5qI/v converter 5 to input the current. The logic signal is converted into a voltage logic signal, which is modified by opening 316743 to turn off the SW7 and output to the electronic terminal block. The Ic tester 1 compares the voltage logic 彳g number input to the electronically known pin 11c with the expected value to determine whether it is good or not. Thus, in the present embodiment, the multiplexer 48 sequentially selects one signal terminal from the signal terminals 41, 42 on the output side, since the current logic signal output from the logic circuit 45 is input to the j/v converter. $, therefore, the number of I/V converters that can reduce the size of large circuits can be reduced compared with the past. Therefore, since the I/V converters 2, 5 can be mounted in the vicinity of the DUT 4, the maintainability is improved. It can also suppress the jaggedness of the phase difference on the output side. As a result, the test using the current logic signal can be easily performed. This is not limited to the implementation of the description. The foregoing embodiment is
t置有一個I/V變換器5，但也可以設置2個以上之I/V 變換器5。但是，此時，DUT4〇必須具備2個以上之 器48 〇 雖顯示DUT40為液晶驅動器之情形，但亦可適用於 藉由電流邏輯信號而動作之邏輯電路之試驗的情形。 又，雖顯示進行輸入輸出之信號端腳41、42之情形， T輸入端腳與輸出端腳亦可分別構成。並且，在多個輸出 鳊腳内，也可將一個輸出端腳作為試驗端腳使用。 、又’設置開關SW8、SW10,並設置輸出側直流特性 試驗之路徑（path)，藉由_ SW3、SW6之路徑進行輸出 側之直流特性試驗，也可不設置開關sW8、SW10。 【圖式簡單說明】 第1圖係本發明之-實施形態之測試系統之構成圖。 15 316743修正本 1279572 第2圖係表示習知測試系統之構成圖 【主要元件符號說明】 1、10 1C測試器 2 V/I變換器 4、40 半導體積體電路 5 ι/v變換器 -11 電子端腳 • 41、42 信號端腳 43 、 44 、 ‘ SW1〜SW6 開關 45 邏輯電路 46 試驗端腳 47 選擇端腳 48 多工器 16 316743修正本An I/V converter 5 is provided, but two or more I/V converters 5 may be provided. However, at this time, the DUT 4 must have two or more devices. 48 Although the DUT 40 is shown as a liquid crystal driver, it can also be applied to a test of a logic circuit that operates by a current logic signal. Further, although the signal terminals 41 and 42 for input and output are displayed, the T input pin and the output pin may be separately configured. Also, in the output pin, one output pin can also be used as the test pin. Further, the switches SW8 and SW10 are set, and the path of the DC characteristic test on the output side is set. The DC characteristic test on the output side is performed by the path of _SW3 and SW6, and the switches sW8 and SW10 are not provided. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a configuration diagram of a test system according to an embodiment of the present invention. 15 316743 Amendment 1279572 Figure 2 shows the structure of a conventional test system [Description of main components] 1. 10 1C tester 2 V/I converter 4, 40 semiconductor integrated circuit 5 ι/v converter-11 Electronic end pins • 41, 42 signal terminal pins 43, 44, 'SW1~SW6 switch 45 logic circuit 46 test pin 47 selection pin 48 multiplexer 16 316743 revision