JP2011137684A - Semiconductor integrated circuit and method of testing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To achieve tests with few terminals on LSI chips, concerning an external terminal test of a semiconductor integrated circuit. <P>SOLUTION: A method is provided for testing the semiconductor integrated circuit having an internal circuit, a plurality of external terminals connected to the internal circuit, and a test circuit provided between the internal circuit and the plurality of external terminals for testing the plurality of external terminals. The plurality of external terminals are connected to one common wire connected to a tester when the external terminals include a plurality of external output terminals. The test circuit decodes control signals from the tester to generate selection signals, selects any one external output terminal among the plurality of external output terminals on the basis of the selection signals, inputs test signals from the tester, outputs the test signals from one selected externa output terminal to the common wire, and observes test signals output via the common wire by the tester to test the continuity of the external output terminals. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a semiconductor integrated circuit and a test method for a semiconductor integrated circuit, and more particularly to a test method for an external input terminal, an external output terminal, an external input / output terminal, and an external input / output circuit associated therewith.

  With the high integration of semiconductor integrated circuits, the test cost of LSI chips is increasing. As a means for reducing the test cost, it is common to use a parallel test in which a plurality of LSI chips are tested simultaneously. The number of external terminals required for the test can be the most obstacle in realizing the parallel test, and it must be kept smaller than the number of terminals of the LSI tester.

  Due to advances in design for testability (DFT) technology, it is now possible to test internal circuits of LSI chips with a small number of external terminals. On the other hand, in the test of the external terminals of the LSI chip, it is necessary to connect all the external terminals to the LSI tester, which is an obstacle in the parallel test. Due to this restriction, the test cost reduction effect is impaired, for example, the test process for the LSI internal circuit and the LSI external terminal is divided (corresponding to the LSI internal: parallel test, LSI external terminal: individual test).

  A technique for testing external terminals of a multi-pin configuration by placing a test circuit and a test board between an internal circuit and an external terminal and controlling the test circuit as a test for external terminals of a semiconductor integrated circuit 1.

  FIG. 4 is a diagram showing an integrated circuit in which the test circuit described in Patent Document 1 is incorporated. As shown in FIG. 4, an integrated circuit (LSI) 201 described in Patent Document 1 includes an internal circuit 210 and a tristate buffer 220 that receives an internal output signal from the internal circuit 210 and outputs the internal output signal to an external output terminal 240. . The tri-state buffers 220 are classified into m sets of two each, and the test circuit 260 is configured by collecting two tri-state buffers. Further, the LSI chip 201 includes two external input terminals 250 for inputting control signals from the LSI tester 203 and two input buffers 230 connected to the external input terminals 250. The two input buffers 230 output a control signal to each of the two tri-state buffers 220 included in each of the m test circuits 260 and simultaneously control the m test circuits 260.

  A test board 202 is connected between the LSI 201 and the LSI tester 203, and the test board short-circuits two external output terminals 240 of each test circuit 220 and connects them to one tester terminal m1. Since 201 has m test circuits 260, m tester terminals are required.

  The tester 203 has two tester terminals k1 and k2 for outputting control signals, and each tester terminal k1 and k2 is connected to the input buffer 230 via the two input terminals 250 of the LSI 201. Yes.

  Here, a case where the LSI 201 is tested will be described. A control signal output from the LSI tester 203 is input to each of the two tri-state buffers 220 constituting the test circuit 260 via the input terminal 250 and the input buffer 230. With this control signal, one of the two tri-state buffers 220 is set to high impedance, and a signal from the internal circuit 210 is output to the test board 202 via the output terminal 240.

  The LSI tester 203 receives one output from each set of the test circuits 260, and executes each set of tests.

  As described above, it is necessary to perform the test for the number of times corresponding to the number of tristate buffers 220 constituting each set by combining the outputs of each set into one by the test board 202, but the tester terminals are the sum of the external terminals. Can be less. That is, a total of 2 + m pieces of two tester terminals k1 and k2 for inputting control signals for controlling the tristate buffer 220 from the tester 203 and m terminals of the tester terminals m1 to mm for measuring the output signals. By using this tester terminal, it is possible to test all the LSI 201 external output terminals.

  On the other hand, a device using JTAG is known as a device for testing an internal circuit and an external terminal of an LSI.

  FIG. 5 shows a boundary scan circuit defined by IEEE1149.1. The circuit of this technique includes an LSI chip 500, a TAP controller 550 as a test circuit disposed on the LSI chip 500, a boundary scan register 510, and a test line 540 connecting the TAP controller 550 and the boundary scan register 510. Each boundary scan register 510 is configured to be connected to a plurality of external terminals 520 via a buffer 560. The external terminal 520 is connected to the tester terminal 530, and the LSI tester 503 inputs and outputs signals from the tester terminal 530.

  The TAP controller 550 operates with five test signals prepared in the LSI. A value can be freely set in each boundary scan register 510 by the TAP controller 550, and the external terminal 520 can be set to an arbitrary state according to the set value. When testing the external terminal 520, the test signal output from the TAP controller 550 is input to each boundary scan register 510 via the test wiring 540, and from the boundary scan register 510 to the output terminal 520 via the buffer 560. It is output and measured by an LSI tester connected to the external terminal 520. The test can be performed by measuring the signal input from the TAP controller and the signal output from the output terminal with a tester.

  In addition, a device using NAND Tree is known as a device for testing an external terminal. In this technique, an external terminal and a NAND tree are connected, and an external terminal and a tester terminal of an LSI tester are connected. The terminal for inputting the NAND Tree test control signal and the terminal for outputting the test result are directly connected to the LSI tester.

  The LSI tester outputs a test control signal and a test signal to the NAND tree, and measures one test result output signal output from the test result output terminal to test the external terminal. This technique requires a tester terminal for inputting a test control signal, a tester terminal for measuring a test result, and a tester terminal for connecting to an external terminal.

JP-A-10-115666

Institute of Electrical and Electronics Engineers Inc. “IEEE Standard Test Access Port and Boundary-Scan Architecture”, USA, May 21, 1990 (May 21, 1990), page (p.7-13 to 7-15) )

  However, the technique described in Patent Document 1 can be applied only when testing an external output terminal, and also when testing an external output terminal, two tester terminals that receive control signals from the tester 203. Therefore, 2 + m tester terminals are required in combination with m terminals for measuring the output signal, and the number of terminals used when testing the LSI cannot be reduced any more.

  When JTAG is used, the TAP controller requires five terminals for control, and all external output terminals must be connected to the tester.

  Further, when NAND Tree is used, the number of terminals for test control may be two, but the same point is that all external terminals must be connected to the tester.

  Accordingly, when the number of LSI chips to be tested at the same time is increased to further reduce the test cost, a test method capable of realizing the LSI chip test with fewer terminals is required.

  A semiconductor integrated circuit and a method for testing a semiconductor integrated circuit according to the present invention include an internal circuit, a plurality of external terminals connected to the internal circuit, and a plurality of external terminals provided between the internal circuit and the plurality of external terminals. A test method for a semiconductor integrated circuit having a test circuit for testing a plurality of external output terminals when the external terminal includes a plurality of external output terminals, wherein the plurality of external terminals are connected to one common wiring connected to the tester. Connect, generate a selection signal by decoding the control signal from the tester by the test circuit, select one of the plurality of external output terminals by the selection signal, input the test signal from the tester, and select This test signal is output from the external output terminal to the common wiring, and the test signal output through the common wiring is observed with a tester to test the continuity of the external output terminal. Test method for an integrated circuit and a semiconductor integrated circuit.

  In the present invention, any one of a plurality of external output terminals is selected based on the selection signal, a test signal is output from the tester via the selected one external output terminal, and the output test is output. The signal is observed with a tester through the common wiring. Therefore, one tester terminal can be used for observing the test result.

  A semiconductor integrated circuit and a method for testing a semiconductor integrated circuit according to the present invention include an internal circuit, a plurality of external terminals connected to the internal circuit, and a plurality of external terminals provided between the internal circuit and the plurality of external terminals. A test method for a semiconductor integrated circuit having a test circuit for testing a plurality of external input terminals when the external terminal includes a plurality of external input terminals, and a single common wiring connected to the tester The test signal output from the tester is input to a plurality of external input terminals via the common wiring, and the test signal output from the tester is received via the plurality of external input terminals. The control signal is decoded to generate a selection signal, and one of the test signals input from a plurality of external input terminals is selected by the selection signal, and the selected one is selected. The test signal is a test method a semiconductor integrated circuit and a semiconductor integrated circuit to test continuity of the external input terminal by observing output to the tester.

  In the present invention, one of the plurality of external input terminals is selected based on the selection signal. In addition, the test circuit receives test signals input from a plurality of external input terminals via a common wiring from the tester, and selects and outputs one of the signals according to the selection signal. One tester terminal can be used.

  The semiconductor integrated circuit and the semiconductor integrated circuit testing method according to the present invention greatly reduce the number of LSI tester terminals required for the test of the output external terminals in the test of the external terminals, thereby reducing the LSI test cost.

1 is a diagram of an overall configuration according to a first embodiment. 1 is a diagram of a test signal selection circuit according to a first embodiment; 1 is a diagram of a test control circuit according to a first embodiment; It is a circuit diagram which performs the test of the external terminal of the conventional patent document 1. FIG. It is a circuit diagram of the test using conventional IEEE1149.1.

Embodiment 1
FIG. 1 is a diagram showing a semiconductor integrated circuit (LSI chip) according to the first embodiment of the present invention. The LSI chip 1 according to the first embodiment includes an internal circuit (not shown), a plurality of external output terminals 14a and external input terminals 14b connected to the internal circuit (hereinafter, unless there is a particular need to distinguish between them) The output terminal 14a and the external input terminal 14b are collectively referred to as the external terminal 14), and a test circuit provided between the internal circuit and the plurality of external terminals 14 for testing the plurality of external terminals 14. ing. The test circuit includes a test signal selection circuit 10 and a test control circuit 19. A tristate buffer 12 as an output circuit is provided between the test signal selection circuit 10 and the external output terminal 14a so as to correspond to each external output terminal 14a, and between the test signal selection circuit 10 and the external input terminal 14b. Are provided with an input buffer 13 as an input circuit corresponding to each external input terminal 14b.

  The test signal selection circuit 10 is connected to a plurality of external output terminals 14 a via tristate buffers 12, and is connected to a plurality of external input terminals 14 b via input buffers 13. The test control circuit 19 is connected to the external reset terminal 16, the external test clock terminal 17, and the external test input / output terminal 18, and signals input from the LSI tester 20 through the terminals to the test signal selection circuit 10. input.

  The LSI tester 20 has tester terminals 22 to 25. The external terminal 14 is wired to the test common wiring 11, and the test common wiring 11 is connected to the tester terminal 22. The test common wiring 11 is formed on a test board (DUT board, not shown) for performing electrical connection between the tester and the semiconductor integrated circuit. The LSI chip 1 includes a plurality of output circuits including an external output terminal 14a and a plurality of input circuits including an external input terminal 14b. The plurality of input circuits and output circuits are connected to a set of testers 20 via a common wiring. Wired connection is made to the terminals 22-25. At the time of testing, as will be described later, any one input circuit or output circuit is selected by the test circuit of the LSI chip 1, and one of the external input terminals or one external output terminal is tested.

  The tester terminals 23 to 25 are connected to the external reset terminal 16, the external test clock terminal 17, and the external test input / output terminal 18, respectively. The LSI tester 20 inputs / outputs test signals via the tester terminals 22 and 25 and outputs control signals via the tester terminals 23 and 24.

  The LSI chip 1 has a plurality of external terminals 14, and the input / output to the external terminals 14 is connected to the test common wiring 11 to be one. Therefore, the LSI tester 20 includes a plurality of testers of the LSI chip 1 only by a total of four tester terminals including the input / output terminals 22 and 25 of the external terminal 14 and the two terminals 23 and 24 for inputting two control signals. The external terminal 14 can be tested. Further, even when there are a plurality of LSI chips connected to the test common wiring 11, it is effective because the input / output to the external terminal 14 of the test common wiring 11 can be made one. The details will be described below.

  First, the test signal selection circuit 10 will be described. FIGS. 2A and 2B are diagrams showing the test signal selection circuit 10, and FIG. 2A corresponds to the external output terminal 14a. FIG. 2B shows a test signal selection circuit (hereinafter referred to as an input side test signal selection circuit 10b) corresponding to the external input terminal 14b. It is a figure which shows.

  As shown in FIG. 2A, the output side test signal selection circuit 10a has a selection circuit 21a as a first selector and a selection circuit 21b as a second selector.

  The selection circuit 21 a receives the signal from the internal circuit and the test signal 103 from the test control circuit 19, and outputs one of them to the tristate buffer 12.

  The selection circuit 21 b receives a signal from the internal circuit and the test selection signal 101 from the test control circuit 19, and outputs one of them as a tristate buffer enable signal 109 to the tristate buffer 12.

  The input side test signal selection circuit 10 b outputs the test output signal 104 input from the LSI tester 20 to the internal circuit and the test control circuit 19 via the input buffer 13.

  Next, the test control circuit 19 according to the present embodiment is shown. FIG. 3 is a diagram showing the test control circuit 19. The test control circuit 19 includes a test result selection circuit 31 as a third selector, a decode signal output circuit 33, a counter circuit 34, and a bidirectional buffer 32. Further, it has an external reset terminal 16, an external test clock terminal 17, and an external test input / output terminal 18.

  The external reset terminal 16 and the external test clock terminal 17 are connected to the counter circuit 34, and the external reset signal 107 and the external test clock 108 from the LSI tester 20 are input to the counter circuit 34, respectively.

  The counter circuit 34 is connected to the decode signal output circuit 33, and the counter circuit 34 inputs the count result 106 to the decode signal output circuit 33. The decode signal output circuit 33 generates a test selection signal 101 and inputs the test selection signal 101 to the test signal selection circuit 10 shown in FIG. The decode signal output circuit 33 is connected to the bidirectional buffer 32 and the test result selection circuit 31, and inputs the control signal 101 and the input / output switching signal 105 to the bidirectional buffer 32 and the test result selection circuit 31, respectively. In response to the input / output switching signal 105, the bidirectional buffer 32 outputs the test input signal 103 output from the tester terminal 25 of FIG. Alternatively, the test output signal 104 output from the test result selection circuit 31 is output to the tester terminal 25 via the external test input / output terminal 18.

  The bidirectional buffer 32 is connected to the external test input / output terminal 18, receives the test input signal 103 from the LSI tester 20 via the external test input / output terminal 18, and inputs it to the test signal selection circuit 10 shown in FIG. Alternatively, the test output signal 104 from the test signal selection circuit 10 is output to the external test input / output terminal 18 via the test result selection circuit 31. The test output signal 104 output to the tester terminal 25 via the external test input / output terminal 18 can be observed by the LSI tester 20.

  Here, the test circuit may include a decode circuit that generates the test selection signal 101 and a selection circuit for selecting any one of the external terminals. That is, the decode circuit receives a control signal from the LSI tester 20, generates the test selection signal 101 that decodes the control signal and selects one of the plurality of external output terminals 14a, and / or the LSI tester 20 The control signal is received, and the control signal is decoded to generate a test selection signal 101 for selecting any one of the plurality of external input terminals 14b. The decode signal output circuit 33 and the counter 34 shown in FIG. Have

  The selection circuit selects any one of the plurality of external output terminals 14a based on the test selection signal 101 generated by the decoding circuit, and the LSI tester 20 outputs the selected one of the external output terminals 14a. A test input signal 103 is output and / or a test output signal 104 from a plurality of external input terminals 14b is received, and one of them is selected by a test selection signal 110 and output to the LSI tester 20, 2 includes an output side test signal selection circuit 10a and an input side test signal selection circuit 10b, and a test result selection circuit 31 shown in FIG.

  The selection circuit includes a selection circuit 21a to which a signal from the internal circuit and a test input signal are input, and a selection circuit 21b to which a signal and a selection signal from the internal circuit are input. As described above, the selection circuit 21 a selects the test input signal 103 by the test enable signal 102 input from the LSI tester 20 and outputs it to the tristate buffer 12. The selection circuit 21 b selects the test selection signal 101 based on the test enable signal 102 and outputs it to the tristate buffer 12 as the tristate buffer enable signal 109. The tri-state buffer 12 is enabled by the tri-state buffer enable signal 109, and outputs a test input signal via the external output terminal 14a.

  The selection circuit also includes a test result selection circuit 31 that receives a test output signal 104 input from the LSI tester 20 via the external input terminal 14b. The test result selection circuit 31 selects the test output signal 104 from any one of the external input terminals 14b based on the test selection signal 110 and outputs the selected test output signal 104 to the LSI tester 20.

  Next, the operation of each block when performing a test will be described in detail. Although the LSI chip 1 according to the present embodiment is described as having both the external output terminal 14a and the external input terminal 14b, a corresponding test circuit is provided even if only one of them is provided. Of course, it can be tested as well. First, a test method for the external output terminal 14a will be described.

  During the test, the LSI tester 20 outputs the external reset signal 107 and the external test clock signal 108 as control signals to the test control circuit 19 via the tester terminals 23 and 24, respectively. The external reset signal 107 and the external test clock signal 108 are input to the counter circuit 34 via the external reset terminal 16 and the external test clock terminal 17, respectively.

  The LSI tester 20 outputs a test input signal 103 from the tester terminal 25, and the output test input signal 103 is output from the test signal selection circuit 10 via the external input / output terminal 18 and the bidirectional buffer 32 of the LSI chip 1. Is input.

  The counter circuit 34 has a counter, and when the external reset signal 107 is received, the counter circuit 34 resets the counter and starts counting the external test clock signal 108. At this time, the external reset signal 107 is simultaneously supplied to the test signal selection circuit 10 as the test enable signal 102. The counter circuit 34 outputs the count result 106 of the external test clock signal 108 to the decode signal output circuit 33.

  The decode signal output circuit 33 generates a test selection signal 101 from the count result 106. The test selection signal 101 is a signal generated for the number of external output terminals 14a, and is a signal for selecting only one of the external output terminals 14a. That is, only one of the test selection signals 101 may be 1 and the remaining 0. The decode signal output circuit 33 outputs the test selection signal 101 to the select circuit 21b.

  The decode signal output circuit 33 outputs the input switching signal 105 to the bidirectional buffer 32 and switches the bidirectional buffer 32 to the output side. In addition to the test selection signal 101 for selecting any one of the external output terminals 14a, the decode signal output circuit 33 receives a test selection signal 101 for selecting any one of the inputs of the external input terminal 14b, as will be described later. When the test selection signal 101 is generated, the input switching signal 105 using the bidirectional buffer 32 as an input buffer is generated, and the test selection signal 101 for selecting any one of the external input terminals 14b is generated. When doing so, the input switching signal 105 which uses the bidirectional buffer 32 as an output buffer is generated.

  The bidirectional buffer 32 is set in the input buffer by the input switching signal 105, and outputs the test input signal 103 from the LSI tester 20 to the select circuit 21a.

  Next, the operation of the output side test signal selection circuit 10a will be described. The output-side test signal selection circuit 10a selects any one of the plurality of external output terminals 14a based on the test selection signal 101, and the test input from the LSI tester 20 from the selected one external output terminal 14a. The signal 103 is output.

  The select circuit 21a, which is the first selector, selects the test input signal 103 from the test input signal 103 and the signal from the internal circuit by the test enable signal 102 input from the LSI tester 20, and supplies it to the tristate buffer 12. Output.

  The select circuit 21b selects the test selection signal 101 from among the test selection signal 101 and the signals from the internal circuit by the test enable signal 102 input from the LSI tester 20. Here, as described above, the test selection signal 101 is a signal for selecting only one of the plurality of external output terminals 14a, and only one of them is a high signal and the rest are low signals. The test selection signal 101 is input to the tristate buffer 12 as a tristate buffer enable signal 109. Among the tristate buffers 12 corresponding to the external output terminals 14a, the high test selection signal 101 is the tristate buffer enable signal 109. Only the tri-state buffer 12 input as can output the test input signal 103.

  When the test selection signal 101 is low, the output circuit is in the HiZ state, and the test input signal 103 is not output from the tristate buffer 12 to the external terminal 14a.

  The test input signal 103 output from the valid tristate buffer 12 is output to the test common line 11 via the external output terminal 14a. The test input signal 103 is input to the LSI tester 20 from the tester terminal 22 connected to the test common wiring 11, and the suitability of the LSI tester 20 can be observed.

  In this way, the test input signal 103 output from the LSI tester 20 to the LSI chip 1 via the tester terminal 25 can be observed by the LSI tester 20 via the test common wiring 11.

  Similarly, when a plurality of LSI chips are connected to the test common wiring 11, any one of the plurality of external output terminals 14a included in the plurality of LSI chips is selected and output from the selected one external output terminal 14a. The test input signal 103 thus obtained can be observed by the LSI tester 20 via the test common wiring 11.

  Next, a test method for the external input terminal 14b will be described. As in the test of the external output terminal 14a, the LSI tester 20 inputs the external reset signal 107 and the external test clock signal 108, which are control signals, to the LSI chip 1 via the tester terminals 23 and 24, respectively. Output to the test control circuit 19. The external reset signal 107 and the external test clock signal 108 are input to the counter circuit 34 via the external reset terminal 16 and the external test clock terminal 17, respectively.

  Further, the LSI tester 20 inputs a test output signal 104 from the tester terminal 22 to the external input terminal 14 b through the test common wiring 11.

  The counter circuit 34 outputs the count result 106 to the decode signal output circuit 33 by the same method as described above. The decode signal output circuit 33 also generates the test selection signal 110 for selecting any one of the test input signals input from the plurality of external input terminals 14b by the same method as described above, and the test result selection circuit 31. Output to.

  At this time, the decode signal output circuit 33 outputs the input switching signal 105 to the bidirectional buffer 32 and switches the bidirectional buffer 32 to the output side.

  Next, the operation of the input side test signal selection circuit 10b will be described. The test output signal 104 output from the LSI tester 20 is input to all external input terminals 14b through the test common wiring 11. The input side test signal selection circuit 10 b outputs the test output signal 104 to the internal circuit and the test result selection selector 31 of the test control circuit 19.

  The test result selection selector 31 receives the test output signals 104 from all the external input terminals 14 b, selects any one by the test result selection signal 110, and outputs it to the bidirectional buffer 32.

  Similar to the test selection signal 101, the test result selection signal 110 is a signal in which only a specific bit is high and the other bits are always 0. By this test result selection signal 110, the external test target is performed. Only the test output signal 104 at the input terminal 14b can be selected.

  The bidirectional buffer 32 outputs the received test output signal 104 to the tester terminal 25 via the external test input / output terminal 18.

  In this way, the test output signal 104 output from the LSI tester 20 via the test common wiring 11 can be observed by the LSI tester 20 via the tester terminal 25.

  Similarly, when a plurality of LSI chips are connected to the test common wiring 11, the tester inputs the test output signal 104 to all the external input terminals 14 b via the test common wiring 11. One external input terminal 14b is selected from the plurality of external input terminals 14b included in the plurality of LSI chips, and only the test output signal 104 via the selected one input terminal 14b is output to the external input / output terminal 18. The test output signal 104 can be observed by the LSI tester 20 via the external test input / output terminal 18.

  Note that the present invention is not limited to the above-described embodiment, and can be changed as appropriate without departing from the spirit of the present invention. For example, the counter circuit, which is a decoding circuit, and the decoding signal output circuit may be combined into one block, or the input terminal and the output terminal may be separated without using a bidirectional buffer.

DESCRIPTION OF SYMBOLS 1 LSI chip 10 Test signal selection circuit 10a Output side test signal selection circuit 10b Input side test signal selection circuit 11 Test common wiring 12 Tristate buffer 13 Input buffer 14 External terminal 14a External output terminal 14b External input terminal 16 External reset terminal 17 External Test clock terminal 18 External test input / output terminal 19 Test control circuit 20 LSI tester 21a selection circuit 21b selection circuit 22 tester terminal 23 tester terminal 24 tester terminal 25 tester terminal 31 test result selection circuit 32 bidirectional buffer 33 decode signal output circuit 34 counter Circuit 101 Test selection signal 102 Test enable signal 103 Test input signal 104 Test output signal 105 Input switching signal 106 Count result 107 External reset signal 108 Test clock signal 109 tristate buffer enable signal 110 test selection signal 201 LSI chip 202 test board 203 LSI tester 210 internal circuit 220 tristate buffer 230 input buffer 240 external output terminal 250 external input terminal 260 test circuit m1, m2, mm tester Terminal k1, k2 Tester terminal 500 LSI chip 503 LSI tester 510 Boundary scan register 520 External terminal 530 Tester terminal 540 Test wiring

Claims (9)

Internal circuitry,
A plurality of external terminals connected to the internal circuit;
A test method for a semiconductor integrated circuit, comprising a test circuit provided between the internal circuit and the plurality of external terminals, for testing the plurality of external terminals,
When the external terminal includes a plurality of external output terminals, the plurality of external terminals are connected to one common wiring connected to a tester,
The test circuit generates a selection signal by decoding a control signal from the tester, selects any one of the plurality of external output terminals by the selection signal,
A test signal is input from the tester, and the test signal is output to the common wiring from the selected one external output terminal,
A test method for a semiconductor integrated circuit, which tests a continuity of an external output terminal by observing a test signal output through the common wiring with a tester. Internal circuitry,
A plurality of external terminals connected to the internal circuit;
A test method for a semiconductor integrated circuit, comprising a test circuit provided between the internal circuit and the plurality of external terminals, for testing the plurality of external terminals,
When the external terminal includes a plurality of external input terminals, the plurality of external input terminals are connected to one common wiring connected to a tester,
The test signal output from the tester is input to the plurality of external input terminals via the common wiring,
Receiving a test signal output from a tester via the plurality of external input terminals;
The test circuit generates a selection signal by decoding a control signal from a tester, and selects one of the test signals input from the plurality of external input terminals by the selection signal,
A test method for a semiconductor integrated circuit, wherein the continuity of an external input terminal is tested by outputting the selected one test signal to the tester and observing the selected test signal. Internal circuitry,
A plurality of external terminals connected to the internal circuit;
A test method for a semiconductor integrated circuit, comprising a test circuit provided between the internal circuit and the plurality of external terminals, for testing the plurality of external terminals,
When the external terminal includes a plurality of external output terminals, the plurality of external terminals are connected to one common wiring connected to a tester,
The test circuit generates a selection signal by decoding a control signal from the tester, selects any one of the plurality of external output terminals by the selection signal,
A test signal is input from the tester, and the test signal is output from the selected one external output terminal to the common wiring.
The test signal output through the common wiring is observed with a tester,
When the external terminal includes a plurality of external input terminals, the plurality of external input terminals are connected to one common wiring connected to a tester,
The test signal output from the tester is input to the plurality of external input terminals via the common wiring,
Receiving a test signal output from a tester via the plurality of external input terminals;
The test circuit generates a selection signal by decoding a control signal from the tester, and selects one of the test signals input from the plurality of external input terminals by the selection signal,
A test method for a semiconductor integrated circuit, wherein the continuity of an external input terminal is tested by outputting the selected one test signal to the tester and observing the selected test signal. There are a plurality of the semiconductor integrated circuits,
The external terminals of each of the plurality of semiconductor integrated circuits are connected to one common wiring, and the test signal output from one external terminal or input to one external terminal is observed for external 4. The method for testing a semiconductor integrated circuit according to claim 1, wherein a terminal is tested. Internal circuitry,
A plurality of external terminals connected to the internal circuit;
A test circuit provided between the internal circuit and the plurality of external terminals, for testing the plurality of external terminals;
When the test circuit includes a plurality of external output terminals, the test circuit receives a control signal from the tester, decodes the control signal, and selects a selection signal for selecting any one of the plurality of external output terminals. A decoding circuit to generate,
A semiconductor integrated circuit comprising: a selection circuit that selects any one of the plurality of external output terminals based on the selection signal and outputs a test signal from the tester from the selected one of the external output terminals. Internal circuitry,
A plurality of external terminals connected to the internal circuit;
A test circuit provided between the internal circuit and the plurality of external terminals, for testing the plurality of external terminals;
When the external circuit includes a plurality of external input terminals, the test circuit receives a control signal from the tester, decodes the control signal, and inputs any one of the test signals input from the plurality of external input terminals. A decoding circuit for generating a selection signal for selecting
A selection circuit that receives a test signal input from the plurality of external input terminals, selects one of the test signals according to the selection signal, and outputs the selected signal to a tester; Internal circuitry,
A plurality of external terminals connected to the internal circuit;
A test circuit provided between the internal circuit and the plurality of external terminals, for testing the plurality of external terminals;
When the test circuit includes a plurality of external output terminals, the test circuit receives a control signal from the tester, decodes the control signal, and selects a selection signal for selecting any one of the plurality of external output terminals. When the external terminal includes a plurality of external input terminals, the control signal is received from the tester, and the control signal is decoded to select any one of the test signals input from the plurality of external input terminals A decoding circuit for generating a selection signal to be
Based on the selection signal, one of the plurality of external output terminals is selected, and a test signal input from the tester is output from the selected one external output terminal, or the plurality of external input terminals And a selection circuit that receives the test signal from the signal and selects one of the test signals according to the selection signal and outputs the selected signal to the tester. An output circuit provided in each of the external output terminals;
The selection circuit includes a first selector to which a signal from the internal circuit and the test signal are input, and a second selector to which a signal from the internal circuit and the selection signal are input.
The first selector selects the test signal according to a test enable signal input from a tester and outputs the selected test signal to an output circuit;
The second selector selects the selection signal according to the test enable signal and outputs the selection signal to the output circuit as an output circuit enable signal;
4. The semiconductor integrated circuit according to claim 1, wherein the output circuit is enabled by the output circuit enable signal and outputs the test signal. An input circuit provided in each of the external input terminals;
The selection circuit includes a third selector that receives the test signal input from the tester via the external input terminal,
4. The semiconductor integrated circuit according to claim 2, wherein the third selector selects a test signal from any one of the external input terminals according to the control signal and outputs the selected test signal to the tester.

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