1278948 凸塊之用的開口 6a，如第1E圖所示。然後，利用印刷方式， ，錫膏（solder paste) 7填入開口 6a中，如第ΐ]ρ圖所示。接 =對錫膏7進行回銲（reflQW)製程並去除光阻層6 ,以形成 V電凸塊8如第1G圖所示。藉此，係完成具有導電凸塊8之 晶圓結構9。 般來4，具有導電凸塊之晶圓結構（wa^r)或是經切割而 成的晶粒（die)，係應用於覆晶式構裝（Flip Chip in Package)。在 封裝的過程中，晶圓或是晶粒會被翻轉，而使得晶圓或是晶粒 φ上的導電凸塊與基板的接點相互連接。 然而，單一種類的導電凸塊材質無法滿足電路與結構上的 所有需求。例如是某些接點係用以接地，其相連的導電凸塊需 要可以瞬間導通大量電流。又例如是位於基板中央之接點，其 相連的導電凸塊需要足夠硬度以支撐晶粒。 【發明内容】 有鑑於此，本發明的目的就是在提供一種形成不同材質 導電凸塊的方法，可以根據不同的設計需求量身打造性能相 應的導電凸塊，提高關鍵元件品質。 b 根據本發明的目的，提出一種形成導電凸塊的方法，包 下列步驟。提供基板，基板具有—主動表面，主動表面且有 個銲墊。形成第一金屬層以及第二金屬層於主動表面，第一 屬層係覆蓋-第一部份之數個銲墊，第二金屬層係覆蓋第二 份之數個銲塾，第-金屬層係與第二金屬層電性絕緣。η 光阻層於第一金屬層以及第二金屬層上， y 開口以及數個第二開口 ’數個第一開口係暴心第一金= 並相對第-部分之數個銲塾，數個第二開口係、暴露二: 層，並相對第二部份之數個銲墊。電鍍一 一、 7 弟一導電材料於數 1278948· 第開口中。電鍍一第二導電材料於數個第二開口中。去除光 阻層。選擇性移除金屬層，以形成數個凸塊下金屬層。回銲數 個第導電材料以及第二導電材料，以形成數個第一導電凸塊 以及數個第二導電凸塊。 根據本發明的目的，再提出一種晶圓結構包括基板、數個 第一導電凸塊以及數個第二導電凸塊。基板具有一主動表面， 主動表面具有數個凸塊下金屬層。數個第一導電凸塊係形成於 部分之數個凸塊下金屬層上。數個第二導電凸塊係形成於另一 肇部份之數個凸塊下金屬層上。 為讓本發明之上述目的、特徵、和優點能更明顯易懂，下 文特舉一較佳實施例，並配合所附圖式，作詳細說明如下： 【實施方式】 本發明主要是提供一種形成不同材質之導電凸塊於同一基 板上的方法，係可於特定區域中形成特定材質的導電凸塊，以 符合電路佈局中之不同的電氣需求以及結構要求。以下係舉一 較佳實施例做詳細說明，然此較佳實施例僅為本發明之發明精 ®神下的一種實施方式，並不會對本發明之欲保護範圍進行限縮。 清參照第2圖’其緣示依照本發明一較佳實施例之形成不 同材質之導電凸塊之方法的流程圖。本實施例之形成不同材質 之導電凸塊之方法主要包括以下步驟Sl〇i〜siog。步驟si〇i， k供基板’基板具有主動表面’主動表面具有數個銲墊。步驟 S102’形成第一金屬層以及第二金屬層於主動表面，第一金屬 層係覆蓋第一部份之數個銲墊，第二金屬層係覆蓋第二部份之 數個鋅墊’第一金屬層係與第二金屬層電性絕緣。步驟S1 〇3， 形成一光阻層於第一金屬層以及第二金屬層上，光阻層具有數 個第一開口以及數個第二開口，數個第一開口係暴露出第一金 1278948 屬層，並相對第一部分之數個銲墊，數個第二開口係暴露出第 一金屬層，並相對第二部份之數個銲墊。步驟sl〇4，電鍍第一 導電材料於數個第一開口中。步驟S105，電鍍第二導電材料於 數個第二開口中。步驟S106，去除光阻層。步驟sl〇7，選擇性 移除金屬層，以形成數個凸塊下金屬層。步驟sl〇8，回銲數個 第一導電材料以及第二導電材料，以形成數個第一導電凸塊以 及數個第二導電凸塊。 第2Α〜2J圖繪示本發明之較佳實施例之形成不同材質^ Μ 導電凸塊的示意圖。為求圖面清楚易懂，在第2A〜2J圖示中 分複數7G件係僅以單一數量表示。以下係配合圖示針對步驟 S101〜s 108進行詳細的說明。 在步驟Sl〇1中，提供基板10，基板10具有主動表面主 動表面具有數個銲墊，如第3A圖所示。銲墊之材質通常為銅 或紹，藉以與外部電路形成電性連接。依其預定形成之導電凸 塊材質的不同’銲墊係區分為數個第一部分之鲜塾以及數個 第二部分之銲墊22。基板10可以是晶圓（wafer)或是晶片（die)。 步驟S102更包括以下步驟。首先，形成金屬層覆蓋主 =表面以及數個銲塾21及22，如第3B圖所示。例 電電鍵、⑽或其他物理化學沉積方式形成金屬層3q : 於金屬層30。第一光阻層例如是 ： :劑。接著，利用適當的方式，例如圖層移轉方式， 案化之第-光__，，選=二 ㈣的方式’並據以形成第一金屬層:S以及第 一，屬層302,第一金屬層3〇1係與第二金屬層如相隔一間⑧ 9 ,1278948 距。最後，移除圖案化之第一光阻層32。藉此，形成第一金屬 ，301以及第二金屬層3〇2於主動表面，第一金屬層3〇1係覆 蓋第一部份之數個銲墊21，第二金屬層3〇2係覆蓋第二部份之 數個銲墊22，第一金屬層301係與第二金屬層3〇2電性絕緣， 如第3D圖所示。 步驟S1G3更包括以下步驟。首先，形成光阻層4()於主動 表面上。光阻層例如是乾膜（Dry Film)或是液態光阻劑。之後， 利用適當的方式，例如圖層移轉方式，於光阻層上定義出開口， •選擇性移除光阻層40以形成數個第一開口 41、數個第一曝孔 43、數個第二開口 42以及數個第二曝孔44。請參照第3E圖， 數個第-開口 以及數個第一曝孔43係暴露出第一金屬層 301 ’且數個第一曝孔3〇1係位於基板1〇之邊緣。數個第二開 42以及數個第二曝孔44係暴露出第二金屬層，且數個 第=曝孔44係位於基板1〇之邊緣。藉此，數個第一開口 “係 暴路出第一金屬層3〇1，並相對第一部分之數個銲墊Μ，數個 第二開口 42係暴露出第二金屬層3〇2，並相對第二部份之數個 銲墊22。 步驟S1G4更包括以下步驟。首先，將基板浸泡於第一電鑛 液中，第-電鍍液係包含一第一導電材料。接著，將第一電極 透，數個第-曝孔43與第一金屬層3〇1電性連接。之後，通以 電机，第一導電材料50係附著於數個第一開口 41中之第一金 屬f 301上。藉助外加直流電的作用，在溶液中進行電解反應， 使得導電體，例如是第—金屬層，的表面沈積一金屬層或合金 /贫例如疋第—導電材料。藉此，第一導電材料5G係、電鑛於數 個第一開口 41中，如第3F圖所示。 步驟S105更包括以下步驟。首先，浸泡基板於第二電鑛液 .1278948 中第一電鑛液係包含第二導電材料。接著，將第二電極透過 數個第二曝孔44與第二金屬層3〇2電性連接。之後，通以電流， 第二導電材料60係附著於數個第二開口 44中之第二金屬層3〇2 上。藉助外加直流電的作用，在溶液中進行電解反應，使得導 電體，例如是第二金屬層，的表面沈積一金屬層或合金層，例 如是第二導電材料。藉此，第二導電材料6〇係電鍍於數個第二 開口 44中，如第3G圖所示。 在步驟S106中，去除光阻層40，如第3Η圖所示。 藝 在步驟S107中，利用第一導電材料5〇以及第二導電材料 60為遮罩，例如是利用濕蝕刻的方式，選擇性移除第一金屬層 301及第二金屬層3〇2，以形成數個凸塊下金屬層 Metallurgy Layer，UBM layer)35，如第 31 圖所示。凸塊下金屬 層 35 通常由黏著層（adhesion layer)、阻障層（barrierlayer) 與潤濕層所組成。黏著層可以提供銲墊及主動表面良好的黏著 性，其材質可為銘、鈥、鉻、鶴化鈦等。阻障層係用以防止導 電凸塊與銲塾之金屬互相擴散，其材質可為鎳釩、鎳等。潤濕 層係提通凸塊下金屬層24與導電凸塊之間良好之沾附性，其材 •質可為銅、鉬、鉑。 在步驟S108中，回銲（reflow)數個第一導電材料5〇以及第 二導電材料60，以形成數個第一導電凸塊55以及數個第二導 電凸塊65，如第3 J圖所示。藉此於基板上形成不同材質之導 電凸塊，以下係以具有不同材質之導電凸塊之晶圓結構作進一 步地說明。然而，熟悉此技藝者當可明瞭本發明所述之形成具 有不同材質之導電凸塊之方法亦可應用於電路基板、S y 曰 入 日日乃、晶 粒以及晶圓上。 請參照第2J圖，按照上述方法所形成之晶圓結構1〇〇包括 11 1278948 精神和範圍内，當可作各種之更動與潤飾，因此本發明之保護 乾圍當視後附之申請專利範圍所界定者為準。 【圖式簡單說明】 第1A〜1G圖繪示依照形成傳統具有導電凸塊之晶圓結構 之方法的示意圖 第2圖繪示依照本發明一較佳實施例之形成不同材質之導 電凸塊之方法的流程圖。 φ 第3A〜3了圖繪示本發明之較佳實施例之形成不同材質之 導電凸塊的示意圖。 【主要元件符號說明】 1 :基板 2 :銲墊 3 :導電層 4:圖案化光阻層 5:凸塊下金屬層 6 :光阻層 7 :錫膏 8 :導電凸塊 9 :晶圓結構 10 :基板 21 :第一部分之銲墊 22:第二部分之桿墊 30 :金屬層 301 :第一金屬層 302·第二金屬層 13 12789481278948 The opening 6a for the bump is as shown in Fig. 1E. Then, by means of printing, a solder paste 7 is filled in the opening 6a as shown in Fig. ρ. Next, the solder paste 7 is subjected to a reflow (reflQW) process and the photoresist layer 6 is removed to form a V-electrode bump 8 as shown in FIG. 1G. Thereby, the wafer structure 9 having the conductive bumps 8 is completed. Generally, a wafer structure having conductive bumps or a die formed by cutting is applied to a Flip Chip in Package. During the packaging process, the wafer or the die is flipped so that the conductive bumps on the wafer or die φ are connected to the contacts of the substrate. However, a single type of conductive bump material does not meet all of the circuit and structural requirements. For example, some contacts are used for grounding, and the connected conductive bumps need to be able to conduct a large amount of current instantaneously. Another example is the contact at the center of the substrate, and the connected conductive bumps need to be sufficiently rigid to support the die. SUMMARY OF THE INVENTION In view of the above, an object of the present invention is to provide a method for forming conductive bumps of different materials, which can be tailored to different performance requirements to improve the quality of key components. b In accordance with the purpose of the present invention, a method of forming a conductive bump is provided, which comprises the following steps. A substrate is provided having an active surface, an active surface and a pad. Forming a first metal layer and a second metal layer on the active surface, the first metal layer covering the first portion of the plurality of pads, the second metal layer covering the second plurality of solder bumps, the first metal layer It is electrically insulated from the second metal layer. The η photoresist layer is on the first metal layer and the second metal layer, the y opening and the plurality of second openings 'a plurality of first openings are violent first gold = and several solder bumps relative to the first portion, and several The second opening system exposes two layers and is opposite to the second portion of the plurality of pads. Electroplating one, seven brothers and one conductive material in the number 1278948 · opening. A second conductive material is electroplated in the plurality of second openings. Remove the photoresist layer. The metal layer is selectively removed to form a plurality of under bump metal layers. A plurality of first conductive materials and a second conductive material are reflowed to form a plurality of first conductive bumps and a plurality of second conductive bumps. According to another aspect of the present invention, a wafer structure includes a substrate, a plurality of first conductive bumps, and a plurality of second conductive bumps. The substrate has an active surface, and the active surface has a plurality of under bump metal layers. A plurality of first conductive bumps are formed on a portion of the plurality of under bump metal layers. A plurality of second conductive bumps are formed on the plurality of under bump metal layers of the other germanium portion. The above described objects, features, and advantages of the present invention will become more apparent and understood. The method of forming conductive bumps of different materials on the same substrate can form conductive bumps of specific materials in specific regions to meet different electrical requirements and structural requirements in the circuit layout. The preferred embodiment is described in detail below. However, the preferred embodiment is merely an embodiment of the invention, and does not limit the scope of protection of the present invention. 2 is a flow chart showing a method of forming conductive bumps of different materials in accordance with a preferred embodiment of the present invention. The method for forming the conductive bumps of different materials in the embodiment mainly includes the following steps S1i to Siog. Step si〇i, k for the substrate 'substrate having an active surface' The active surface has a plurality of pads. Step S102' forms a first metal layer and a second metal layer on the active surface, the first metal layer covers a plurality of pads of the first portion, and the second metal layer covers the plurality of zinc pads of the second portion. A metal layer is electrically insulated from the second metal layer. Step S1 〇3, forming a photoresist layer on the first metal layer and the second metal layer, the photoresist layer has a plurality of first openings and a plurality of second openings, and the plurality of first openings expose the first gold 1278948 The genus layer is opposite to the first portion of the plurality of pads, and the plurality of second openings expose the first metal layer and are opposite to the second portion of the plurality of pads. Step s1〇4, electroplating the first conductive material into the plurality of first openings. In step S105, the second conductive material is plated in the plurality of second openings. In step S106, the photoresist layer is removed. Step s1〇7, selectively removing the metal layer to form a plurality of under bump metal layers. Step s1〇8, a plurality of first conductive materials and a second conductive material are reflowed to form a plurality of first conductive bumps and a plurality of second conductive bumps. 2 to 2J are schematic views showing the formation of different materials 导电 conductive bumps in accordance with a preferred embodiment of the present invention. In order to make the drawing clear and easy to understand, in the 2A to 2J diagrams, the plural 7G parts are represented by a single number. The steps S101 to s108 will be described in detail below with reference to the drawings. In the step S1, a substrate 10 is provided which has an active surface active surface having a plurality of pads as shown in Fig. 3A. The pad is usually made of copper or copper to form an electrical connection with an external circuit. The solder pads are divided into a plurality of first portions of fresh solder and a plurality of second portions of solder pads 22 according to the predetermined conductive bump material. The substrate 10 can be a wafer or a die. Step S102 further includes the following steps. First, a metal layer is formed to cover the main = surface and a plurality of solder fillets 21 and 22, as shown in FIG. 3B. The metal layer 3q is formed on the metal layer 30 by way of an electric key, (10) or other physicochemical deposition. The first photoresist layer is, for example, a :: agent. Then, using a suitable method, such as layer transfer mode, the method of the first light __, select = two (four) 'and according to the formation of the first metal layer: S and the first, genus layer 302, first The metal layer 3〇1 is separated from the second metal layer by a distance of 8 9 and 1278948. Finally, the patterned first photoresist layer 32 is removed. Thereby, the first metal, 301 and the second metal layer 3〇2 are formed on the active surface, the first metal layer 3〇1 covers the plurality of pads 21 of the first portion, and the second metal layer 3〇2 covers The second portion of the plurality of pads 22, the first metal layer 301 is electrically insulated from the second metal layer 3〇2, as shown in FIG. 3D. Step S1G3 further includes the following steps. First, a photoresist layer 4 is formed on the active surface. The photoresist layer is, for example, a dry film or a liquid photoresist. Thereafter, an opening is defined on the photoresist layer by an appropriate method, such as layer transfer mode, and the photoresist layer 40 is selectively removed to form a plurality of first openings 41, a plurality of first exposure holes 43, and a plurality of The second opening 42 and the plurality of second exposure holes 44. Referring to FIG. 3E, a plurality of first openings and a plurality of first exposure holes 43 expose the first metal layer 301 ' and a plurality of first exposure holes 3 〇 1 are located at the edge of the substrate 1 . The plurality of second openings 42 and the plurality of second exposure holes 44 expose the second metal layer, and the plurality of first exposure holes 44 are located at the edge of the substrate 1〇. Thereby, the plurality of first openings "exaceate the first metal layer 3〇1 and are opposite to the first portion of the plurality of pads Μ, and the plurality of second openings 42 expose the second metal layer 3〇2, and The step S1G4 further includes the following steps. First, the substrate is immersed in the first electric ore liquid, and the first plating solution comprises a first conductive material. Then, the first electrode is A plurality of first-exposure holes 43 are electrically connected to the first metal layer 3〇1. Thereafter, the first conductive material 50 is attached to the first metal f 301 of the plurality of first openings 41 by a motor. The electrolytic reaction is carried out in the solution by the action of external direct current, so that a surface of the electric conductor, for example, the first metal layer, is deposited with a metal layer or an alloy/poor, for example, a first conductive material. Thereby, the first conductive material 5G And the electric ore is in the plurality of first openings 41, as shown in Fig. 3F. Step S105 further comprises the following steps. First, the substrate is immersed in the second electric ore liquid. 1278948, the first electric ore liquid system comprises the second conductive Next, the second electrode is passed through the plurality of second exposure holes 44 and the second The genus layer 3〇2 is electrically connected. Thereafter, a current is applied, and the second conductive material 60 is attached to the second metal layer 3〇2 of the plurality of second openings 44. The solution is carried out in the solution by the action of external direct current. The electrolytic reaction causes a surface of the electrical conductor, such as the second metal layer, to deposit a metal layer or an alloy layer, such as a second conductive material. Thereby, the second conductive material 6 is plated in the plurality of second openings 44. As shown in Fig. 3G, in step S106, the photoresist layer 40 is removed, as shown in Fig. 3. In step S107, the first conductive material 5? and the second conductive material 60 are used as a mask, for example. The first metal layer 301 and the second metal layer 3〇2 are selectively removed by wet etching to form a plurality of under bump metal layer Metallurgy Layer (UBM layer) 35, as shown in FIG. The under-metal layer 35 is usually composed of an adhesion layer, a barrier layer and a wetting layer. The adhesive layer can provide good adhesion to the bonding pad and the active surface, and the material can be inscription, bismuth and chromium. , crane titanium, etc. barrier layer is used to prevent The conductive bump and the metal of the solder joint mutually diffuse, and the material thereof may be nickel vanadium, nickel, etc. The wetting layer improves the adhesion between the metal layer 24 under the bump and the conductive bump, and the material and quality thereof can be It is copper, molybdenum, platinum. In step S108, a plurality of first conductive materials 5 〇 and a second conductive material 60 are reflowed to form a plurality of first conductive bumps 55 and a plurality of second conductive bumps. 65, as shown in FIG. 3 J. Thereby, conductive bumps of different materials are formed on the substrate, and the following is further described by a wafer structure having conductive bumps of different materials. However, those skilled in the art can It is to be understood that the method of forming conductive bumps having different materials according to the present invention can also be applied to a circuit substrate, a sin, a die, a die, and a wafer. Please refer to FIG. 2J, the wafer structure 1 formed according to the above method includes the spirit and scope of 11 1278948, and when various modifications and retouchings can be made, the protection scope of the present invention is attached to the patent application scope. The definition is final. BRIEF DESCRIPTION OF THE DRAWINGS FIGS. 1A to 1G are schematic views showing a method of forming a conventional wafer structure having conductive bumps. FIG. 2 is a view showing formation of conductive bumps of different materials according to a preferred embodiment of the present invention. Flow chart of the method. φ 3A to 3 are schematic views showing the formation of conductive bumps of different materials in accordance with a preferred embodiment of the present invention. [Main component symbol description] 1 : Substrate 2 : Solder pad 3 : Conductive layer 4 : Patterned photoresist layer 5 : Under bump metal layer 6 : Photoresist layer 7 : Solder paste 8 : Conductive bump 9 : Wafer structure 10: substrate 21: first portion of the pad 22: second portion of the pad 30: metal layer 301: first metal layer 302 · second metal layer 13 1278948
32 ： 第 一光阻層 35 ： 凸塊下金屬層 40 ： 光阻層 41 ： 第 一開口 42 ： 第 二開口 43 ： 第 一曝孔 44 ： 第 二曝孔 50 ： 第 一導電材料 55 ： 第 一導電凸塊 60 ·· 第 二導電材料 65 ： 第 二導電凸塊32: first photoresist layer 35: under bump metal layer 40: photoresist layer 41: first opening 42: second opening 43: first exposure hole 44: second exposure hole 50: first conductive material 55: a conductive bump 60 · · a second conductive material 65 : a second conductive bump