I2781fi^4tw,doc/r 九、發明說明： 【發明所屬之技術領域】 本發明是有關於一種半導體記憶體元件，且特別是有 關於一種動態隨機存取記憶體的製造方法及其陣列。 【先前技術】 隨著元件之尺寸曰漸縮小，現在高積集度的半導體元 件，例如動態隨機存取記憶體(Dynamic Random Access Memory，DRAM)，常採用絕緣層上有矽（SiUc〇n 〇n Insulator，SOI)元件之設計。這是因為絕緣層上有矽元件 具有低漏電流(Leakage Current)、低起始電壓(Thresh〇ldI2781fi^4tw, doc/r IX. Description of the Invention: [Technical Field] The present invention relates to a semiconductor memory device, and more particularly to a method of fabricating a dynamic random access memory and an array thereof. [Prior Art] As the size of components is gradually shrinking, high-integration semiconductor components, such as dynamic random access memory (DRAM), are often used on the insulating layer (SiUc〇n 〇 n Insulator, SOI) component design. This is because the germanium element on the insulating layer has low leakage current (Leakage Current) and low initial voltage (Thresh〇ld
Voltage，VT)與低寄生電容(parasitic Capacitance)等優點， 故能夠減少耗電、減少元件錯誤，以及增加元件操作速率 (Performance) 〇 圖1為繪示習知一種絕緣層上有矽元件之剖面示意 圖。 凊參照圖1，SOI元件是在基底石夕材表面的不遠處， 增加一層絕緣層102(—般為二氧化石夕層），讓用以製作半導 體元件的石夕主體104與矽基底1〇〇之間，以這一層絕緣層 102加以隔開。然後，在矽主體104中形成淺摻雜區1〇/、 源極/汲極區108，以及基體(Body)區110，並在矽主體1〇4 上形成一閘極結構112。 & 然而，一般SOI元件最大的問題是有浮置基體效應 (Floating Body Effect)產生。所謂的浮置基體效應是指，在 SOI元件中，基體區因絕緣層的隔絕，而無法經由矽基底 5 1278100 d〇c/r 16684twf. 接地’因而成為浮置(Floating)基體區，其存在會影響元件 的可靠度與穩定性，且會造成漏電流。 目前在半導體領域中，通常是採用額外的導體層來形 成基體接觸(Body Contact)，如此便可將電荷由基體區排 出’以消除浮置基體效應的不良影響。 在文獻上有幾種製作半導體元件之基體接觸的方 法。特別是，C· J· Radens等人於美國專利第6,437,388 B1 號(U.S· pat· Νο· 6,437,388 B1)提出一種具有基體接觸之 溝渠式電容記憶胞。圖2為繪示習知一種具有基體接觸之 溝渠式電容記憶胞之剖面示意圖。圖3為繪示圖2之溝渠 式電谷記憶胞陣列之上視示意圖。請參照圖2與圖3，半 導體元件10，例如是DRAM，其包括一基底14、一深溝 渠式電容器11、一垂直式電晶體52、一基體接觸48、一 字元線72、一位元線82以及一接觸窗78。其中，基底14 具有一主動區90，且基底14中具有深溝渠12。另外，基 體接觸48係配置接觸窗78下方，以及位於二主動區9〇 之間，且電性連接二主動區90與基底14。但是，專利第 6,437,388 B1號仍具有一些問題存在，舉例來說，其會有 製程窗(process window)、元件阻值太高以及汲極電流(地) 明顯不夠等問題。 另外，U.Gruening等人於美國專利第6,593,612扣號 (U.S· Pat· No· 6,593,612 B2)中提出一種垂直電晶體之^ 體接觸的形成方法與結構。L· Forbes等人亦於美國專利第 6,537,871 B2 號(U.S· Pat· No· 6,537,871 B2)中提出一種具 6 I278iaQtw,0C/r 有垂直電晶體和溝渠式電容器之開放式位元線的形成方 ^同樣地’由於上述專利僅具有單邊的字元線，因此會 存在有汲極電流(1办)明顯不夠等問題。 s而且’賴上述的方法皆可消除浮置基體效應，但 疋所形成的基體接觸會佔Μ件的使用面積，造成元件的 低。此外’上述專利中之元件的製程皆相當繁複， 會棱南製程成本。 【發明内容】 本么明的目m在提供—種誠_存取記憶體 隹5夠降低基體接觸在晶片上的使用面積’提高元 可财2倍的汲極電流，提高元件的電流 驅動力。 的制、ίί、Γ的另—目的是提供—種動態隨機存取記憶體 ^方法’能夠以易之製程製造基體接觸，以避免浮 置基底效應。 -種動减機存取記紐之卩㈣，其包括 :、、'巴緣層上树基底、錄個記鮮元、錄條基體線、 多數條字元線以及多數條位a & ^ ^ 、、' 鮮μ > 碰。錄個記憶單元係配置 奸1層t 底上，且以行與列之方式排列，每一個 汲^區;㈣基餘讀料第一源極/ 導體检^ f ί t _及極區’二閘極結構配置於半 版柱狀4之相對應的二側壁，而閘極介電層配置於半 1278100 16684twf.doc/r ‘體柱狀結淑二祕結構 方，電容器包括第-電極，配置配f於電晶體下 飯京m卜…r~ 呢置於+導體柱狀結構下，曰 共弟源極/汲極區接合、第二電極 ：下且 構旁以及電容介電層，配置 黛'^肢柱狀結 另外，多數條基體線係平行配置“極極之間。 並串二。多:條位元線與字元線垂直， 電性連接。，且與電晶體的第二源極/沒極區 依，本發明的實施例所述，上述 體層，導體層的材質例如是摻雜 二如疋-導 物或P型金屬。 杜.一、完全金屬石夕化合 依妝本發明的實施例所述，上 — 係低於半導體柱狀結構_面。、之—閘極結構的頂面 依照本發明的實施例所述，上 第二源極/汲極區例如是具有—第 及極區與 區例如是具有一第二導電型態4層 態為N型，第二導電型態為p型。，、中導電型 依照本發明的實施例所述，上述之帝 第二源極/汲極區之材質相同，第二電_如=導^與 依照本發明的實施例所述，上述之動熊六。 體陣列係為4F2之記憶體陣列。 現、子取圮憶 本發明另提出一種動態隨機存取記憶體的製造方 1278 100 16684twf.doc/r Ϊ包:一絕緣層上有矽基底，絕緣層上有矽基底依 4夕基底、絕緣層與具有第一導電型能之當一々爲 :::緣⑽形成具;第-導视態 〃有弟—¥電财之第三發層、具有第-導 您之弟四矽層，以及已圖案化· :第一=fi:移除部分第叫 接著，於第::夕：H’ 暴露出絕緣層表面。 形成第一介電运:石运、第二石夕層與第四石夕層側壁 部分第一介頁;;=二：層的頂面高度。之後，移除 體層的頂面古〗_ 電層的頂面高度等於第-導 曰㈣面呵度。繼之， 步中 序形成第二介電層、基體層與第：介二弟2電層上依 電層上依序形罩幕層與第三介 係沿列方向形成於對應第一罩阻】’其中光 見度小於第一罩篡展夕命危1 9上方’且光阻層之 除部第二罩幕層與;心:罩：:為罩幕，移 移除未被光;J與;士罩^^ =、部分基體層與部分第二介二第三介 ί:;::介電層頂面，然後移除光4 ir第—導 層之頂面低於第二;=;電層’其中第四介電 貝甶&後，於第四石夕層、第三 u78m ：4twf.d〇c/r 石夕層及部分第二@層之側 二介電層之表面形成第五介略電層、基體層與第 第二導體層。 电5，於苐五介電層表面形成 第四介電層上形成上述之製造方法更包括於 罩幕層、第五介電声以及笛!層’覆蓋第二罩幕層、第-幕層、第—罩幕層:八:導體層。然後’移除第二罩 出第四石夕層表面。θ接著，'^第^層與部分第六介電層至暴露 且第三導體層與第 、秒層上形成-第三導體層’ 成前，更包括移除部分第_^1另=於，介電層形 低於第四發層之頂面，其怜^日’使弟4體層之頂面 如是進行一 钱刻製程i 除部分第二導體層的方法例 物或Ρ型金屬。另外，基 夕广梦、完全金屬梦化合 沈積法。 g々形成方法例如是化學氣相 朗本發明的實施例所 型’第二導電型態為ρ型。上述之弟-V電型態為Ν —電;=明的實施例所述’上述之第一介電層例如是 依照本發明的實施例所述， 一閘極介電層。 现之弟五介電層例如是 元件觸’叫能夠消除 基^應，及其衍生的種種問題。而且，因為 I2781l 基體線係以串接的方式平行形成於二電晶體之間，所以可 較習知更為節省元件的使用面積，提高元件的積集度。此 外三本發明之電晶體具有二通道區，因此其汲極電流(Ids) 為單通道區之電晶體的2倍，如此一來可提高元件的電流 驅動力。另一方面，本發明所使用之製程皆為一般半導體 製程中所熟知之技藝，因此在製作上較為簡單不複雜，如 此可較為郎省製程之成本。 # 為讓本發明之上述和其他目的、特徵和優點能更明顯 易懂，下文特舉實施例，並配合所附圖式，做詳細說明如 下。 ， 【實施方式】 _ X® 4為依照本發明實施例所繪示之動態隨機存取記憶 體之陣列的佈局上視圖。圖5(a)所繪示為圖4沿a_a，方向 之剖面示意圖，圖5(b)所繪示為圖4沿B-B，方向之剖面示 意圖。 口 " 請同時參照目4、目5⑻與圖5(b)，本發明之動態隨 取記憶體陣列包括絕緣層上有矽基底500、多數個記 憶單元502、多數條基體線5〇4、多數條字元線5〇6以及多 數條位元線508。 其中，記憶單元502配置於絕緣層上有矽基底5〇〇 ^，且以行與列之方式排列，每一記憶單元5〇2包括一電 晶體510與-電容器512。電晶體51〇係由源極/沒極區 514、源極/汲極區516、基體區518、閘極介電層及二 閘極結構522所構成。源極/汲極區516配置於源極/沒極 11 1278100 16684twf.doc/rVoltage, VT) and low parasitic capacitance, which can reduce power consumption, reduce component errors, and increase component operating speed. Figure 1 shows a cross-section of a germanium component on an insulating layer. schematic diagram. Referring to FIG. 1, the SOI element is located not far from the surface of the base stone, and an insulating layer 102 (generally a layer of SiO2) is added to allow the Si Xi body 104 and the base 1 to be used for fabricating the semiconductor component. Between the turns, the insulating layer 102 is separated by this layer. Then, a shallow doped region 1/, a source/drain region 108, and a body region 110 are formed in the crucible body 104, and a gate structure 112 is formed on the crucible body 1〇4. & However, the biggest problem with general SOI components is the floating body effect. The so-called floating matrix effect means that in the SOI element, the substrate region cannot be grounded via the germanium substrate 5 1278100 d〇c/r 16684twf. due to the isolation of the insulating layer, thus becoming a floating substrate region, which exists It will affect the reliability and stability of the component and will cause leakage current. In the semiconductor field, it is common to use an additional conductor layer to form a body contact so that charge can be discharged from the substrate region to eliminate the adverse effects of the floating matrix effect. There are several methods of making substrate contact for semiconductor components in the literature. In particular, a ditch-type capacitive memory cell having a matrix contact is proposed by U.S. Patent No. 6,437,388 B1 (U.S. Pat. Ν ο. 6, 437, 388 B1). 2 is a schematic cross-sectional view showing a conventional trench-type capacitor memory cell having a substrate contact. 3 is a top plan view of the trench-type electric valley memory cell array of FIG. 2. Referring to FIGS. 2 and 3, the semiconductor component 10, such as a DRAM, includes a substrate 14, a deep trench capacitor 11, a vertical transistor 52, a substrate contact 48, a word line 72, and a bit cell. Line 82 and a contact window 78. The substrate 14 has an active region 90 and a deep trench 12 in the substrate 14. In addition, the substrate contact 48 is disposed under the contact window 78 and between the two active regions 9A, and electrically connects the two active regions 90 with the substrate 14. However, Patent No. 6,437,388 B1 still has some problems, for example, it has problems such as a process window, a high resistance of the element, and a significant insufficient current (ground). In U.S. Patent No. 6,593,612 (U.S. Pat. No. 6,593,612 B2), a method and structure for forming a body contact of a vertical transistor is proposed. L. Forbes et al., U.S. Patent No. 6,537,871 B2 (U.S. Pat. No. 6,537,871 B2), the disclosure of which is incorporated herein by reference. ^ Similarly, since the above patents only have single-sided word lines, there is a problem that the bungee current (1) is obviously insufficient. s and the above methods can eliminate the floating matrix effect, but the contact of the substrate formed by 疋 will occupy the use area of the component, resulting in low component. In addition, the manufacturing process of the components in the above patents is quite complicated and will cost the process. SUMMARY OF THE INVENTION The object of the present invention is to provide a kind of 诚 _ access memory 隹 5 to reduce the use area of the substrate contact on the wafer 'to increase the potential of 2 times the bungee current, improve the current driving force of the component . The purpose of the system is to provide a dynamic random access memory method that enables substrate contact to be made in an easy process to avoid floating substrate effects. - 种 减 存取 存取 存取 卩 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四^,, 'Fresh μ > Touch. Recording a memory unit is arranged on the bottom of a layer of t, and arranged in rows and columns, each 汲 ^ area; (4) base reading material first source / conductor inspection ^ f ί t _ and polar region 'two The gate structure is disposed on the corresponding two sidewalls of the half-plate column 4, and the gate dielectric layer is disposed on the half 1278100 16684twf.doc/r 'body columnar junction structure, the capacitor includes the first electrode, and the configuration With f in the crystal under the rice jing b...r~ is placed under the +conductor columnar structure, the 曰 弟 源 source/drain region bonding, the second electrode: the lower and the side and the capacitor dielectric layer, configuration 黛 ' ^ Limb columnar knots In addition, most of the matrix lines are arranged in parallel "between the poles. The string is two. More: the strip line is perpendicular to the word line, electrically connected. And with the second source of the transistor / In the embodiment of the present invention, the body layer and the material of the conductor layer are, for example, doped with a ruthenium-conductor or a P-type metal. Du. I. Complete metal shi yi huayi For example, the upper-layer is lower than the semiconductor columnar structure. The top surface of the gate structure is in accordance with an embodiment of the present invention. The upper second source/drain region has, for example, a -pole region and a region, for example, having a second conductivity type, the layer state is N-type, and the second conductivity type is p-type. According to the embodiment of the present invention, the second source/drain region of the above-mentioned emperor is made of the same material, and the second electric device is the same as the embodiment of the present invention. It is a memory array of 4F2. Now, the present invention also proposes a manufacturer of dynamic random access memory 1278 100 16684twf.doc/r package: an insulating layer has a germanium substrate, and the insulating layer has The base layer of the base layer, the insulating layer and the first conductivity type are::: edge (10) is formed; the first guide state has a younger brother - the third layer of electricity, with a first guide Your brother's four layers, as well as patterned: First = fi: Remove part of the first call, then: ::: H: expose the surface of the insulation layer. Form the first dielectric: stone transport, the first The second layer of the second stone layer and the fourth stone layer side wall;; = two: the top surface height of the layer. After that, the top surface of the body layer is removed _ the top surface of the electric layer The degree is equal to the first-to-fourth (fourth) surface degree. Then, the second dielectric layer, the base layer and the second dielectric layer are formed in the step by step, and the mask layer and the third layer are sequentially formed on the electric layer. The system is formed along the column direction in the corresponding first mask resistance], wherein the visibility is smaller than the first mask, and the second mask layer is removed from the photoresist layer; Mask, remove and remove light; J and; hood ^^ =, part of the base layer and part of the second second and third third ί:;:: the top surface of the dielectric layer, and then remove the light 4 ir - The top surface of the conductive layer is lower than the second; =; the electric layer 'the fourth dielectric shellfish & the fourth layer, the third u78m: 4twf.d〇c/r Shi Xi layer and part of the A fifth dielectric layer, a base layer and a second conductor layer are formed on the surface of the two dielectric layers on the side of the second layer. The manufacturing method for forming the fourth dielectric layer on the surface of the dielectric layer is further included in the mask layer, the fifth dielectric sound, and the flute layer to cover the second mask layer and the first layer. , the first cover layer: eight: conductor layer. Then 'removal the second cover to the surface of the fourth layer. θ, then, the ^^ layer and a portion of the sixth dielectric layer are exposed and the third conductor layer and the third layer are formed on the second and second layers, and the portion including the removed portion is further removed. The dielectric layer is lower than the top surface of the fourth layer, and the top surface of the body layer is such that the top surface of the body layer is subjected to a method of engraving i or a part of the second conductor layer. In addition, the foundation is full of dreams and complete metal dreams. The g々 formation method is, for example, a chemical vapor phase of the embodiment of the invention. The second conductivity type is a p-type. The above-described first-dielectric layer is, for example, a first dielectric layer as described in the embodiment of the present invention, a gate dielectric layer. The current five-dielectric layer is, for example, a component that can eliminate the basic response and its various problems. Moreover, since the I2781l base line is formed in parallel between the two transistors in a series connection, it is more practical to save the use area of the components and improve the integration of the elements. In addition, the transistor of the three inventions has a two-channel region, so that the drain current (Ids) is twice that of the transistor in the single-channel region, thereby increasing the current driving force of the device. On the other hand, the processes used in the present invention are all well-known in the general semiconductor process, and therefore are relatively simple and uncomplicated in production, so that the cost of the process can be relatively high. The above and other objects, features, and advantages of the present invention will become more apparent from the aspects of the appended claims. [Embodiment] _X® 4 is a layout top view of an array of dynamic random access memories according to an embodiment of the present invention. Fig. 5(a) is a cross-sectional view taken along line a-a of Fig. 4, and Fig. 5(b) is a cross-sectional view along line B-B of Fig. 4. Please refer to item 4, item 5 (8) and FIG. 5 (b) at the same time. The dynamic memory array of the present invention includes a germanium substrate 500 on the insulating layer, a plurality of memory cells 502, and a plurality of base lines 5〇4. A majority of the word line 5 〇 6 and a plurality of bit lines 508. The memory unit 502 is disposed on the insulating layer with a germanium substrate 5〇〇 and arranged in rows and columns. Each memory unit 5〇2 includes a transistor 510 and a capacitor 512. The transistor 51 is composed of a source/drain region 514, a source/drain region 516, a substrate region 518, a gate dielectric layer, and a gate structure 522. Source/drain region 516 is configured at source/no-pole 11 1278100 16684twf.doc/r
區514下方，基體區518配置於源極/汲極區514與源極/ 汲極區516之間，而源極/汲極區514、基體區518與源極 /汲極區516係構成一半導體柱狀結構524。其中，源極/ ，極區514例如是具有N型導電型態之矽層，基體區例如 疋具有p型導電型態之矽層，源極/汲極區516例如是具有 N型導電型態之料。二閘極結構522配置於半導體柱狀 結構524之相對應的二側壁，間極介電層52〇配置於半導 體柱狀結構524及二閘極結構522之間。 、在貝鈿例中，二閘極結構522的頂面係低於半導體 柱狀、、、口構524的了貞面，如此可避免位元線因製程誤差 522產生不正常的電性連接’進而使元件發 生短路或失效等問題。 電容器512配置於電晶體训下方’其包括電 也谷介電層528與電極53〇。其中，電極 有N型；IS，汲極區516之材質相同，其例如是具 524旁別配置於半導體柱狀結構 石夕、完全1=1，是導體層’其材質例如是換雜多晶 如是例如是氧切與^極別之間，其材質例 等介電材料。 I化石夕、乳化石夕復化石夕/氧化石夕(ΟΝΟ) 12 1278100 16684twf.d〇c/r ，線504係電性連接基體區518。其中，基體線5〇4例如 是導體層，導體層的材質例如是摻雜多晶石夕、完全金屬石夕 、匕s物或P型金屬專導體材料。字元線Mg與基體線504 平行，且每一條字元線5恥係與位於同一列上之電晶體51〇 的二閘極結構522接合，字元線例如是一導體層。另外， =兀線508與字元線506呈垂直配置，並串聯同一行上之 電晶體510，且位元線508與電晶體5丨〇的源極/汲極區5工4 ⑩ 電性連接，位元線例如是一導體層。由圖4之佈局可知， 本發明之動態隨機存取記憶體陣列可例如是一 4护之記憶 體陣列。 接下來，係說明本發明之動態隨機存取記憶體的製造 方法。 圖6至圖12為依照本發明實施例所繪示之動態隨機 存取圮憶體的製造流程的示意圖，其中子圖（a)係繪示上視 示意圖，子圖(b)係繪示沿剖面線，之剖面示意圖，子圖 (c)係繪示沿剖面線π-π，之剖面示意圖。 ⑩ 首先，請同時參照圖6(a)與圖6(b)，提供一個絕緣層Below the region 514, the base region 518 is disposed between the source/drain region 514 and the source/drain region 516, and the source/drain region 514, the base region 518, and the source/drain region 516 form a Semiconductor columnar structure 524. The source/polar region 514 is, for example, a germanium layer having an N-type conductivity type, the base region such as germanium having a p-type conductivity type germanium layer, and the source/drain region 516 having, for example, an N-type conductivity type. The material. The two gate structures 522 are disposed on the corresponding two sidewalls of the semiconductor pillar structure 524, and the interposer dielectric layer 52 is disposed between the semiconductor pillar structure 524 and the two gate structures 522. In the case of the Bellows, the top surface of the two-gate structure 522 is lower than that of the semiconductor columnar shape and the mouth structure 524, so that the abnormality of the bit line due to the process error 522 can be avoided. In turn, the component is short-circuited or failed. Capacitor 512 is disposed below the transistor train, which includes an electrical valley dielectric layer 528 and an electrode 53A. Wherein, the electrode has an N-type; the IS and the drain region 516 have the same material, for example, the 524 is disposed adjacent to the semiconductor columnar structure, and is completely 1=1, which is a conductor layer, and the material thereof is, for example, a hetero-polycrystal. For example, it is a dielectric material such as an oxygen-cut and a-electrode. I fossil eve, emulsified stone eve eve fossil eve / oxidized stone ΟΝΟ (ΟΝΟ) 12 1278100 16684twf.d 〇 c / r, line 504 is electrically connected to the base region 518. The base line 5〇4 is, for example, a conductor layer, and the material of the conductor layer is, for example, a doped polycrystalline stone, a full metal stellite, a bismuth material or a P-type metal specific conductor material. The word line Mg is parallel to the base line 504, and each word line 5 is spliced to the two gate structures 522 of the transistor 51A on the same column, for example, a conductor layer. In addition, the =兀 line 508 and the word line 506 are vertically arranged, and the transistors 510 on the same row are connected in series, and the bit line 508 is electrically connected to the source/drain region 5 of the transistor 5? The bit line is, for example, a conductor layer. As can be seen from the layout of Fig. 4, the dynamic random access memory array of the present invention can be, for example, a memory array. Next, a method of manufacturing the dynamic random access memory of the present invention will be described. 6 to FIG. 12 are schematic diagrams showing a manufacturing flow of a dynamic random access memory according to an embodiment of the present invention, wherein sub-picture (a) is a top view and sub-picture (b) is a The section line, the section diagram, and the subgraph (c) show the section along the section line π-π. 10 First, please refer to Figure 6(a) and Figure 6(b) together to provide an insulation layer.
上有矽(Silicon On Insulator，SOI)基底 400，其例如是一 N 型基底。此SOI基底400中具有一層絕緣層402，而絕緣 層402將SOI基底400分隔為石夕基底4〇1與具有第一導電 型態之矽層403。其中，絕緣層4〇2之形成方法例如是氧 植入隔離法（Separation by Implanted Oxygen，SIM0X)、晶 片黏著法（Bonded Wafer)或介電隔離法（Dielectric Isolation，DI)等，而其材質例如是二氧化矽。另外，矽層 13 1278100 16684twf.doc/r 403之導電型態例如是n型。 之後，於SOI基底400上依序形成具有第一導電型態 之f層404、具有第二導電型態之矽層4〇6、具有第一導電 型恶之石夕層408,以及已圖案化之罩幕層41〇。其中，矽層 404之‘電型怨例如是N型，矽層4〇6之導電型態例如是 P型，矽層408之導電型態例如是N型。矽層4〇4、矽層 4〇6—、石夕層408的形成方法例如是以臨場(In Situ)方式同時 _ 進行磊晶沈積與摻雜製程或其他適合之方法。另外，罩幕 層410之材質例如是氮化石夕，而其形成方法例如是先於石夕 層彻上利用化學氣相沉積法(CVD)全面性地形成罩幕材 料層後，再對罩幕材料層進行微影钱刻製程以形成之。在 —實施例中，罩幕層還可例如是由―墊氧化層與一氮 化石夕層所組成，墊氧化層係形成於氮化石夕層下方，其材質 例如是氧化石夕，形成方法例如是熱氧化法。塾氧化層具有 緩f的作用，可解決氮化石夕層對石夕層表面附著能力不良的 問題。 • ，然後，請同時參照圖7⑻與圖了⑼，以罩幕層物為 罩幕，移除部分矽層404、部分矽層406、部分矽層408, 以及SOI基底400之石夕層403，直至暴露出絕緣層4〇2表 面’以形成多個柱狀結構4〇9。其中，移除部分石夕層4〇4、 部分石夕層406、部分梦層儀，以及部分s〇I基底姻之 石夕層403的方法例如是進行—爛製程。上述所形成之石夕 層餘可做為後續預形成之電晶體的基體(B〇d力區，而石夕 層4〇8a以及與石夕層406a接合之石夕層4〇4&的部分區域可做 ：4twf.doc/r I2781〇〇 為二源極/汲極區。 之後，請同時參照圖8(a)與圖8⑻，於石夕層她、石夕 二(Ma石夕層4〇6a與矽層4。如側壁形成一介電層 412。 ^電層412的材質例如是氧化石夕、氮化石夕、氧化石夕/ ，氧化石夕(〇N〇)等介電材料，其形成方法例如是化學 法。然後，於絕緣層他上形成一層導體層414， 中=414的了貝面高度小於石夕層404a的頂面高度。其 C4的材質例如是摻雜多晶矽、完全金屬矽化 屬等導體材料。導體層414的形成方法例如 層，之=_法於絕緣層402上形成一層導體材料 項 ^ _製程部分導體材料層，直至其 φ ,八貝面问度寻於導體層414的頂面高度。1 刻製程: = 如是 壁之卵4n^ 介電層412及介電層412側 導體戶lu U分砍層衡係可構成一電容器，其中 V脰層414可做為電容哭 ^ Τ 顿可做為電容哭=：：；7極’㈣403a與部分石夕層 器之電容介電層。而介電層412可做為電容 声414 ^人二同照圖9(a)、圖9(b)與圖9(c)，於導體 二=二丨6、_忽 ―域間。介 w:6=:=::= 1278100 16684twf.doc/r 化^^氮化石夕等介電材料，而基體層418的材質例如是摻 1 3夕元王金屬石夕化合物或P型金屬等導體材料。介 電層416、基體層418與介電層420的形成方法是先於導 j 414與介電層412上沈積一層介電材料層，然後移除 "刀此介電材料層，使其表面低於石夕層4〇6a的頂面，高於 夕、g =04a的頂面，以形成介電層416。隨後，於介電層ye f/尤知-層基體材料層，然後移除部分基體材料層，使其 又面低於砂層406a的頂面，以形成基體層418。接著，於 二體層418上沈積—層介電材料層，然後移除部分介電材 料層，至暴露出罩幕層·的表面，以形成介電層物。 422，^罩1=層/2〇 t罩幕層θ 410上形成一層單幕層 八 幕層422的材質例如是氮化矽，其形成方法 =化，沈積法。隨後，於罩幕層422上形= 罩幕且t阻層424係沿列方向形成於相對應 t層1〇上方，且光阻層424之寬度小於罩幕層410之 繼之’請同時參照關⑻、圖剛與圖剛， 層424為罩幕，移除部分罩幕層奶與部分罩幕層41〇， 以形成罩幕層422a與罩幕層41Ga，而罩幕 立 寬度大於光阻層424之寬度。其中，===底部 鱼部八g莖a j m 4刀罩幕層422 1刀罩幕層4H)的方法例如是進行—綱製程。然後， 以光阻層424與罩幕層410a為罩幕，移除未 與罩幕層41〇a所覆蓋之介電層420、基體層418^ 4 416,直至暴露出導體層414與介電層4〗2曰頂面/、"电€ 16 1278100 16684twf.doc/r 特別是，上述於進行移除部分基體層418的步驟，例 如是進行二次蝕刻製程，其包括非等向性蝕刻製程以及等 向性蝕刻製程。因此，移除部分基體層418而形成之基體 線418a係以自行對準之方式形成於柱狀結構4〇9之間，且 電性連接相鄰柱狀結構409之矽層4〇6a。更詳細而言，基 體線418a可做為後續預形成之電晶體的基體接觸出〇办 Contact)，以消除s〇I元件之浮置基體效應(ρ1〇^η§如办 _ Effect)，及其衍生的種種問題。而且，由於基體線41%係 以串接的方式平行形成於柱狀結構4〇9之矽層4〇6a之間， 因此可較習知更為節省元件的使用面積，提高元件的積华 “之後，請同時參照圖11⑻、圖11(b)與圖11(c)，移除 • 光阻層424，其中移除光阻層424的方法例如是進行一钮 刻製程。接著，於導體層414與介電層412上形成一介電 每426其中"黾層426之頂面低於妙層4〇4a之頂面。接 ⑩=，於矽層408a、矽層406a及部分矽層404a之側壁以及 層420a、基體線418a與介電層41如之表面形成一層 ;丨屯層428。其中，介電層428的材質例如是氧化石夕或氮 化=等介電材料，形成方法例如是化學氣相沈積法或其二 適當的方式。然後，於介電層428表面形成一導體層43〇。 "中，導體層430的材質例如是摻雜多晶矽、完全金屬矽 化&物或P型金屬等導體材料，形成方法例如是化學氣相 沈積法或其他適當的方法。 〃 上述，形成於柱狀結構409側壁的介電層428係做為 17 1278100 16684twf.doc/r 問極介電層，而形成於相對應挺狀結構側壁之導體層 430可當做是閘極，且形成於相對應介電層微、基體線 她與介電層416a側壁之導體層可當做是字元線 (W〇nl Une ’ WL) °因此’導體層43G、介電層428、石夕層 聲、矽層406a、矽層4〇4a係可構成一電晶體。而且， 由於基體線雜係形成於柱狀結構4〇9之間，因此基體線 條不會與導體層物接觸，而產生短路⑽。拳情形。 另-方面，本發明之電晶體具有二開極結構，亦即是具有 二通迢區，因此其汲極電流(Ids)為單通道區之電晶體的2 t，如此一來可提高元件的電流驅動力。 繼之’請同時參照圖u⑷、圖U⑼與圖Η⑷，於介 426上形成-層介電層432，覆蓋罩幕層422&、罩幕 層410a、介電層428以及導體層物。然後，移除罩幕層 a、罩幕層術、介電層働與部分介電層432至暴 二出石夕層4G8a表面。接著，於梦層聲上形成一導體層 伤〜f導體層434與導體層430垂直。上述之導體層434 係§做是位元線(Bit Line，BL)。 實施例中’於介電層432形成前，更可移除部分 ^層430 ’使導體層㈣之頂面低於石夕層408a之頂面。 二胜移f部分導體層430的方法例如是進行-酬製 '別疋，上述之移除部分導體層430的步驟，能夠避 免^體層434(位元線)因製賴差而與導體層43G產生不 正苇的包性連接，進而使元件發生短路或失效等問題。 18 間There is a Silicon On Insulator (SOI) substrate 400, which is, for example, an N-type substrate. The SOI substrate 400 has an insulating layer 402 therein, and the insulating layer 402 separates the SOI substrate 400 into a stone substrate 4〇1 and a germanium layer 403 having a first conductivity type. The method for forming the insulating layer 4〇2 is, for example, Separation by Implanted Oxygen (SIM0X), Bonded Wafer or Dielectric Isolation (DI), and the like. It is cerium oxide. Further, the conductivity type of the germanium layer 13 1278100 16684twf.doc/r 403 is, for example, an n-type. Thereafter, a f layer 404 having a first conductivity type, a germanium layer 4〇6 having a second conductivity type, a layer 408 having a first conductivity type, and a patterned layer are sequentially formed on the SOI substrate 400. The mask layer 41〇. The conductivity type of the germanium layer 404 is, for example, an N type, and the conductive type of the germanium layer 4 is, for example, a P type, and the conductive type of the germanium layer 408 is, for example, an N type. The formation method of the germanium layer 4〇4, the germanium layer 4〇6—, and the stone layer 408 is, for example, an in-situ (In Situ) method for performing epitaxial deposition and doping processes or other suitable methods. In addition, the material of the mask layer 410 is, for example, a nitrite, and the formation method thereof is, for example, a comprehensive formation of a mask material layer by chemical vapor deposition (CVD) before the layer is applied, and then the mask is formed. The material layer is subjected to a lithography process to form it. In an embodiment, the mask layer may also be composed, for example, of a pad oxide layer and a nitride layer, and the pad oxide layer is formed under the nitride layer, and the material thereof is, for example, oxidized oxide, forming a method, for example. It is a thermal oxidation method. The niobium oxide layer has the effect of retarding f, and can solve the problem that the nitrile layer has poor adhesion to the surface of the stone layer. • Then, please refer to FIG. 7(8) and FIG. 9(9) simultaneously, with the mask layer as a mask, and remove part of the layer 404, part of the layer 406, part of the layer 408, and the layer 403 of the SOI substrate 400, Until the surface of the insulating layer 4〇2 is exposed to form a plurality of columnar structures 4〇9. Wherein, the method of removing part of the stone layer 4〇4, part of the stone layer 406, part of the layerer, and part of the layer 403 of the base layer is, for example, performing a rotten process. The layer formed by the above can be used as the base of the subsequently preformed transistor (B〇d force zone, and the part of the stone layer 4〇8a and the stone layer 4〇4& which is joined with the stone layer 406a) The area can be done: 4twf.doc/r I2781〇〇 is the two source/bungee area. After that, please refer to Fig. 8(a) and Fig. 8(8) at the same time, in Shi Xi layer, she Xi Er 2 (Ma Shi Xi layer 4 〇6a and 矽4. A dielectric layer 412 is formed on the sidewalls. The material of the electrical layer 412 is, for example, a dielectric material such as oxidized oxide, nitrite, oxidized oxide, or oxidized stone (〇N〇). The forming method is, for example, a chemical method. Then, a conductor layer 414 is formed on the insulating layer, and the height of the shell surface of the middle = 414 is smaller than the height of the top surface of the layer 404a. The material of the C4 is, for example, doped polysilicon, completely. The metal bismuth is a conductor material. The conductor layer 414 is formed by a layer, for example, a layer of a conductor material is formed on the insulating layer 402, and the conductor material layer is formed until the φ, the eight-facet problem is found in the conductor. The top surface height of the layer 414. 1 engraving process: = if the wall of the egg 4n ^ dielectric layer 412 and the dielectric layer 412 side conductor household u U cut The layer balance system can constitute a capacitor, wherein the V 脰 layer 414 can be used as a capacitor crying 可 可 can be used as a capacitor crying =::; 7 pole '(four) 403a and a part of the capacitor layer of the dielectric layer. 412 can be used as a condenser sound 414 ^ person two together with Figure 9 (a), Figure 9 (b) and Figure 9 (c), between the conductor two = two 丨 6, _ suddenly "domain. Intermediary w: 6 =: =::= 1278100 16684twf.doc/r The dielectric material of the nitride layer is formed, and the material of the base layer 418 is, for example, a conductor material such as a metal alloy or a P-type metal. 416, the base layer 418 and the dielectric layer 420 are formed by depositing a layer of dielectric material on the conductive layer 414 and the dielectric layer 412, and then removing the layer of the dielectric material to make the surface lower than the stone. The top surface of the layer 4〇6a is higher than the top surface of g = 04a to form the dielectric layer 416. Subsequently, the dielectric layer ye f / especially the layer of the base material layer, and then remove part of the base material The layer is further lower than the top surface of the sand layer 406a to form the base layer 418. Next, a layer of dielectric material is deposited on the body layer 418, and then a portion of the dielectric material layer is removed to expose the mask layer ·of Surface, to form a dielectric layer. 422, ^ hood 1 = layer / 2 〇 t mask layer θ 410 on the formation of a single layer of the eight-layer 422 material such as tantalum nitride, its formation method = deposition, deposition Then, the mask layer 422 is formed on the mask layer 422 and the resist layer 424 is formed in the column direction above the corresponding t layer 1〇, and the width of the photoresist layer 424 is smaller than the mask layer 410. Referring to the reference (8), the diagram and the diagram, the layer 424 is a mask, and part of the mask layer milk and part of the mask layer 41 are removed to form the mask layer 422a and the mask layer 41Ga, and the mask width is greater than The width of the photoresist layer 424. Among them, === bottom fish part eight g stem a j m 4 knife cover layer 422 1 knife cover layer 4H) method is for example - the process. Then, with the photoresist layer 424 and the mask layer 410a as a mask, the dielectric layer 420 and the base layer 418^4 416 not covered by the mask layer 41A are removed until the conductor layer 414 and the dielectric are exposed. Layer 4 曰 2 曰 top surface /, " electricity € 16 1278100 16684twf.doc / r In particular, the above step of removing part of the base layer 418, for example, is a secondary etching process, including anisotropic etching Process and isotropic etching processes. Therefore, the base line 418a formed by removing a portion of the base layer 418 is formed between the columnar structures 4〇9 in a self-aligned manner, and electrically connects the tantalum layers 4〇6a of the adjacent columnar structures 409. In more detail, the base line 418a can be used as a substrate contact for the subsequent pre-formed transistor to eliminate the floating substrate effect of the 〇I element (ρ1〇^η§ _ Effect), and The problems it derives. Moreover, since 41% of the base line is formed in parallel in the manner of being connected in parallel between the top layer 4〇6a of the columnar structure 4〇9, it is more practical to save the use area of the component and improve the accumulating of the component. Thereafter, please refer to FIG. 11 (8), FIG. 11 (b) and FIG. 11 (c), and remove the photoresist layer 424, wherein the method of removing the photoresist layer 424 is, for example, performing a button etching process. Then, on the conductor layer 414 and a dielectric layer 412 are formed on the dielectric layer 412, wherein the top surface of the layer 426 is lower than the top surface of the layer 4 4a. 10 =, the layer 408a, the layer 406a and the portion of the layer 404a The sidewalls and the layer 420a, the base line 418a and the dielectric layer 41 form a layer on the surface thereof; the germanium layer 428. The material of the dielectric layer 428 is, for example, a dielectric material such as oxidized oxide or nitriding, and the like. It is a chemical vapor deposition method or a suitable method thereof. Then, a conductor layer 43 is formed on the surface of the dielectric layer 428. The material of the conductor layer 430 is, for example, doped polysilicon, fully metal deuterated & Conductive materials such as P-type metals, such as chemical vapor deposition or other suitable methods The dielectric layer 428 formed on the sidewall of the columnar structure 409 is referred to as a 17 1278100 16684 twf.doc/r dielectric layer, and the conductor layer 430 formed on the sidewall of the corresponding stiff structure can be regarded as a gate. And formed on the corresponding dielectric layer micro, the base line and the conductor layer of the sidewall of the dielectric layer 416a can be regarded as a word line (W〇nl Une ' WL) ° thus the conductor layer 43G, the dielectric layer 428, the stone The layer acoustic layer, the enamel layer 406a, and the enamel layer 4〇4a may constitute a transistor. Moreover, since the matrix line hybrid is formed between the columnar structures 4〇9, the substrate lines are not in contact with the conductor layer, and A short circuit (10) is generated. In other aspects, the transistor of the present invention has a two-open structure, that is, has a two-pass region, and therefore its drain current (Ids) is 2 t of the transistor of the single channel region. In this way, the current driving force of the device can be improved. Then, please refer to FIG. u(4), FIG. U(9) and FIG. 4(4), and a dielectric layer 432 is formed on the dielectric layer 426, covering the mask layer 422&, the mask layer 410a, The dielectric layer 428 and the conductor layer. Then, the mask layer a, the mask layer, and the dielectric layer are removed. And a portion of the dielectric layer 432 to the surface of the 4G8a layer. Next, a conductor layer is formed on the layer of the dream layer. The conductor layer 434 is perpendicular to the conductor layer 430. The conductor layer 434 is a bit line. (Bit Line, BL). In the embodiment, before the formation of the dielectric layer 432, the portion 430' may be removed to make the top surface of the conductor layer (4) lower than the top surface of the layer 408a. The method of the conductor layer 430 is, for example, a process of performing a compensation process, and the above-described step of removing a portion of the conductor layer 430 can prevent the body layer 434 (bit line) from being misaligned with the conductor layer 43G due to the difference in the manufacturing process. Sexual connections, which in turn cause problems such as short-circuiting or failure of components. 18 rooms
1278100 16684twf.d〇c/r 上述可知，本發明之方法所使用之製料為—般半 ¥體相中所熟知之技藝，@此在製作上較為簡單 雜，如此可較為節省製程之成本。 綜上所述，本發明至少具有下列之優點·· 1·本發明係於電晶體侧壁形成一基體線做為基體 觸’以 >肖除7G件之浮置基體效應，及其射龍種問題。 而且’由於基體線細轉的方式平行形成於二電晶體之 ’因此可較習知更為節省元件的使用面積，提高元件 積集度。 ^本發明所使狀製程皆為—般半導體製程中所熟知 之技#，因此在製作上較為簡單不複雜，如此可較 製程之成本。 3·本發明之電晶體的汲極電流(Ids)為單通道區之電晶 體的2倍，如此一來可提高元件的電流驅動力。 _ 雖然本發明已以較佳實施例揭露如上，然其並非用以 限J本發明，任何熟習此技藝者，在不麟本發明之精神 和範圍内，當可作些許之更動與潤飾，因此本發明之保護 範圍當視後附之申請專利範圍所界定者為準。 又 【圖式簡單說明】 圖1為繪示習知一種絕緣層上有矽元件之剖面示意 圖2為繪示習知一種具有基體接觸之溝渠式電容記憶 胞之剖面示意圖。 圖3為綠示圖2之溝渠式電容記憶胞陣列之上視示意 19 1278100 twf.doc/r 圖。 圖4為依財發明魏例所纟㈡之動態隨 艘之陣列的佈局上視圖。 圖5為纟會示圖4之動態隨機存取記憶體陣列之剖面示 意圖，其中子圖⑻為沿A-A，方向之剖面示意圖，子圖(的 為沿B-B’方向之剖面示意圖。 圖6至圖12為依照本發明實施例所繪示之動態隨機 存取記憶體的製造流程的示意圖，其中子圖（a)係繪示上視1278100 16684twf.d〇c/r As can be seen from the above, the method used in the method of the present invention is a well-known technique in the body phase, which is relatively simple in production, which can save the cost of the process. In summary, the present invention has at least the following advantages: 1. The present invention is based on the sidewall of the transistor to form a base line as a substrate to touch the effect of the floating substrate of the 7G piece, and its shooting dragon Kind of problem. Further, since the base line is formed in parallel in the manner of the fine rotation of the substrate, it is more practical to save the use area of the element and to improve the element accumulation. The manufacturing process of the present invention is a technique known in the semiconductor manufacturing process, and thus is relatively simple and uncomplicated in production, so that the cost of the process can be compared. 3. The gate current (Ids) of the transistor of the present invention is twice that of the single crystal region, so that the current driving force of the device can be improved. Although the present invention has been disclosed in the above preferred embodiments, it is not intended to limit the invention, and any skilled person skilled in the art can make some modifications and refinements within the spirit and scope of the present invention. The scope of the invention is defined by the scope of the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic cross-sectional view showing a conventional germanium element having an insulating layer. FIG. 2 is a schematic cross-sectional view showing a conventional trench-type capacitive memory cell having a substrate contact. Fig. 3 is a top view of the trench capacitor memory cell array of Fig. 2, showing a schematic diagram of 19 1278100 twf.doc/r. Fig. 4 is a top view showing the layout of the dynamic array of ships according to the Wei (2) of the Wei Dynasty. 5 is a cross-sectional view of the dynamic random access memory array of FIG. 4, wherein the sub-picture (8) is a cross-sectional view along the direction of AA, and the sub-picture is a cross-sectional view along the B-B' direction. FIG. 12 is a schematic diagram of a manufacturing process of a dynamic random access memory according to an embodiment of the invention, wherein the sub-picture (a) is a top view
禾意圖，子圖（b)係繪示沿剖面線14,之剖面示意子圖 (c)係繪示沿剖面線Π-Π，之剖面示意圖。 、回 回 【主要元件符號説明】 10 :半導體元件 11 :深溝渠式電容器 12 :深溝渠 14 :基底In the intent, the subgraph (b) is shown along the section line 14, and the section diagram (c) is a schematic cross-sectional view along the section line Π-Π. , Back [Main component symbol description] 10 : Semiconductor component 11 : Deep trench capacitor 12 : Deep trench 14 : Base
機存取記億 48 :基體接觸 52 :垂直式電晶體 72、506 :字元線 78 :接觸窗 82、5〇8 :位元線 90 :主秦區 100 :矽基底 102、402 :絕緣層 104 :石夕主體 20 I2781〇〇twf,oc/r 106 :淺摻雜區 108、514、516 :源極/汲極區 110、518 :基體區 112、522 :閘極結構 400、500 :絕緣層上有矽基底 401 :矽基底 403、403a、404、404a、406、406a、408、408a :矽 409 :柱狀結構 410、410a、422、422a :罩幕層 412、416、416a、420、426、428、432 :介電層 414、430、434 :導體層 418 :基體層 418a、504 :基體線 424 :光阻層 502 :記憶單元 510 :電晶體 512 :電容器 520 :閘極介電層 524 :半導體柱狀結構 526、528 :電極 530 :電容介電層 21Machine access memory 48: base contact 52: vertical transistor 72, 506: word line 78: contact window 82, 5 〇 8: bit line 90: main Qin area 100: 矽 base 102, 402: insulation 104: Shixi main body 20 I2781〇〇twf, oc/r 106: shallow doped region 108, 514, 516: source/drain region 110, 518: base region 112, 522: gate structure 400, 500: insulation The layer has a germanium substrate 401: germanium substrate 403, 403a, 404, 404a, 406, 406a, 408, 408a: germanium 409: columnar structures 410, 410a, 422, 422a: mask layers 412, 416, 416a, 420, 426, 428, 432: dielectric layer 414, 430, 434: conductor layer 418: base layer 418a, 504: base line 424: photoresist layer 502: memory unit 510: transistor 512: capacitor 520: gate dielectric layer 524: semiconductor columnar structures 526, 528: electrode 530: capacitor dielectric layer 21