1273274 九、發明說明： 【發明所屬之技術領域】 本發明係關於一種脈波產生器及脈波產生方法，尤指一 種可調整脈寬之脈波產生器及脈波產生方法。 【先前技術】 脈波產生器已廣泛地使用在積體電路的運用產品中，係 利用時脈訊號（clock signal)之觸發來產生電子脈衝訊號。 圖1所示為一習知之脈波產生器1，其包含一延遲單元12及 一 NAND邏輯閘11。該延遲單元12係用以將一輸入訊號Pin 反相並延遲一特定内部時間（certain internal time)而形成一 延遲訊號&。該NAND邏輯閘11接收該延遲訊號f及該輸 入訊號Pin之後，經過NAND運算輸出一輸出訊號p〇ut。其中 位於上方之橫條符號表示負邏輯（negatiVe i〇gic)運算。 該延遲單元12之結構可以圖2(a)或圖2(b)之方式實現。於 圖2(a)中，奇數個反相器INV彼此串接形成該延遲單元12。 於圖2(b)中，奇數組之反相器INV及電阻器r彼此串接形成 另一種形式之該延遲單元12。圖3表示該輸入訊號Ριη、延遲 訊號怂及該輸出訊號P〇uti時序圖，其中該輸出訊號？。以之 脈寬與該延遲單元12中之反相器inV數目有關。因此，一旦 以圖2(a)或圖2(b)實現之延遲單元12被使用在習知之脈波 產生器1時，則該輸出訊號Ρ_之脈寬將固定不變。圖3也顯 示習知之脈波產生器丨係操作在輸入訊號Ριη之升緣。若需要 操作在降緣，則圖丨中之NAND邏輯閘丨丨改為1^〇11邏輯閘（圖 未不）即可。 100021.doc 1273274 另，美國專利US6，121，803揭示一脈波產生器，係根據一 電壓源Vcc由ΟV上升至3 V(或5 V)及將一電源打開（p〇wer 〇n) 或重置（reset)以穂定地產生脈波訊號。然而，當該電壓源 Vcc之上升斜率（slew rate)控制不良時，將導致脈波脈寬改 臺。另外，將δ亥電壓源Vcc由0V提昇（boost)至3V(或5V)時， 所需之時間需要數微秒（1〇-6秒）或更長，因此無法滿足脈波 寬度小於微秒的運用上。此外，上述之習知技藝需要許多 的反相器或電晶體方可產生一具預期脈寬之脈波，然，如 此將增加電路設計之複雜度及成本。 【發明内容】 本發明之主要目的係提供一種脈波產生器，該脈波產生 β使用較少之電晶體來產生具大範圍可調脈寬之脈波訊 號。本發明之次要目的係提供一種脈波產生器，係藉由一 控制訊號來調整脈波之脈寬。 為達到上述之目的，本發明揭示一種脈波產生器，該脈 波產生器包含一 CMOS反相器、一電容元件及一電阻元件。 該CMOS反相器具兩端子，分別連接至一電壓源及一參考電 壓（例如接地）。該電容元件及該電阻元件並聯連接至該 CMOS反相器之輪入端，且該CM〇s反相器之輸出端產生複 數個脈波輸入汛號（或稱提昇訊號）利用該電容元件耦合 至A CMOS反相器之輸入端，而儲存於該電容元件之電荷可 猎由該電阻兀件釋放電荷。該輸入訊號可為一於數奈秒 (ίο9秒）之内由〇v提昇至3λ^5ν之訊號。如此，操控該 CMOS反相之輪人端之電壓，即可用以控制該㈤⑽反相 100021.doc 1273274 器之操作，即控制該CMOS反相器輸出端之電壓位準。脈波 之脈寬可藉由控制經由該電容元件接收及經由該電阻元件 放電之該輸入訊號來加以調整。該脈波之脈寬可調整至奈 秒等級之寬度。 【實施方式】 圖4係本發明之脈波產生器2之系統方塊圖。該脈波產生 器2包含一 CMOS反相器3、一電容元件4及一電阻元件5。該 CMOS反相器3包含連接至一電壓源vcc之一第一端點31、 連接至一第一參考電壓Vrefl之一第二端點32及用以輸出脈 波Vo ut之輸出端30。該電容元件4之一輸入端42接收一提昇 訊號BST ’其另一節點n係連接至該CMOS反相器3之輸入 端。該電阻元件5之一端點連接至該節點n，其另一端點則 連接至一第二參考電壓Vref2。因此，該電容元件4及該電阻 元件5係並聯連接至該CMOS反相器3之輸入端。 圖5係本發明之脈波產生器2之一實施例之電路示意圖。 該CMOS反相器3包含一 PM0S電晶體34及一 NM0S電晶體 35。該PM0S電晶體34及該NM0S電晶體35之閘極連接至該 CMOS反相器3之輸入端，意即上述兩者之閘極電氣連接至 該節點N。該第一端點3丨連接一電壓源Vcc。在此實施例 中，第一參考電壓vrefl及第二參考電壓Vren均接地；該電 容元件4採用具電容值c之一電容器43 ;該電阻元件3採用具 電阻值R之一電阻器53。該脈波產生器2係操作在開機後之 穩定狀態’即操作在該電壓源VCC已達穩態之後。 圖6係圖5之脈波產生器2之相關訊號時序圖，其顯示輸入 100021.doc 1273274 端42、節點N及輸出端30之電壓變化。首先，節點N之電壓 Vn位於低位準且電容器43中無電荷儲存。複參圖5，此時因 為PMOS電晶體34處於導通狀態，輸出端3〇之電壓Vout則位 於高位準且等於電壓源Vcc。參圖6之路徑（a)，當提昇訊號 BST之電壓由0V提昇至Vcc時，藉由電容器43與提昇訊號 BST耦合之節點N之電壓Vn則上升至一特定位準，其中該特 定位準由電容器43之電容值C所決定且通常小於電壓源 Vcc。如路徑（b)所示，當Vn大於NMOS電晶體35之門檻電壓 (threshold voltage)時，NMOS 電晶體 35及 PMOS 電晶體 34分 別轉變成導通及非導通狀態，此時輸出端3〇將與第二端點 32電氣連接。於本實施例中，第二端點32係接地，因此輸 出端30之電壓Vout降為低位準。之後，如路徑（c)所示，節 點N之電壓Vn將藉由電阻器53逐漸釋放電荷而下降。當Vn 低於NMOS電晶體35之門檻電壓時，意即當儲存在電容元件 之電荷低於門檻電壓時，NMOS電晶體35及PMOS電晶體34 分別轉變成非導通及導通狀態。因此，Vout將由低位準轉 變成高位準（Vcc)，而電容器43中之電荷釋放率（dissipating rate)將決定Vout脈波之脈寬。在本實施例中，提昇訊號BST 被使用作為上升緣觸發訊號。然而，提昇訊號BST亦可實 施成下降緣觸發訊號。 圖7係本發明之脈波產生器2之另一實施例之電路示意 圖，係將圖5之該電容器43及該電阻器53分別以一 PMOS電 晶體44及一 NMOS電晶體54取代。該PMOS電晶體44之源極 和汲極連接至輸入端42以接收提昇訊號BST。該PMOS電晶 100021.doc 1273274 體44之閘極則連接至節點N。當該脈波產生器2於操作時， 可施加一大於该NMOS電晶體54之門檻電壓之控制訊號Vs 於該NMOS電晶體54之閘極55，以使得該NM〇s電晶體54轉 變成導通狀態，以形成一條經由該NM〇s電晶體54流通至地 面之釋放電荷路徑。因此儲存於該1>]^〇3電晶體44之電荷可 經由釋放電荷路徑釋放至地面。於本實施例中，v〇ut之脈 寬大小可利用控制訊號Vs加以調整。當控制訊號Vs愈大 . 時，表示流經該NMOS電晶體54至地面的電流愈大，意即節 點N之電荷釋放率愈高，則v〇ut之脈寬將減小。此外，該脈 波產生器2在操作過程中，控制訊號Vs是可調整。v〇ut之脈 . 寬大小亦跟該PMOS電晶體44之電容值C，有關。當電容值c, • 愈大時，Vout之脈寬將愈大。另，Vout之脈寬大小也可藉 由改變該NMOS電晶體54之電阻值來調整。 於圖7之實施例中，該pM〇s電晶體44之閘極係連接至節 點N ’因此其中所使用之電晶體型式（p型或n型）則如圖7所 .不。然，若將該PMOS電晶體44之連接端點反向，意即將該 PMOS電晶體44之源極及汲極連接至節點N且將其閘極連 接至輸入端42，也是可行的。只要改變其中所使用之電晶 體型式即可。 本發明之脈波產生器2優於習知脈波產生器1之處在於： (1)於操作時，Vout之脈寬大小可以調整；以及（2)所使用的 電晶體數量大為減少。 本發明之技術内容及技術特點已揭示如上，然而熟悉本 項技術之人士仍可能基於本發明之教示及揭示而作種種不 100021.doc 1273274 为離本發明精神之替換及修飾。因此，本發明之保護範圍 應不限於實施例所揭示者，而應包括各種不背離本發明之 替換及修飾，並為以下之申請專利範圍所涵蓋。 【圖式簡單說明】 圖1例示習知脈波產生器之電路示意圖； 圖2 (a)及2(b)例示圖1之延遲單元之電路示意圖； 圖3為習知脈波產生器相關訊號之時序圖； 圖4係本發明之脈波產生器之系統方塊圖； 圖5係本發明之脈波產生器之一實施例之電路示意圖； 圖6係圖5之脈波產生器之相關訊號時序圖；以及 圖7係本發明之脈波產生器之另一實施例之電路示意圖。 【主要元件符號說明】 卜2 脈波產生器 3 CMOS反相器 4 電容元件 5 電阻元件 11 NAND邏輯閘 12 延遲單元 30 輸出端 31 第一端點 32 第二端點 34、44 PMOS電晶體 35 > 54 NMOS電晶體 42 輸入端 43 電容器 53 電阻器 55 閘極 100021.doc -10-1273274 IX. Description of the Invention: [Technical Field] The present invention relates to a pulse wave generator and a pulse wave generating method, and more particularly to a pulse wave generator and a pulse wave generating method capable of adjusting a pulse width. [Prior Art] A pulse wave generator has been widely used in the application of an integrated circuit, and an electronic pulse signal is generated by triggering a clock signal. Figure 1 shows a conventional pulse generator 1 comprising a delay unit 12 and a NAND logic gate 11. The delay unit 12 is configured to invert an input signal Pin and delay a specific internal time to form a delay signal & After receiving the delay signal f and the input signal Pin, the NAND logic gate 11 outputs an output signal p〇ut through a NAND operation. The horizontal bar symbol at the top indicates the negative logic (negatiVe i〇gic) operation. The structure of the delay unit 12 can be implemented in the manner of FIG. 2(a) or FIG. 2(b). In Fig. 2(a), an odd number of inverters INV are connected in series to each other to form the delay unit 12. In Fig. 2(b), the inverter INV of the odd array and the resistor r are connected in series to each other to form the delay unit 12 of another form. FIG. 3 is a timing diagram of the input signal Ριη, the delayed signal 怂, and the output signal P〇uti, wherein the output signal is? . The pulse width is related to the number of inverters inV in the delay unit 12. Therefore, once the delay unit 12 implemented in Fig. 2(a) or Fig. 2(b) is used in the conventional pulse generator 1, the pulse width of the output signal Ρ_ will be fixed. Figure 3 also shows that the conventional pulse generator is operating at the rising edge of the input signal Ριη. If the operation is required to fall, the NAND logic gate in the figure is changed to 1^〇11 logic gate (not shown). U.S. Patent No. 6,121,803 discloses a pulse generator that rises from ΟV to 3 V (or 5 V) and opens a power source (p〇wer 〇n) according to a voltage source Vcc or Reset to generate a pulse signal indefinitely. However, when the slew rate of the voltage source Vcc is poorly controlled, the pulse width is changed. In addition, when the δHay voltage source Vcc is boosted from 0V to 3V (or 5V), the required time takes several microseconds (1〇-6 seconds) or longer, so the pulse width is less than microseconds. The use of. In addition, the above-described prior art requires many inverters or transistors to generate a pulse wave of a desired pulse width, which, as a result, increases the complexity and cost of the circuit design. SUMMARY OF THE INVENTION A primary object of the present invention is to provide a pulse wave generator that uses less transistors to generate pulse signals having a wide range of adjustable pulse widths. A secondary object of the present invention is to provide a pulse wave generator that adjusts the pulse width of a pulse wave by a control signal. To achieve the above object, the present invention discloses a pulse wave generator comprising a CMOS inverter, a capacitive element and a resistive element. The two terminals of the CMOS inverter device are respectively connected to a voltage source and a reference voltage (for example, ground). The capacitive element and the resistive element are connected in parallel to the wheel-in end of the CMOS inverter, and the output end of the CM〇s inverter generates a plurality of pulse input nicknames (or boost signals) coupled by the capacitive element To the input of the A CMOS inverter, the charge stored in the capacitive element can be hunted by the resistor to release the charge. The input signal can be a signal that is raised from 〇v to 3λ^5ν within a few nanoseconds (ίο9 seconds). Thus, by controlling the voltage of the CMOS inverting wheel terminal, the operation of the (5) (10) inverting 100021.doc 1273274 can be controlled to control the voltage level of the output of the CMOS inverter. The pulse width of the pulse wave can be adjusted by controlling the input signal received through the capacitive element and discharged through the resistive element. The pulse width of the pulse can be adjusted to the width of the nanosecond level. [Embodiment] FIG. 4 is a system block diagram of a pulse wave generator 2 of the present invention. The pulse generator 2 comprises a CMOS inverter 3, a capacitive element 4 and a resistive element 5. The CMOS inverter 3 includes a first terminal 31 connected to a voltage source vcc, a second terminal 32 connected to a first reference voltage Vref1, and an output terminal 30 for outputting a pulse Vo ut. One of the input terminals 42 of the capacitive element 4 receives a boost signal BST' and its other node n is coupled to the input of the CMOS inverter 3. One end of the resistive element 5 is connected to the node n, and the other end thereof is connected to a second reference voltage Vref2. Therefore, the capacitive element 4 and the resistive element 5 are connected in parallel to the input terminal of the CMOS inverter 3. Figure 5 is a circuit diagram showing an embodiment of the pulse wave generator 2 of the present invention. The CMOS inverter 3 includes a PMOS transistor 34 and an NMOS transistor 35. The gates of the PMOS transistor 34 and the NMOS transistor 35 are coupled to the input of the CMOS inverter 3, meaning that the gates of the two are electrically connected to the node N. The first terminal terminal 3 is connected to a voltage source Vcc. In this embodiment, the first reference voltage vref1 and the second reference voltage Vren are both grounded; the capacitor element 4 is a capacitor 43 having a capacitance value c; and the resistor element 3 is a resistor 53 having a resistance value R. The pulse generator 2 operates in a steady state after power-on, i.e., after the voltage source VCC has reached a steady state. Figure 6 is a timing diagram of the associated signal of the pulse generator 2 of Figure 5, showing the voltage change at terminal 42, node N and output 30 of input 100021.doc 1273274. First, the voltage Vn of the node N is at a low level and no charge is stored in the capacitor 43. Referring to Figure 5, at this time, because the PMOS transistor 34 is in an on state, the voltage Vout at the output terminal 3 is at a high level and is equal to the voltage source Vcc. Referring to path (a) of FIG. 6, when the voltage of the boost signal BST is raised from 0V to Vcc, the voltage Vn of the node N coupled by the capacitor 43 and the boost signal BST rises to a specific level, wherein the specific level It is determined by the capacitance value C of the capacitor 43 and is usually smaller than the voltage source Vcc. As shown in the path (b), when Vn is greater than the threshold voltage of the NMOS transistor 35, the NMOS transistor 35 and the PMOS transistor 34 are respectively turned into a conducting and non-conducting state, and the output terminal 3〇 is The second terminal 32 is electrically connected. In the present embodiment, the second terminal 32 is grounded, so that the voltage Vout of the output terminal 30 is lowered to a low level. Thereafter, as shown by the path (c), the voltage Vn of the node N will be lowered by the gradual discharge of the electric charge by the resistor 53. When Vn is lower than the threshold voltage of the NMOS transistor 35, that is, when the charge stored in the capacitor element is lower than the threshold voltage, the NMOS transistor 35 and the PMOS transistor 34 are respectively turned into a non-conducting and conducting state. Therefore, Vout will change from a low level to a high level (Vcc), and the dissipating rate in capacitor 43 will determine the pulse width of the Vout pulse. In this embodiment, the boost signal BST is used as a rising edge trigger signal. However, the boost signal BST can also be implemented as a falling edge trigger signal. Fig. 7 is a circuit diagram showing another embodiment of the pulse wave generator 2 of the present invention, in which the capacitor 43 and the resistor 53 of Fig. 5 are replaced by a PMOS transistor 44 and an NMOS transistor 54, respectively. The source and drain of the PMOS transistor 44 are coupled to the input 42 to receive the boost signal BST. The PMOS transistor 100021.doc 1273274 The gate of body 44 is connected to node N. When the pulse generator 2 is in operation, a control signal Vs greater than the threshold voltage of the NMOS transistor 54 can be applied to the gate 55 of the NMOS transistor 54 to turn the NM〇s transistor 54 into conduction. State to form a discharge charge path that circulates to the ground via the NM〇s transistor 54. Therefore, the charge stored in the 1>3 transistor 3 can be released to the ground via the release charge path. In this embodiment, the pulse width of v〇ut can be adjusted by using the control signal Vs. When the control signal Vs is larger, it indicates that the larger the current flowing through the NMOS transistor 54 to the ground, that is, the higher the charge release rate of the node N, the pulse width of v〇ut will decrease. Further, during the operation of the pulse generator 2, the control signal Vs is adjustable. The pulse width is also related to the capacitance value C of the PMOS transistor 44. When the capacitance value c, • is larger, the pulse width of Vout will be larger. In addition, the pulse width of Vout can also be adjusted by changing the resistance value of the NMOS transistor 54. In the embodiment of Figure 7, the gate of the pM?s transistor 44 is connected to node N' so that the type of transistor used therein (p-type or n-type) is as shown in Figure 7. However, if the connection terminal of the PMOS transistor 44 is reversed, it is feasible to connect the source and drain of the PMOS transistor 44 to the node N and connect its gate to the input terminal 42. Just change the type of electro-optic used in it. The pulse wave generator 2 of the present invention is superior to the conventional pulse wave generator 1 in that: (1) the pulse width of Vout can be adjusted during operation; and (2) the number of transistors used is greatly reduced. The technical contents and technical features of the present invention have been disclosed as above, but those skilled in the art can still make various alternatives and modifications to the spirit of the present invention based on the teachings and disclosures of the present invention. Therefore, the scope of the present invention should be construed as being limited by the scope of the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic circuit diagram of a conventional pulse wave generator; FIGS. 2(a) and 2(b) are schematic diagrams showing the circuit of the delay unit of FIG. 1; FIG. 3 is a conventional pulse wave generator related signal. 4 is a system block diagram of a pulse wave generator of the present invention; FIG. 5 is a circuit diagram of an embodiment of a pulse wave generator of the present invention; FIG. 6 is a related signal of the pulse wave generator of FIG. A timing diagram; and Figure 7 is a circuit diagram of another embodiment of a pulse wave generator of the present invention. [Main component symbol description] Bu 2 Pulse generator 3 CMOS inverter 4 Capacitive element 5 Resistive element 11 NAND logic gate 12 Delay unit 30 Output terminal 31 First terminal 32 Second terminal 34, 44 PMOS transistor 35 > 54 NMOS transistor 42 input terminal 43 capacitor 53 resistor 55 gate 100021.doc -10-