TWI273147B - Method for plating on a substrate and conductive dry film used in the method - Google Patents
Method for plating on a substrate and conductive dry film used in the method Download PDFInfo
- Publication number
- TWI273147B TWI273147B TW93131283A TW93131283A TWI273147B TW I273147 B TWI273147 B TW I273147B TW 93131283 A TW93131283 A TW 93131283A TW 93131283 A TW93131283 A TW 93131283A TW I273147 B TWI273147 B TW I273147B
- Authority
- TW
- Taiwan
- Prior art keywords
- conductive
- substrate
- dry film
- layer
- photoresist
- Prior art date
Links
Landscapes
- Manufacturing Of Printed Wiring (AREA)
Abstract
Description
12731471273147
【發明所屬之技術領域】 本發明係有關於一種基板電鍍方法,特別係有關於一 種無電鑛線連接之基板電鑛_方法。 【先前技術】 習知電路基板在後段製程中係包含有一電鍍作業,以 保護外露之金屬墊或線路並增進銲接特性,因此電路基板 ,設計有適當的電鍍線或是電鍍導接路徑,以利電鍍。隨 著電路基板之線路密集化與特殊用途,電路基板需要在缺 乏電鍍線連接的區段增加獨立接墊或獨立線路,導致後 電鍍之困難。 V'' 一種習知之基板電鍍方法,如中華民國專利公告第 5 93 789唬「基板電鍍製程」所揭示者,該製程係包含下列 步驟:提供一已完成前段製程之基板,該基板係具有一義 板内部線路、一第一表面及對應之一第二表面,該第一^ 面係具有複數個第一接觸墊及複數個線路圖荦, ^ 面係具有複數個第二接觸墊及複數個線路Κ 與第二表面係分別具有一防銲層,係用以覆蓋該些線路圖 案。’而暴露出該些第一接觸墊與第二接觸墊,為了電鑛 之,性導接,一導電種子層(conductive seed layer)係 在該基板之第一表面上,再電鍍形成一第一金屬層與 一第二金屬層於該導電種子層與該些第二接觸墊上, 再圖案化該第一金屬層與該導電種子層。因此,相對於L 知以電鍍線連接之電鍍製程,額外的導電種子層形成與^ 案化步驟需要被額外添加,故製造成本將大幅增加,不利BACKGROUND OF THE INVENTION 1. Field of the Invention This invention relates to a substrate plating method, and more particularly to a substrate electrowinning method for an electroless mine connection. [Prior Art] The conventional circuit substrate includes a plating operation in the back-end process to protect the exposed metal pad or circuit and improve the soldering characteristics. Therefore, the circuit substrate is designed with an appropriate plating line or a plating lead path to facilitate plating. As the circuit board is densed and used for special purposes, the circuit board needs to add independent pads or independent lines in the section where the plating line is missing, resulting in difficulty in post plating. V'' A conventional substrate plating method, as disclosed in the Republic of China Patent Publication No. 5 93 789 唬 "Substrate Plating Process", the process comprising the steps of: providing a substrate having a completed front-end process, the substrate having a meaning The inner circuit of the board, a first surface and a corresponding one of the second surfaces, the first surface has a plurality of first contact pads and a plurality of circuit patterns, wherein the surface has a plurality of second contact pads and a plurality of lines Κ and the second surface system respectively have a solder resist layer for covering the circuit patterns. And exposing the first contact pad and the second contact pad, for the purpose of electric ore bonding, a conductive seed layer is on the first surface of the substrate, and then electroplating to form a first The metal layer and a second metal layer are on the conductive seed layer and the second contact pads, and the first metal layer and the conductive seed layer are patterned. Therefore, with respect to the electroplating process in which the electroplating line is connected, the additional conductive seed layer formation and processing steps need to be additionally added, so the manufacturing cost will be greatly increased, which is disadvantageous.
第6頁 1273147 < 案號93131283_年月曰 修正 _ 五、發明說明(2) 於大量生產。此外,該導電種子層之形成方法係為濺鍍 (sputtering)或無電電鍍(eletr〇less plating),不同於 習知地基板之電鑛(electroplating)方法,需要建購額外 的濺鐘或無電電鍍設備。 , 【發明内容】 本舍明之主要目的係在於提供一種基板電锻方法,其 係將一具有一導電面與一非導電面之導電性光阻乾膜設置 於基板上,该導電性光阻乾膜係以該導電面係貼設於該 基板,在圖案化該導電性光阻乾膜後,電鍍形成至少一金 屬層於該基板上,在無電鍍線連接下能電鍍形成複數個獨 立線路或獨立塾。 本發明之另一目的係在於提供一種基板電鍍方法,利 用一具有一導電面與一非導電面之導電性光阻乾膜,將該 V電性光阻乾膜之該導電面係貼設於一具有獨立墊或獨立 線路之基板上,在圖案化該導電性光阻乾膜後,在無電鍍 線連接下能電鍍形成至少一金屬層於該基板之獨立墊或^ 本發明之次 、㈡μ w你取扠供一等電性光阻乾膜,其 ^含有-導電感光層以及一非導電感光層該; 益+雜綠、*社電又 基板之一待電鍍表面,以在 …、迅鑛線連接下形成複數個獨立線路或獨立墊。 j明之再—目的係在於提供—導電性光阻乾膜,复 導ΐ感光層以及一非導電感光層,利用該導電 乾Μ之導電面貼設於一具有獨立墊或獨立線路之基Page 6 1273147 < Case No. 93131283_ Year Month 修正 Amendment _ V. Invention Description (2) Mass production. In addition, the method for forming the conductive seed layer is sputtering or electroless plating. Unlike the electroplating method of the conventional substrate, it is necessary to purchase an additional sputtering clock or electroless plating. device. The main purpose of the present invention is to provide a method for electrically forging a substrate by disposing a conductive photoresist film having a conductive surface and a non-conductive surface on a substrate, and the conductive photoresist is dried. The film is adhered to the substrate by the conductive surface. After the conductive photoresist dry film is patterned, at least one metal layer is plated on the substrate, and a plurality of independent lines can be formed by electroless plating. Independent. Another object of the present invention is to provide a method for plating a substrate by using a conductive photoresist film having a conductive surface and a non-conductive surface, and attaching the conductive surface of the V-electric photoresist film to the conductive surface On a substrate having a separate pad or a separate line, after patterning the conductive photoresist dry film, an electroless plating line connection can be used to form at least one metal layer on the substrate or a separate pad of the substrate, (2) μ w you take the fork for an isoelectric dry film, which contains - a conductive photosensitive layer and a non-conductive photosensitive layer; Yi + green, * social power and one of the substrate to be plated surface, in... A plurality of independent lines or independent pads are formed under the connection of the ore line. The purpose of the invention is to provide a conductive photoresist dry film, a photoconductive photosensitive layer and a non-conductive photosensitive layer, and the conductive surface of the conductive dry layer is attached to a substrate having independent pads or independent lines.
第7頁 1273147 修正 曰 Μ 虎 93131283 五、發明說明(3) 想* #以在無電鑛線連接下電鍍形成一金屬層於該基板之 询立墊或獨立線路上。 首先依t發明之基板電鑛方法’其主要包含以下的步驟; 一、胃i提供一導電性光阻乾膜,該導電性光阻乾膜係具有 板2電面以及一非導電面;設置該導電性光阻乾膜於一基 上·’ ^中該導電性光阻乾膜之導電面係貼設於該基板 ’接著’圖案化該導電性光阻乾膜,以使該導電性光阻 ^,形成一鏤空圖案;之後,藉由該導電性光阻乾膜之電 V通’電鍍形成至少一金屬層於該鏤空圖案中,以製作 2獨立線路、獨立連接墊或者是在無電鍍線連接之線路、 連接墊上電鍍形成保護金屬層。 【實施方式】 ^ 本發明之第一具體實施例,一種無電鍍線連接之基板 電錄方法,首先,請參閱第丨A圖,提供一導電性光阻乾膜 11〇 ’該導電性光阻乾膜丨1()係包含有一非導電感光層 m、一導電感光層112、一載體膜113(carrier film)及 一覆蓋膜114(cover film),該導電性光阻乾膜11〇係具有 一非導電面115及一導電面116,其中,該非導電面115係 為該非導電感光層111之一表面,該導電面116係為該導電 感光層112之一表面,該非導電面115係可不具有黏性,該 導電面11 6係具有黏性,較佳地,該導電感光層11 2之厚度 係不超過該非導電感光層111之厚度二分之一,並且該導 電感光層112之材質係包含有與該非導電感光層ill相同之 光阻物質,在本實施例中,該導電感光層丨丨2之厚度約為Page 7 1273147 Amendment 曰 虎 Tiger 93131283 V. INSTRUCTIONS (3) I want to make a metal layer on the substrate or independent line of the substrate by electroless plating. Firstly, according to the substrate electrowinning method of the invention, it mainly comprises the following steps: 1. The stomach i provides a conductive photoresist dry film having a plate 2 electric surface and a non-conductive surface; The conductive photoresist dry film is adhered to the conductive surface of the conductive photoresist film on a substrate, and then the conductive photoresist film is patterned to make the conductive light Forming a hollow pattern; thereafter, forming at least one metal layer in the hollow pattern by electro-V-plating of the conductive photoresist dry film to form 2 independent lines, independent connection pads or in electroless plating The line connecting the wires and the connection pads are plated to form a protective metal layer. [Embodiment] A first embodiment of the present invention, a substrate electro-recording method for electroless plating connection, first, referring to FIG. A, a conductive photoresist dry film 11 〇 'the conductive photoresist The dry film 丨 1 () comprises a non-conductive photosensitive layer m, a conductive photosensitive layer 112, a carrier film 113 (carrier film) and a cover film 114 (cover film), the conductive photoresist dry film 11 has A non-conductive surface 115 and a conductive surface 116, wherein the non-conductive surface 115 is a surface of the non-conductive photosensitive layer 111, and the conductive surface 116 is a surface of the conductive photosensitive layer 112, and the non-conductive surface 115 may not have The thickness of the conductive surface layer 11 is not more than one-half the thickness of the non-conductive photosensitive layer 111, and the material of the conductive photosensitive layer 112 is included. There is a photoresist material which is the same as the non-conductive photosensitive layer ill. In the embodiment, the thickness of the conductive photosensitive layer 丨丨2 is about
1273147 _案號 93131283 五、發明說明(4) 1 · 0 // m為佳;該載體膜11 3係設於該導電性光阻乾膜11 〇之 該非導電面11 5,用以承載該非導電感光層丨丨丨與該導電感 光層112,該載體膜113係可為一種PET(聚乙烯對苯二曱酸 脂)膜,該覆蓋膜11 4係設於該導電性光阻乾膜丨丨〇之該導 電面11 6 ’用以保護該非導電感光層1丨1與該導電感光層 112,該&覆蓋膜Π4係可為一種LDPE(低密度聚乙烯)膜: 请參閱第1B圖’設置該導電性光阻乾膜丨丨〇於一基板 120上,其係移除該覆蓋膜114,再將該導電性光阻乾膜 110之該導電面116貼設於該基板12〇之一上表面121,該基 板1 2 0係可為混合有玻纖布強化纖維之—環氧樹 酯或BT樹酯基板、聚醯亞胺膜、陶瓷基板、半導體基板 其它基板。 ^ 之後,圖案化該導電性光阻乾膜1 1 〇,以形成一鏤空 圖案117,其圖案化步驟說明如后,請參閱第lc圖,以二 光罩130設置於該導電性光阻乾膜11〇之該載體膜丨13上, 並曝光該導電性光阻乾膜11〇,在本實施例中,該 = 112倍'包含有與該非導電感光層1U相同之光阻物質, I使用相同之紫外光(UV light)同時對該非導電感光声 m導電感光層112進行曝光;之後,請參閱第, 二露出該導電性光阻乾膜11G之非導電面 該二,17對該Λ”生*阻乾膜110加以顯影,以形成 為線路狀凹陷’用以製作出無電鍍線連接之獨立線#路17#1273147 _ Case No. 93131283 V. Description of the invention (4) 1 · 0 // m is preferred; the carrier film 113 is disposed on the non-conductive surface 11 of the conductive photoresist film 11 , for carrying the non-conductive a photosensitive layer 丨丨丨 and the conductive photosensitive layer 112, the carrier film 113 may be a PET (polyethylene terephthalate) film, and the cover film 11 is disposed on the conductive photoresist dry film 丨丨The conductive surface 11 6 ′ is used to protect the non-conductive photosensitive layer 1丨1 and the conductive photosensitive layer 112. The & cover film 4 can be an LDPE (low density polyethylene) film: Please refer to FIG. 1B. The conductive photoresist film is disposed on a substrate 120, and the cover film 114 is removed, and the conductive surface 116 of the conductive photoresist film 110 is attached to one of the substrates 12 The upper surface 121 may be an epoxy resin or BT resin substrate, a polyimide film, a ceramic substrate, or another substrate of a semiconductor substrate in which a fiberglass reinforced fiber is mixed. After that, the conductive photoresist dry film 1 1 图案 is patterned to form a hollow pattern 117, and the patterning step is described later. Referring to FIG. lc, the photomask is disposed on the photomask. The film 11 is coated on the carrier film 13 and exposed to the conductive photoresist film 11A. In the present embodiment, the film 112b contains the same photoresist material as the non-conductive photosensitive layer 1U. The same ultraviolet light (UV light) simultaneously exposes the non-conductive photosensitive acoustic conductive layer 112; after that, please refer to the second, expose the non-conductive surface of the conductive photoresist dry film 11G. Raw* resisting dry film 110 is developed to form a line-like recess' to create an independent line of electroless plating connection #路17#
第9頁 1273147 五、發明說明(5) ----- " (independence trace) ’或者亦可製作出無電鏟線連接之 獨立墊。 請參閱第1F圖,藉由該該導電性光阻乾膜11〇之該導 電感光層112在該基板120上之電性導通,可以運用電鍍 (electroplating)技術,在該基板12〇之上表面121上^該 鏤空圖案117内電鍍形成至少一金屬層141,此時,該導電 性光阻乾膜110之非導電面115係浸置於電鍍液中,因此不 會有金屬沉積在該導電性光阻乾膜11〇上,但在該鏤空圖 案117内係能形成適當之該金屬層14ι,例如銅、鎳、金、 鋁、錫鉛或其它適當之金屬層,在本實施例中,該金屬層 14係為一銅層,其係對應於該鏤空圖案117之形狀,可構 成忒基板1 2 0之獨立線路或獨立墊。較佳地,請參閱第1 ^ 圖,藉由該導電性光阻乾膜11〇在該基板12〇上之電性導 ,,可再電鍍形成一鎳層142於該金屬層14ι上;此外,請 參閱第1H圖,可再藉由該導電性光阻乾膜11〇在該基板12〇 上之電性導通,可額外電鍍形成一金層143於該鎳層142 上,該鎳層142與該金層143可保護該金屬層141,以避免 該金屬層1 41氧化。 请麥閱第11圖,移除該導電性光阻乾膜丨丨〇,其係可 使用相同之光阻清洗劑除去該非導電感光層丨丨1與該導電 感光層112,使得該金層143、該鎳層142或該金屬層141顯 露在該基板1 2 0之該上表面1 21。 因此’在上述之基板電鍍方法中,藉由該導電性光阻 乾膜110之導電面116貼設於該基板12〇上,以該導電性光Page 9 1273147 V. Invention Description (5) ----- " (independence trace) ‘Or a separate pad with no electric shovel connection. Referring to FIG. 1F, the conductive photosensitive layer 112 of the conductive photoresist film 11 is electrically conductive on the substrate 120, and an electroplating technique may be applied on the surface of the substrate 12 121 is formed in the hollow pattern 117 to form at least one metal layer 141. At this time, the non-conductive surface 115 of the conductive photoresist film 110 is immersed in the plating solution, so that no metal is deposited on the conductive layer. The photoresist film 11 is coated, but in the hollow pattern 117, a suitable metal layer 141 such as copper, nickel, gold, aluminum, tin-lead or other suitable metal layer can be formed. In this embodiment, The metal layer 14 is a copper layer corresponding to the shape of the hollow pattern 117, and may constitute a separate line or a separate pad of the substrate 120. Preferably, referring to FIG. 1 , a nickel layer 142 can be re-plated onto the metal layer 14 by the electrical conduction of the conductive photoresist dry film 11 on the substrate 12 ;; The first layer of FIG. The metal layer 141 can be protected from the gold layer 143 to prevent oxidation of the metal layer 141. Please refer to FIG. 11 to remove the conductive photoresist dry film crucible, which can remove the non-conductive photosensitive layer 丨丨1 and the conductive photosensitive layer 112 by using the same photoresist cleaning agent, so that the gold layer 143 The nickel layer 142 or the metal layer 141 is exposed on the upper surface 121 of the substrate 120. Therefore, in the above substrate plating method, the conductive surface 116 of the conductive photoresist film 110 is attached to the substrate 12A, and the conductive light is used.
第10頁 1273147 - -~迎別283— _年月 日_修正 五、發明說明(6) ----- 阻乾膜11〇在該基板12〇上之電性導通,以在無電鍍線之連 接下可在電路基板1 20上電鍍形成預定之獨立線路或是獨 立接墊,用以運用在高密度佈線之印刷電路板、半導體基 板、陶瓷基板或BT樹脂基板等等,使得線路的設計可更加 靈活與有彈性。 ^、依本發明之第二具體實施例,請參閱第2A至%圖,其 係為:基板在另一基板電鍍製程中之截面圖。請參閱第2a 圖,首先提供一導電性光阻乾膜21(),該導電性光阻乾膜 21〇係包含有一非導電感光層2U、一導電感光層212、一' 載體膜213及一覆蓋膜214。該導電性光阻乾膜2 ίο係具有 一非導電面215及一導電面216,其中,該非導電面215係 為該非導電感光層211之一表面之,該導電面216係為該導 電感光層21 2之一表面之。該載體膜21 3係貼設於該導電性 光阻乾膜21 0之該非導電面21 5。該覆蓋膜21 4係貼設於該 導電性光阻乾膜210之該導電面216。 請參閱第2 B圖,設置該導電性光阻乾膜2 1 〇於一基板 220之上表面221,該基板220係預先設置有至少一連接墊 222或是其它導電性之墊層或線路(圖未繪出),在本實施 例中’該連接塾222係為一虛設墊(dummy pad),其係未連 接任何電鍍線;在設置該導電性光阻乾膜21 〇之過程,其 係先移除該覆蓋膜2 1 4,以該導電性光阻乾膜21 0之導電面 216緊貼於該基板220之該上表面221。 請參閱第2C圖,圖案化該導電性光阻乾膜210,以使 該導電性光Ik乾膜210形成有一鏤空圖案217,以使用相同Page 10 1273147 - -~ Welcome to 283 - _ _ _ _ _ _ 5, invention description (6) ----- resistive dry film 11 〇 electrically conductive on the substrate 12 ,, in the electroless plating line Under the connection, a predetermined independent circuit or a separate pad can be formed on the circuit substrate 120 for use in a high-density printed circuit board, a semiconductor substrate, a ceramic substrate or a BT resin substrate, etc., so that the circuit design is performed. Can be more flexible and flexible. According to a second embodiment of the present invention, please refer to FIG. 2A to FIG. 2, which is a cross-sectional view of the substrate in another substrate plating process. Referring to FIG. 2a, a conductive photoresist dry film 21 (1) is provided. The conductive photoresist dry film 21 comprises a non-conductive photosensitive layer 2U, a conductive photosensitive layer 212, a carrier film 213 and a carrier film 213. Cover film 214. The conductive photoresist film 2 has a non-conductive surface 215 and a conductive surface 216, wherein the non-conductive surface 215 is a surface of the non-conductive photosensitive layer 211, and the conductive surface 216 is the conductive photosensitive layer. 21 2 one of the surfaces. The carrier film 213 is attached to the non-conductive surface 215 of the conductive photoresist film 21 0. The cover film 214 is attached to the conductive surface 216 of the conductive photoresist film 210. Referring to FIG. 2B, the conductive photoresist dry film 2 1 is disposed on the upper surface 221 of a substrate 220. The substrate 220 is provided with at least one connection pad 222 or other conductive pads or lines. In the present embodiment, the connection port 222 is a dummy pad which is not connected to any plating line. In the process of disposing the conductive photoresist film 21, the system is not shown. The cover film 2 14 is removed first, and the conductive surface 216 of the conductive photoresist dry film 210 is in close contact with the upper surface 221 of the substrate 220. Referring to FIG. 2C, the conductive photoresist dry film 210 is patterned such that the conductive light Ik dry film 210 is formed with a hollow pattern 217 to use the same
第11頁 1273147 MM_9313^283^--年 月 曰__修正 五、發明說明(7) 之紫外光將該非導電感光層211與該導電感光層212加以圖 案化,在本實施例中,該鏤空圖案2 i 7係為區塊狀凹陷且 對準於該連接墊222,並且該導電性光阻乾膜210之導電感 光層21 2係電性耦合至該連接墊2 2 2,以供電鍍形成在該連 接墊222上之保護性金屬層。 言明蒼閱第2D與2E圖,藉由該導電性光阻乾膜21〇之該 導電感光層212在該基板220上之電性導通,電鍍形成至少 一金屬層於該鏤空圖案217内,在本實施例中,電鍍形成 在忒連接墊2 2 2上者係包含有一鎳層231與一金層232。 二請參閱第2F圖,移除該導電性光阻乾膜21〇,以使在 該連接墊222上最外層之金層232為顯露,此, %圖,可在該基板220之上表面221係覆蓋有一防銲層閱第 240,該防銲層24〇可形成在該導電性光阻乾膜2ι〇之移除 v驟之後’或者預先形成在該導電性光阻乾膜21 〇之 步驟之前。運用上述之基板電鍍方法,可在一基^ 連接墊或是獨立線路上任意電鍍形成適當之金^層。 本發明之保護範圍當視後附之申 為準,任何熟知此項技藝者,在不脫離= 圍内所作之任何變化與修改,均屬於本發明之保護範圍。巳Page 11 1273147 MM_9313^283^--Yearly 曰__ Amendment 5, the ultraviolet light of the invention (7), the non-conductive photosensitive layer 211 and the conductive photosensitive layer 212 are patterned, in the present embodiment, the hollowing out The pattern 2 i 7 is a block-shaped recess and is aligned with the connection pad 222 , and the conductive photosensitive layer 21 2 of the conductive photoresist film 210 is electrically coupled to the connection pad 2 2 2 to form a power supply plating. A protective metal layer on the connection pad 222. In the second and second embodiments, the conductive photosensitive layer 212 of the conductive photoresist film 21 is electrically connected to the substrate 220, and at least one metal layer is formed in the hollow pattern 217 by electroplating. In this embodiment, the plating is formed on the tantalum connection pad 22 and includes a nickel layer 231 and a gold layer 232. 2, referring to FIG. 2F, the conductive photoresist dry film 21 is removed, so that the outermost gold layer 232 on the connection pad 222 is exposed. Thus, the % map can be on the upper surface 221 of the substrate 220. Covering a solder mask layer 240, the solder resist layer 24 can be formed after the step of removing the conductive photoresist film 2m, or preformed in the conductive photoresist film 21 prior to. By using the above substrate plating method, an appropriate gold layer can be formed by electroplating on a substrate or a separate line. The scope of the present invention is defined by the appended claims, and any changes and modifications made by those skilled in the art without departing from the scope of the invention are within the scope of the invention.巳
' 1273147' 1273147
【圖式簡軍說明】 第1 A至1 I圖··依掳士炊 基板電鍍過程中之截二_=第一具體實施例,一基板在一 心戰面不意圖;及 第2A至2G圖·•依擋太汰口口 _ 1^ Φ % 4 ^本务月之第二具體實施例,另一基板在 一基板電鍍過程中之截面示意圖。 元件符號簡單說明: 11 0導電性光阻乾厘 111非導電感光層i i 2 114覆蓋膜 117鏤空圖案 120基板 121 130 光罩 141金屬層 142 21 0導電性光阻乾膜 211非導電感光層212 214覆蓋膜 215 21 7鏤空圖案 2 2 0基板 221 231鎳層 232 240 防銲層 導電感光層 113 載體膜 非導電面 116 導電面 上表面 鎳層 143 金層 導電感光層 213 載體膜 非導電面 216 導電面 上表面 222 連接墊 金層[Illustration of the diagram] 1A to 1 I············································· ·• 太 汰 口 _ 1 ^ Φ % 4 ^ The second specific embodiment of the current month, another substrate in a substrate plating process schematic diagram. Brief description of the components: 11 0 conductive photoresist dry 111 non-conductive photosensitive layer ii 2 114 cover film 117 hollow pattern 120 substrate 121 130 photomask 141 metal layer 142 21 0 conductive photoresist dry film 211 non-conductive photosensitive layer 212 214 cover film 215 21 7 hollow pattern 2 2 0 substrate 221 231 nickel layer 232 240 solder resist layer conductive photosensitive layer 113 carrier film non-conductive surface 116 conductive surface surface nickel layer 143 gold layer conductive photosensitive layer 213 carrier film non-conductive surface 216 Conductive surface 222 is connected to the gold layer
第13頁Page 13
Claims (1)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW93131283A TWI273147B (en) | 2004-10-15 | 2004-10-15 | Method for plating on a substrate and conductive dry film used in the method |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW93131283A TWI273147B (en) | 2004-10-15 | 2004-10-15 | Method for plating on a substrate and conductive dry film used in the method |
Publications (2)
Publication Number | Publication Date |
---|---|
TW200611997A TW200611997A (en) | 2006-04-16 |
TWI273147B true TWI273147B (en) | 2007-02-11 |
Family
ID=38621385
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW93131283A TWI273147B (en) | 2004-10-15 | 2004-10-15 | Method for plating on a substrate and conductive dry film used in the method |
Country Status (1)
Country | Link |
---|---|
TW (1) | TWI273147B (en) |
-
2004
- 2004-10-15 TW TW93131283A patent/TWI273147B/en not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
TW200611997A (en) | 2006-04-16 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
TWI286372B (en) | Semiconductor package substrate with protective metal layer on pads formed thereon and method for fabricating the same | |
TWI246753B (en) | Package substrate for electrolytic leadless plating and manufacturing method thereof | |
TW200806138A (en) | Method for manufacturing wiring board | |
US20130062106A1 (en) | Printed Circuit Board and Method of Manufacturing the Same | |
TW201025529A (en) | Substrate structure and manufacturing method thereof | |
JP4087080B2 (en) | Wiring board manufacturing method and multichip module manufacturing method | |
TWI293856B (en) | Substrate manufacturing method and circuit board | |
CN103098565B (en) | Substrate having built-in components | |
TW200537999A (en) | Fabrication method of a printed circuit board | |
TWI273147B (en) | Method for plating on a substrate and conductive dry film used in the method | |
CN111837210A (en) | Wiring substrate and method for manufacturing same | |
CN111343802B (en) | Circuit board and manufacturing method thereof | |
TWI525226B (en) | Electrolytic gold or gold palladium surface finish application in coreless substrate processing | |
JP2009177022A (en) | Plating film, method for manufacturing plating film, wiring board, and method for manufacturing wiring board | |
CN101552211A (en) | Composite metal substrate and process thereof | |
KR101313155B1 (en) | Plating Method for PCB and Method for Manufacturing Flexible PCB Using the Same | |
JP4033090B2 (en) | Manufacturing method of tape carrier for semiconductor device | |
CN111863633B (en) | Package carrier, package and process thereof | |
JP4142933B2 (en) | Wiring board manufacturing method | |
JP2005340866A (en) | Wiring board | |
KR101008422B1 (en) | Printed circuit board manufacturing method | |
JP4139185B2 (en) | Wiring board manufacturing method | |
TWI245355B (en) | Formation method of conductor pattern | |
JP2004165575A (en) | Method of manufacturing wiring board | |
TWI247363B (en) | A substrate structure having solid micro vias and manufacture method thereof |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
MM4A | Annulment or lapse of patent due to non-payment of fees |