TWI245355B - Formation method of conductor pattern - Google Patents

Formation method of conductor pattern Download PDF

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Publication number
TWI245355B
TWI245355B TW93123335A TW93123335A TWI245355B TW I245355 B TWI245355 B TW I245355B TW 93123335 A TW93123335 A TW 93123335A TW 93123335 A TW93123335 A TW 93123335A TW I245355 B TWI245355 B TW I245355B
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TW
Taiwan
Prior art keywords
wiring
layer
forming
patterning
layers
Prior art date
Application number
TW93123335A
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Chinese (zh)
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TW200607029A (en
Inventor
Ryoichi Toyoshima
Original Assignee
Nippon Mektron Kk
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Publication of TWI245355B publication Critical patent/TWI245355B/en
Publication of TW200607029A publication Critical patent/TW200607029A/en

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  • Manufacturing Of Printed Wiring (AREA)
  • Non-Metallic Protective Coatings For Printed Circuits (AREA)
  • Formation Of Insulating Films (AREA)

Abstract

The present invention provides a formation method of conductor pattern, which includes steps of forming a 1st patterning layer 2 on an insulating substrate 1; forming a 1st patterning passivation layers 3 outside the 1st patterning layer 2 by providing necessary gap with the 1st patterning layers 2; then comprehensively forming a semiconductor layers 4 which are made thicker than the top end of the 1st patterning protection layers 3, subsequently using a mask material to remove the unnecessary portion of the semiconductor layer 4 after completely polishing the top side of the semiconductor layers 4 to form a 2nd patterning layers 6, optionally forming a 2nd patterning passivation layers 7 on the 2nd patterning layer 6.

Description

1245355 九、發明說明: 【發明所屬之技術領域】 ^本發明係關於電路佈線之形成方法,更詳細地說,本 發2係關於可以製造適用於電機、電子機器之小型輕量化 之電路基板或電路元件之電路佈線之形成方法。 【先前技術】 為達到包機、電子機器之更加小型輕量化之要求,電 中所眉之佈線挽度年年增高。因應此要求,為提昇每單 位面積之佈線量的佈線年年細微化。 為了佈線之細微化,使用減去法(Subtractive Method) :以將佈線厚度變薄’且作為遮罩之阻劑亦可薄膜化。此 夕:,使用半加成法(Semiadditive Meth〇d)可在不提高直流 電阻值而形成微細的佈線。 :而’減去法中之抗钱層。戈半加成法中之防鍍層係 :方式形成’因此曝光時之異物、阻劑中之氣泡, :形成時之異物等皆會成為不良之原目"寺別是在微 :广’此問題將變得更為顯著,因此必須要有嚴格之管 d $路基板中’纟動元件或是主動元件之構裝是不可缺 ^。-件構袈時’會使用焊料或金引線 小型化與1/〇端子之高密度化,亦使用ACF與NCP等。 u/而1上述方式進行構實料,心必須在元件盘 形成焊料或金等之突塊、或在使用金引線等時: Μ保配線所須之空間’因此電路基板將會變厚, 1245355 元件製造、電路基板之p W幻$〜構裝等的製程數亦多。 光微影製程、或佈線形成 化中雖會變得顯著,,曰可择/、物寻之問題在微細 寬來減輕此問題。 …布線間隔或是佈線寬度加 因此,本發明之電路佈 材上形成第一佈線層,接著係於絕緣性基 線層間具有間隙之方式形成二佈線層之外面以該配 面形成較第一佈線保護層之上俨 冉方…、上王 _層之上面對全面進行研磨: 以形成第二佈線層。 由除去不要的Β 絕緣:二:第一佈線保護層係使用能僅在佈線周圍形成 ;方=著性絕緣樹脂,空隙部之樹脂則係使用以光微 〜方式除去之感光性絕緣樹脂。 絕緣樹脂後,使用乾式或 亦可在王面地形成 隙。 飞^濕式蝕刻法來在佈線間形成空. 卜S對全面㈣之導體層進行研磨a夺,研磨至第 呆護層之上端’藉由在第二佈線層形成後在該佈線 曰广成保達層,即能形成較第一佈線層更高密度之電路基 处由於第一、第二線層皆不需要微細之佈線形成製程, 因此能以高良率製造高密度佈線。 又’在對全面形成之導體層進行研磨時,研磨至第一 佈線上端’在第二佈線層形成後,例如藉由在既定處形成 \製作元件,即不需要構裝製程而能製造薄型的構 1245355 裝電路基板。 【實施方式】 圖1為本發明一實施例之電路佈線的形成製程圖。首 先’如該圖(1)所示’在絕緣性基材1上形成第一佈線層2。 此時,亦同時地形成用以在電鍍時通電之引線。此處之佈 線層2,可使用減去法、半加成法或在其他可剝離之基材 上形成佈線,然後轉印至該絕緣性基材丨上等之方法形^。 接著,如該圖(2)所示,以電鍍方法將聚醯亞胺樹脂、 %氧樹脂或氟樹脂等具有絕緣性之樹脂膜析出至佈線層2 外面,據以形成第一佈線保護層3。 此時,為形成與其他元件或基板等連接用之端子,係 預先使用如乾膜等非導電性、可除去之膜加以遮蔽,並在 電錢後除去’或是在電鑛後以雷射、電漿或負離子钱刻等 乾式或樹脂蝕刻液等化學性濕式蝕刻方式,來形成 部。 接著如該圖(3)所示,以無電解鑛等方法對絕緣性基材 1之佈、㈣2存在之面全面進行導電化後,以電解銅鍵等 方法形成較佈線保護層3上端高的導體層4。此時,導體 層4可選擇銅等能以蝕刻等方法加以除去之金屬。 之後,如該圖⑷所示,將導體層4研磨至第一佈線保 娜h之上知it步的’如該圖⑺所示,僅將所需之導 ::以乾膜等可除去、且在除去導…時不會被侵姓之 =罩材5加以覆蓋,藉由除去導體層4之不需要的部分, 來形成第二佈線層6。 !245355 最後,如該圖(6)所示,形成第二佈線保護層7。此時, 佈線保護;| 7所覆蓋之範圍,除了端子部之開口之外,沒 有特別之規定。藉由此等製帛’即能獲得到發明目的之電 路基板。 根據本餐明’可不使用微細電路佈線形成技術而能形 成微細之佈線。因此,能以高良率製造高密度之電路基板。 此外,藉由研磨至第一佈線層,在其上例如形成液晶 件等’ $需構裝製程、且不需為與元件連接之焊料 突塊或引線之配線所需空間’即能製造薄高密度之元 件構裝電路基板。 本發明可以在電機、電子 、縮短製程所得之低價袼 藉由此等製法上之優越性, 製品之小型輕量化,特別是良率 化有所貢獻。 【圖式簡單說明】 以說明本發明一實施例之電路佈 第以1)〜(6)圖,係用 線形成法的製程圖。 【主要元件符號說明】 1 絕緣性基材 第一佈線層 3 第一佈線保護層 導體層 遮罩材 第二佈線層 第二佈線保護層 71245355 IX. Description of the invention: [Technical field to which the invention belongs] ^ The present invention relates to a method for forming circuit wiring. More specifically, the present invention 2 relates to a circuit board or Method for forming circuit wiring of circuit element. [Previous technology] In order to meet the requirements of more compact and lightweight charter aircraft and electronic equipment, the wiring pull of electric power plants has been increasing year by year. In response to this requirement, the wiring has been refined year by year in order to increase the wiring amount per unit area. In order to miniaturize the wiring, a Subtractive Method is used: to reduce the thickness of the wiring 'and use it as a masking resist. In this case, the semi-additive method can be used to form fine wiring without increasing the DC resistance value. : And ’minus the anti-money layer in the method. The anti-plating layer in the Ge semi-additive method: the way to form 'so foreign matter during exposure, bubbles in the resist,: foreign matter when forming, etc. will become the original purpose of the bad " Temple is in the micro: Guang' this The problem will become more significant, so it is necessary to have a strict control of the structure of the 'moving component' or the active component in the substrate. -In the case of component structure, solder or gold leads are used for miniaturization and high density of 1 / 〇 terminals, and ACF and NCP are also used. u / 1 The above method is used to construct the actual material. The core must be formed with solder or gold bumps on the component board, or when using gold leads, etc .: The space required for wiring is guaranteed. Therefore, the circuit board will become thicker, 1245355 There are also many manufacturing processes such as component manufacturing and circuit board assembly. Although the photolithography process or the formation of wiring will become significant, the problem of optional / physical search is narrowed to reduce this problem. ... the wiring interval or the wiring width is increased. Therefore, a first wiring layer is formed on the circuit cloth material of the present invention, and then the outer surface of the two wiring layers is formed in a manner with a gap between the insulating baseline layers. Ranfang on the protection layer ..., the upper surface of the upper layer is fully polished: to form a second wiring layer. The unnecessary B insulation is removed: two: the first wiring protective layer is formed only around the wiring; the square = an insulating insulating resin, and the resin in the void portion is a photosensitive insulating resin that is removed in a light-to-light manner. After the insulating resin is used, a dry type or a gap can be formed in the king surface. Fly ^ wet etching to form voids between the wirings. The polishing of the entire conductor layer is performed to the upper end of the first protective layer. By forming the second wiring layer in the wiring, Baoda layer, that is, a circuit base that can form a higher density than the first wiring layer. Because neither the first nor the second wire layer requires a fine wiring formation process, high-density wiring can be manufactured with a high yield. Also, "when polishing the fully formed conductor layer, it is polished to the upper end of the first wiring". After the second wiring layer is formed, for example, by forming / producing elements at predetermined locations, it is possible to manufacture a thin type without a fabrication process. Structure 1245355 is mounted on the circuit board. [Embodiment] FIG. 1 is a manufacturing process diagram of a circuit wiring according to an embodiment of the present invention. First, as shown in the figure (1), a first wiring layer 2 is formed on an insulating base material 1. At this time, a lead for energizing during plating is also formed at the same time. Here, the wiring layer 2 can be formed by a subtractive method, a semi-additive method, or forming a wiring on another peelable substrate, and then transferring it to the insulating substrate. Next, as shown in the figure (2), an insulating resin film such as polyimide resin,% oxygen resin, or fluororesin is deposited on the outside of the wiring layer 2 by a plating method, thereby forming a first wiring protection layer 3. . At this time, in order to form a terminal for connection with other components or substrates, a non-conductive, removable film such as a dry film is used to cover it in advance, and it is removed after the electricity is charged, or it is lasered after the power mine. Chemically dry etching methods such as plasma, negative ion money engraving, or chemical wet etching methods such as resin etching solution are used to form the part. Then, as shown in the figure (3), the entire surface of the insulating substrate 1 and the ㈣ 2 are electrically conductive by methods such as electroless ore, and then are formed higher than the upper end of the wiring protection layer 3 by methods such as electrolytic copper bonding. Conductive layer 4. In this case, the conductor layer 4 can be selected from metals such as copper that can be removed by etching or the like. After that, as shown in the figure ,, the conductor layer 4 is ground to the first wiring 娜 a. As shown in the figure 仅, only the required guides can be removed with a dry film, etc., In addition, the second wiring layer 6 is formed by removing unnecessary portions of the conductive layer 4 when the guide is removed. ! 245355 Finally, as shown in the figure (6), a second wiring protection layer 7 is formed. At this time, the wiring protection; | 7 covers the area, except for the opening of the terminal section, there are no special provisions. By preparing the substrates in this way, the circuit substrate for the purpose of the invention can be obtained. According to the present invention, fine wiring can be formed without using a fine circuit wiring forming technique. Therefore, a high-density circuit board can be manufactured with a high yield. In addition, by grinding to the first wiring layer, for example, a liquid crystal device is formed thereon. “It requires a fabrication process and does not need space for the wiring of solder bumps or leads connected to the component.” The density element constitutes a circuit board. The present invention can contribute to the low price of motors, electronics, and shortened manufacturing processes. With the superiority of these manufacturing methods, the products can be made smaller and lighter, and especially contribute to yield. [Brief description of the drawings] To illustrate the circuit layout of an embodiment of the present invention, the drawings 1) to (6) are process drawings using a wire forming method. [Description of main component symbols] 1 Insulating substrate First wiring layer 3 First wiring protection layer Conductor layer Masking material Second wiring layer Second wiring protection layer 7

Claims (1)

1245355 十、申請專利範圍: 1· 一種電路佈線之 〈小成法,其特徵在於: 於絕緣性基材上形成 μ 成弟一佈線層,接著在該第一佈線 看之外面以该配線層間且 声,A你甘t«入 八有二隙之方式形成第一佈線保護 、 子乂弟怖線保蠖層之上端厚的導體 層’並進一步從該導體声 3之上面對全面進行研磨後,藉由 除去不要的部分以形成第二佈線層。 2·如申請專利範圍第 ^ 固乐1項之電路佈線之形成法,其中, 係猎由將該第一佈線;却·中炎y士 A 吓深層e又疋為期望佈線間距的一倍,以有 效率地形成微細佈線。 3 ·如申凊專利範圍第丨或2項之電路佈線之形成法, 其中,該研磨係進行至該第一佈線保護層,除去不要之導 體部後’形成該第二佈線保護層。 4 ·如申請專利範圍第1或2項之電路佈線之形成法, 其中,該研磨係進行至該第一佈線層上端,並在此佈線層 上形成元件。 十一、圖式: 如次頁 91245355 10. Scope of patent application: 1. A method of circuit wiring, which is characterized in that: a wiring layer is formed on an insulating substrate, and then the wiring layer is placed between the wiring layer and the outer surface of the first wiring. Sound, A you Gan t «into the gap there are two ways to form the first wiring protection, the thick conductor layer on the top of the wire protection layer ', and further grinding from the surface of the conductor 3 By removing unnecessary portions, a second wiring layer is formed. 2. If the method of forming a circuit wiring of item No. ^ Gule 1 is formed, the first wiring is used for this purpose; however, the middle layer y is a scared deep layer e which is twice the expected wiring pitch. To form fine wiring efficiently. 3. The method of forming a circuit wiring according to the item No. 1 or 2 of the patent application scope, wherein the polishing is performed to the first wiring protection layer, and the second wiring protection layer is formed after removing unnecessary conductor portions. 4. The method for forming a circuit wiring according to item 1 or 2 of the scope of patent application, wherein the polishing is performed to the upper end of the first wiring layer, and an element is formed on the wiring layer. XI. Schematic: as next page 9
TW93123335A 2003-06-11 2004-08-04 Formation method of conductor pattern TWI245355B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2003166153A JP4115342B2 (en) 2003-06-11 2003-06-11 Forming circuit wiring

Publications (2)

Publication Number Publication Date
TWI245355B true TWI245355B (en) 2005-12-11
TW200607029A TW200607029A (en) 2006-02-16

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TW93123335A TWI245355B (en) 2003-06-11 2004-08-04 Formation method of conductor pattern

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JP4115342B2 (en) 2008-07-09
TW200607029A (en) 2006-02-16
JP2005005422A (en) 2005-01-06

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