TWI266337B - Efficient register for additive latency in DDR2 mode of operation - Google Patents

Efficient register for additive latency in DDR2 mode of operation

Info

Publication number
TWI266337B
TWI266337B TW094125548A TW94125548A TWI266337B TW I266337 B TWI266337 B TW I266337B TW 094125548 A TW094125548 A TW 094125548A TW 94125548 A TW94125548 A TW 94125548A TW I266337 B TWI266337 B TW I266337B
Authority
TW
Taiwan
Prior art keywords
latency
additive latency
register
chain
additive
Prior art date
Application number
TW094125548A
Other languages
English (en)
Other versions
TW200632937A (en
Inventor
Jon Faue
Craig Barnett
Original Assignee
Promos Technologies Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Promos Technologies Inc filed Critical Promos Technologies Inc
Publication of TW200632937A publication Critical patent/TW200632937A/zh
Application granted granted Critical
Publication of TWI266337B publication Critical patent/TWI266337B/zh

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/1066—Output synchronization
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/18—Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals
TW094125548A 2005-03-03 2005-07-28 Efficient register for additive latency in DDR2 mode of operation TWI266337B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US11/071,852 US7251172B2 (en) 2005-03-03 2005-03-03 Efficient register for additive latency in DDR2 mode of operation

Publications (2)

Publication Number Publication Date
TW200632937A TW200632937A (en) 2006-09-16
TWI266337B true TWI266337B (en) 2006-11-11

Family

ID=36947091

Family Applications (1)

Application Number Title Priority Date Filing Date
TW094125548A TWI266337B (en) 2005-03-03 2005-07-28 Efficient register for additive latency in DDR2 mode of operation

Country Status (3)

Country Link
US (1) US7251172B2 (zh)
CN (1) CN100524514C (zh)
TW (1) TWI266337B (zh)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100733420B1 (ko) * 2005-06-30 2007-06-29 주식회사 하이닉스반도체 동기식 반도체 메모리 장치
KR100753081B1 (ko) * 2005-09-29 2007-08-31 주식회사 하이닉스반도체 내부 어드레스 생성장치를 구비하는 반도체메모리소자
KR101145784B1 (ko) * 2010-10-11 2012-05-17 에스케이하이닉스 주식회사 반도체 메모리 장치 및 그를 포함하는 메모리 시스템
CN103050146B (zh) * 2013-01-11 2015-09-16 昆山慧凝微电子有限公司 高占空比ddr2数字延迟链电路
CN107230491B (zh) * 2017-06-06 2020-09-04 上海兆芯集成电路有限公司 储存装置的控制方法

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US4954325A (en) * 1986-07-29 1990-09-04 Mobil Oil Corp. Composition of synthetic porous crystalline material, its synthesis and use
US5250277A (en) * 1991-01-11 1993-10-05 Mobil Oil Corp. Crystalline oxide material
US5827491A (en) * 1993-04-26 1998-10-27 Mobil Oil Corporation Process for preparing the synthetic porous crystalline material MCM-56
ES2124154B1 (es) * 1995-11-08 1999-12-01 Univ Politecnica De Valencia C Metodo de preparaciion y propiedades cataliticas de un solido microporoso con alta superficie externa.
US6292428B1 (en) * 1998-02-03 2001-09-18 Fujitsu Limited Semiconductor device reconciling different timing signals
US6205062B1 (en) * 1998-11-13 2001-03-20 Hyundai Electronics Industries Co. Ltd. CAS latency control circuit
US6169702B1 (en) * 1999-05-26 2001-01-02 Lockheed Martin Corporation Memory device having a chip select speedup feature and associated methods
US6504767B1 (en) * 2000-08-30 2003-01-07 Micron Technology, Inc. Double data rate memory device having output data path with different number of latches
US6434082B1 (en) 2001-03-13 2002-08-13 International Business Machines Corporation Clocked memory device that includes a programming mechanism for setting write recovery time as a function of the input clock
US6757857B2 (en) * 2001-04-10 2004-06-29 International Business Machines Corporation Alternating current built in self test (AC BIST) with variable data receiver voltage reference for performing high-speed AC memory subsystem self-test
US6542416B1 (en) 2001-11-02 2003-04-01 Rambus Inc. Methods and arrangements for conditionally enforcing CAS latencies in memory devices
MXPA04004180A (es) * 2001-11-06 2004-09-06 Wyeth Corp Proceso para la preparacion de cloruros de 2-(alquil(aril)(sulfonilbencenosulfonil y sus intermedarios.
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US6714462B2 (en) * 2002-08-29 2004-03-30 Micron Technology, Inc. Method and circuit for generating constant slew rate output signal
JP4570321B2 (ja) * 2002-10-29 2010-10-27 ルネサスエレクトロニクス株式会社 半導体記憶装置
KR100507874B1 (ko) * 2002-10-30 2005-08-17 주식회사 하이닉스반도체 클럭 동기화 회로를 구비한 동기식 반도체 메모리 장치 및클럭 동기화 회로의 클럭 트리 온/오프 제어회로
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US7054222B2 (en) * 2004-07-19 2006-05-30 Micron Technology, Inc. Write address synchronization useful for a DDR prefetch SDRAM
US7061823B2 (en) * 2004-08-24 2006-06-13 Promos Technologies Inc. Limited output address register technique providing selectively variable write latency in DDR2 (double data rate two) integrated circuit memory devices

Also Published As

Publication number Publication date
US20060209618A1 (en) 2006-09-21
CN100524514C (zh) 2009-08-05
CN1828770A (zh) 2006-09-06
TW200632937A (en) 2006-09-16
US7251172B2 (en) 2007-07-31

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