TWI264071B - Method for fabricating a sublithographic gate structure for field-effect transistors, an associated field-effect transistor and an associated inverter, and associated inverter structure - Google Patents
Method for fabricating a sublithographic gate structure for field-effect transistors, an associated field-effect transistor and an associated inverter, and associated inverter structure Download PDFInfo
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28123—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects
- H01L21/2815—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects part or whole of the electrode is a sidewall spacer or made by a similar technique, e.g. transformation under mask, plating
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823418—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
- H01L21/823425—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures manufacturing common source or drain regions between a plurality of conductor-insulator-semiconductor structures
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
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- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823468—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28114—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor characterised by the sectional shape, e.g. T, inverted-T
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
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- Condensed Matter Physics & Semiconductors (AREA)
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Abstract
Description
1264071 本發明關於一種 構，一相關聯之場致 及關於——反向器結構 造方法，用於製造一次微影閘極結 電晶體以及一相關聯之£向器，以 並且特別地闕於一種用於製造次微 金 閘怪的方法、其具有一閘極長度低於1 U (J奈来的 奈 作為阻 術的 米範 阻抗 滿足 新的 本的 一種 法， 輔助 罩被 I虫亥J 法轉 〇 所稱 近一 圍。 材料 技術 用於 。高 因此 替代 如使 層， 力ϋ以 方法 移至 的微影 米範圍 化學， 作為1 步發、展 , 不論 的要求 遮罩之 成本並 ，所稱 此種便 用一種 所述辅 移除， 。這獲 一閘極 方法 ，產 遮罩 5 7 ， 而 例子 大部 關於 製造 且很 作為 利最 便利 助層 並且 得次 的發 生特 之製 奈米 用於 中， 份徹 玫匕小 亦同 困難 次微 適微 的光 非等 於是 微影 用於 展，鸬 別大的造，以 之微影 製造非 這些微 底盡力 結構。 時需要 管理微 影之方 影技術 阻劑， 方向性 減少尺 遮罩結 形成有 於製造非 問題，特 及複雜的 技術已經 常好的結 影技術的 ，無阻抗 在者，除 ，並且他 影系統因 法已經被 方法。在 一種結構 地被加以 寸，其係 構而；|ij用 如次微影 常好的 別是導 微影系 達成光 構於次 方法要 已被發 了這些 們的發 此所得 力口以導 這些次 被加以 蝕刻， 利用一 習慣用 閘極結 結構於次 致由所稱 統。 學微影技 1〇〇奈 术新賴的 現完全地 新材料， 展是高成 的結果。 入而作為 微影方 成像在一 該阻抗遮 種等向性 的敍刻方 構之目 利闬相同白勺方 此種次 遮置結構同時能夠利用1264071 The present invention relates to a configuration, an associated field and related-inverter structure fabrication method for fabricating a lithography gate junction transistor and an associated viater, and particularly A method for manufacturing a sub-micro-Golden Gate Monster, which has a gate length of less than 1 U (J Nai Nai as a resistance to the M-Vian impedance to satisfy a new method, the auxiliary cover is I The method is called “next to the circumference.” Material technology is used for high. Therefore, instead of the layer, the force is moved to the lithography range of the chemical, as a one-step development, regardless of the cost of the mask required. This is referred to as a kind of auxiliary removal, which is a gate method that produces a mask 57, and most of the examples are about manufacturing and are very convenient for the most convenient layer. When rice is used in the middle, the light that is small and the same as the difficulty is not equal to the lithography used for exhibition, and the large-scale creation is made. Shadow side Technical resistance, directional reduction ruler mask formation is not problematic in manufacturing, special and complex technology has been often good for the junction technology, no impedance, except, and the shadow system has been the method. A structure is sized, and its structure is used; |ij is used as a sub- lithography, and the lithography system is used to achieve the light structure in the secondary method. The second time is etched, using a habitual gate junction structure for the secondary system. The lithography technology 1 〇〇奈术新赖's completely new material, the exhibition is the result of Gao Cheng. The image of the shadow is in the same direction as the impedance of the impedance occlusion, and the sub-shielding structure can be utilized at the same time.
第6頁 1264071 L '铃叫說叫：'Page 6 1264071 L 'The bell is called: '
所稱作間隙物方法被加以形成，首先地，一第一遮罩帶有 實質地垂直的（則璧正被加以形成‘·並且已被加以刻劃有圖 案，其經常地係利用光學的微影技銜來達成。之後，一非 當薄的進一步遮罩層被加以沉積在該第一遮罩表面上覆蓋 整個面積而達到預估的厚度。該進一步的遮罩層之水平層 區域隨即地利用非等方向性蝕刻方法被加以移除，使得只 有一次彳敗影遮罩保持在該第一遮罩的惻壁。最後地，該第 一遮罩被加以移除並且唯一的帶有其預估厚度以及閘極長 度之次微影遮罩，被加以轉印至該構成基底的下層閘極 層，而用於形成一次微影閘極結構的目的。 然而，在此種習用方法的缺點是在利用此種方式所加 以形成之該次微影閘極結構中臨界尺寸不合意的變異，而 這實質地起源於所被加以使用的阻抗材料，所使用的該阻 抗化學以及所使用的該.14刻加工程序。A so-called spacer method is formed, firstly, a first mask with substantially vertical (ie, 璧 is being formed '· and has been scribed with a pattern, which often utilizes optical micro The shadow mask is achieved. Thereafter, a non-thin thin further mask layer is deposited on the first mask surface to cover the entire area to reach a predicted thickness. The horizontal layer region of the further mask layer is immediately It is removed by an unequal etch method such that only one smash mask remains on the dam of the first mask. Finally, the first mask is removed and uniquely The sub-lithographic mask of the estimated thickness and the gate length is transferred to the lower gate layer constituting the substrate for the purpose of forming a lithography gate structure. However, the disadvantage of this conventional method is An undesired variation in critical dimension in the lithography gate structure formed by such a method, which essentially originates from the impedance material used, the impedance chemistry used, and the used. 14 engraving process.
隨著進階積體密度，然而，具有例如小於1 0 0奈米 (如，2 5奈米）之一閘極長度的半導體結構增加地被加 以要求並且被加以獲得。該閘極長度實現具有對一半導體 物件之電學性質一有意義的影響。再者，具有增加的需要 去積分此種在一慣用的標準加工程序中次微影’’短通 道…閘極結構，而用於製造微影技術所形成之…長通 道…閘極結’構，例如，為了能夠形成在該半導體模組上類 比電路以及數位邏輯電路之積體電路。 因此，本發明基於提供一種製造方法的目的，來製造 一次微影閘極結構，一所相關聯的場效應電晶體以及一所With advanced bulk density, however, semiconductor structures having a gate length of, for example, less than 100 nm (e.g., 25 nm) are incrementally required and obtained. This gate length realization has a significant impact on the electrical properties of a semiconductor article. Furthermore, there is an increased need to integrate such a sub-lithography ''short channel...gate structure in a conventional standard processing procedure, and used to fabricate lithography techniques...long channel...gate junction structure For example, in order to form an integrated circuit of an analog circuit and a digital logic circuit on the semiconductor module. Accordingly, the present invention is based on the object of providing a fabrication method for fabricating a primary lithography gate structure, an associated field effect transistor, and a
第7頁 1264071 相關聯的反向器，以及一反向器結構，實現於臨界尺寸以 反特別是間極正被加以減少，並且一與慣闬的方法所相結 合而用於製造微影技衔閘極結構，而正利用簡單的方式可 能被加以製作。 揋據本發明，藉由如申請專利範圍第1項，第1 5 項，以及第1 6項所相關的方法量測並且藉由如申請專利 範圍第7項所相關反向器結構之特徵而被加以達成目的。Page 7 1264071 The associated inverter, as well as an inverter structure, is implemented in a critical dimension to be reduced, especially in particular, and is used in conjunction with conventional methods for manufacturing lithography. The gate structure is being made and can be made in a simple way. According to the present invention, it is measured by the method related to the first, fifth, and sixth aspects of the patent application and by the features of the inverter structure as claimed in claim 7 Be made to achieve the goal.
特別地^利用帶有貫質地在一半導體基材表面垂直的 •ί則壁之一微影技術所刻劃有圖案之遮罩的形成優點，可能 隨即至少在該半導體基材表面構造性形成一閘極絕緣層， 以及隨即至少在該閘極絕緣層與遮罩的側壁表面構造性形 成一閘極層。在包含進行一等方向性I虫刻方法以及移除該 遮罩之後，製造次微影閘極結構，而其帶有小的臨界尺寸 以及不帶有直接地由一閘極層而來的額外轉印步驟，於是 導致一已被加以改善而與慣用製造微影技術閘極結構方法 的結合。特別地所被加以使用於邏輯電路中之次微影閘極 結構於是能夠利用相同的製造方法以特別地簡單的方式被 加以形成，而帶有以微影技術所形成之平常閘極結構，優 選地被加以使用於類比電路中。In particular, the use of a mask having a pattern etched by a lithography technique that is perpendicular to the surface of a semiconductor substrate, may be formed at least on the surface of the semiconductor substrate. A gate insulating layer, and then a gate layer is formed constructively at least on the sidewall of the gate insulating layer and the mask. After the method of performing the unidirectional I insect engraving and removing the mask, the sub-lithographic gate structure is fabricated with a small critical dimension and without additional extra directly from a gate layer The transfer step thus results in a combination of methods that have been improved and conventionally used to fabricate lithography gate structures. In particular, the sub-lithographic gate structure used in the logic circuit can then be formed in a particularly simple manner by the same manufacturing method, with a normal gate structure formed by lithography, preferably Ground is used in analog circuits.
特別地，當使用一用失層之金屬材料時，可能對於第 一時間之次微影技術金屬閘極結構直接地i加以形成，結 果該場效應電晶體之電性性質能夠充分地被加以改善。 該閘極層優選地具有一帶有調節閘極層之複數序列， 其直接地被加以形成在該閘極絕緣層上，並且用作為調節In particular, when a metal material of a lost layer is used, it is possible to directly form a metal gate structure of the lithography technique for the first time, and as a result, the electrical properties of the field effect transistor can be sufficiently improved. . The gate layer preferably has a complex sequence with a regulated gate layer that is directly formed on the gate insulating layer and used as an adjustment
第8頁 1264071 ^碑說明 又 善 應 場 個 入 該個羽半導體材料以及一優選的金屬所使用之該閘極層 隨唆钙色惶；問怪..f在其上被加以形成〃 的閘極絕緣層優選地為一氧ft龄，一氧氮化物 具有一相對高介電當數之電分質，在例子中， 有具有一高相對電容率之電介質忖料，有可能 是去實現一充分高厚度之閘極絕緣層而帶有充分大的偶 漏電Ά性質能夠利用個方式充分地被加以改 工 (ir "]ί£ / 上 a ./ 疋 τ{( ! ί^>^τ ， 因子 該 用 區 區 你丁 該 5汶 以 特別 電晶體 效應電 第二傳 區域而 質地利 此種方 域，以 個例子 域之間 閘極結 正交次 正交次 小尺寸 實現。 本發 地，對於一 反向器之製 曰曰 體被加以 導型態之場 在該半導體 用正交的方 式 及 一第一 第二截 中，被加以 接合的一共 構之相對部 微影技術閘 微影技術閘 之非常強力 明的進一步 具有次 造，相 形成於 效應電 基材上 式被加 部份截 面被力口 形成在 用的閘 份截面 極結構 極結構 的反向 微影技術間極結構之積 關地，複數個第一傳導 一第一井按入區域’以 加以形成於一第 影技術已圖案化 在該半導體基材 以形成在 晶體被 。該微 以形成 面被加 以形成該第二井 介於該 第一以及 極接觸平台區域 至另一上。該源 外側，以及該汲 内側。利用這個 器結構能夠以最 該第一 才爹入區 該第二 連接次 極接觸 極接觸 方式， 小花> 費 體場效 型態之 及複數 二井摻 遮罩正 上，利 井推入 域。在 井摻入 微影技 只落於 只落於 而 具有 被加 如進一步申請專利範圍所述Page 8 1264071 ^The inscription shows that the gate layer used in the plume semiconductor material and a preferred metal is accustomed to the calcium color; the stranger..f is formed on it. The pole insulating layer is preferably an oxygen ft age, and the oxynitride has a relatively high dielectric number of electrical components. In the example, there is a dielectric material having a high relative permittivity, which may be achieved. A sufficiently high-thickness gate insulating layer with a sufficiently large leakage electric leakage property can be fully modified by a method (ir "] ί£ / a a ./ 疋τ{( ! ί^>^ τ , the factor should be used in the area of the 5th to the special transistor effect electric second transmission area and the quality of the square domain, with an example of the gate junction orthogonal sub-orthogonal sub-small size. Ground, the field of the inductive body of an inverter is guided in a manner orthogonal to the semiconductor and a first and second section, and a co-constructed opposite portion of the lithography technique The shadow technology gate is very powerful and further sub-created The phase formed on the effective electric substrate is added to the cross section by the force port to form the gate structure of the gate structure of the gate structure, and the plurality of first conduction first a well pressed into the region 'to be formed in a lithography technique has been patterned on the semiconductor substrate to form a crystal. The micro to form a face is formed to form the second well between the first and the pole contact platform regions to another The outer side of the source, and the inner side of the crucible. With this device structure, the second connected sub-pole contact pole contact mode can be used in the most first intrusion region, the small flower > the body field effect type and the plurality of two wells Blending the mask directly, the well is pushed into the domain. The technique of incorporating lithography into the well only falls on only the ones that have been added as described in the further patent application.
第9頁 1264071 本發明參考 f;c 材 中 別 的 中 當 S 用 後 以 施 即 影 圖]A 圖案化之 如？皮如以 根據圖 1利用一 ，利用實 的一凹陷 並 矽 可 材 擊 摻入 口 口 C3 早日 曰曰 然是有 〇I基 离隹子轟 之傻 作為微 形成於 例的方 ，具有 是形成 閘極結 如聚矽 以及藉 a / 法 或 由 以及圖1 B顯 遮罩的製造力 要承而同於根 1 A，利用一 種相對應的方 施例的方法， 溝槽隔離（S 且同時複數個 優選地被加以 能去使用替代 等而作為例如 或者是由氣湘 一用於微影閘 閘極絕緣層2 導體基材1的 ，二氧化石夕， 南的相對電容 為了在該微影 S G ，利用貫 者是發化鍺 ；: 利用平當的方 示用 實質 據本 標進 式而 有可 T I 井摻 使用 材料 半導 擴散 極結 而 表面 氧氮 率之 閘極 施例 S i 法而 於圖解說明任一 發明之次微影間 ’ 首先地 1 以製備，在 方法 被加 能去形成一溝槽 歡影技術已 化剖面圖， 極結構： 一半導體基 這例子子 隔难以及特 yV 區 作為 丫列如7 體基 或者 構L 之後 ，在 化物 電介 結構 的方 G e 被加 半導體基材 域在该半導 半導體基材 III- 材 是一固 G之層 被加以 其中的 稱作為 質，以 絕緣層 式，一 )被加 以光學 摻入 態材 —被 形成 例子 高介 熱來 2的 以 微 之 基本 體基材之 1 ，其同時 V半導體， 可以例如利 料。 加以指定此 ，而其被加 中，利用實 電材料7意 加以沉積或 表面形成微 技術閘極層 積在整個面 圖案化。隨Page 9 1264071 The present invention refers to the f;c material in the other, when S is used, it is patterned by the image]A? The skin is used according to Figure 1, using a solid depression and smashing the material to join the inlet C3. The poles such as the polythene and the manufacturing force by the a / method or by the mask of Figure 1 B are the same as the root 1 A, using a corresponding method of the embodiment, trench isolation (S and simultaneous plural Preferably, the relative capacitance of the magnet dioxide substrate 1 for the lithography gate 2, for example, or for the conductor substrate 1 for the lithography gate insulating layer 2 is used, in order to be in the lithography SG. The use of the continuum is a sputum sputum;: the use of the singularity of the singularity of the singularity of the stipulations of the use of the semiconductor wells with the material semi-conductive diffusion pole junction and the surface oxygen and nitrogen rate of the gate example S i method Illustrated in the second lithography of any invention's firstly to prepare, in the method is added to form a grooved photoview technology, the polar structure: a semiconductor base example and the special yV District as a column such as 7 After the base or the structure L, the square G e of the compound dielectric structure is added to the semiconductor substrate region, and the semiconductive semiconductor substrate III is a layer of solid G, which is referred to as an insulating layer. a) being optically doped into the state-formed by the example of a high dielectric constant 2 of the micro-base substrate, while the V-semiconductor, for example, may be advantageous. This is specified, and it is added, using solid material 7 to deposit or surface-forming micro-technical gate layers to be patterned over the entire surface. With
第10頁 1264071 二 晉f丨貢性光1¾忖料之淡用1這獲浔尤學鼠影製造的閑極储 二-或·著是具右一由&等到大的問怪長度關極結構L G s而 二，蚌在類比電路*㈤被加α使吊的' 最後地，一遮覃看Μ 0被加以形成而覆蓋在ί敗影問極 絕绫看2以及徵[間極結構L G之整値面積上1以及一 I 面化被加以進行以為了不f蓋微影閘極結構L G ，結果如 圈1 A所圖解說明之剖面圖被獲得。 由這個傳統層序列之程序，利用複數個標準方法被加 以生欣’在此有可能去貫現該次微影問極結構。Page 10 1264071 Second Jin F丨 tribute light 13⁄4 之 之 淡 淡 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Structure LG s and two, 蚌 in the analog circuit * (five) is added to make the hang 'the last, a concealer Μ 0 is formed and covered in the ί 问 问 问 问 以及 以及 以及 以及 以及 以及 以及 以及 以及 以及 以及The entire area 1 and the I-face are performed so as not to cover the lithography gate structure LG, and as a result, a sectional view as illustrated in the circle 1 A is obtained. By the procedure of this traditional layer sequence, a plurality of standard methods are used to add Shengxin', where it is possible to implement the lithography structure.
根據圖1 B ，在這個例子之中，使用一額外的光學微 影方式，一進一步的光阻遮罩（未被示於圖示中）被加以 形成，並且一特定的部份區域被加以暴露，因一光阻構能 夠被加以剝除至少在一微影技術閘極結構L G以及一因而 為被加以覆蓋的微影技術閘極結構，利用共用蝕刻之方法 而被加以移除。利用相同的方式，該微影技術閘極絕緣層 2同樣地在這個位置被加以移除，結果該開口〇或者是如 在圖1 B所圖示說明之微影技術地被加以.圖案化的負型遮 置被加以獲得。According to FIG. 1B, in this example, an additional optical lithography is used, a further photoresist mask (not shown) is formed, and a specific partial area is exposed. Since a photoresist structure can be stripped at least in a lithography gate structure LG and a lithography gate structure that is thus covered, it is removed by a common etching method. In the same manner, the lithography gate insulating layer 2 is likewise removed at this location, with the result that the opening is either lithographically patterned as illustrated in Figure IB. Patterned Negative masking is obtained.
因此，利用特別簡單的方式，有可能的去製造具有一 士等以及一大閘極長度之閘極結構，並同時利用一種製造 方法製造次微影技術閘極結構。 > 只有該開口〇的區域被加以圖示如下，在其中的例子 ^相對應圖1 B之一微影技術已圖案化_型遮罩Μ ◦放大 |圖根據圖2而被加以圖示說明，並且維持參考符號來標註Therefore, in a particularly simple manner, it is possible to fabricate a gate structure having a length of one gate and a large gate length, and at the same time, to fabricate a gate structure of a sub-lithography technique by a manufacturing method. > Only the area of the opening is illustrated as follows, in which the example ^ corresponds to one of the lithography techniques of Figure 1 B has been patterned _ type mask ◦ ◦ magnified | Figure is illustrated according to Figure 2 And maintain reference symbols to mark
第丨1頁 1264071 元浮以及層7 了這個理田，一重t的描述被加以說明如 試微景:丨技銜已圖案化遮罩可以利用相同方式同樣建構 正$邀罩Μ ϋ — i如圖b ·ρρτ加以圖不說明的。任ιχ (固制子 平· 一正型遮罩或者是一 I型遮罩實質地依據該標单可使 同的加工程序而定°相同的參考符號再次地標註相同的或 者是相對應的元伴，為了這個理由，一詳細的描述再次地 被加以說明如下。Dijon 1 page 1264071 Yuan float and layer 7 This Ritian, a description of a heavy t is explained as a test micro-view: the pattern mask can be constructed in the same way as the same $ Μ ϋ i — i Figure b · ρρτ is not illustrated. Any χ χ (solid 子 · 一 一 或者 或者 或者 或者 或者 固 固 固 固 固 固 固 固 固 固 固 固 固 固 固 固 固 固 固 固 固 固 固 固 固 固 固 固 固 固 固 固 固 固 固 固 固 固 固For this reason, a detailed description is again explained below.
圖4 Α至圖4 D顯示簡化了的剖面圖以及一簡化了的 平面圖，而用來圖解說明在用於場效應電晶體之一次微影 技術閘極結構製造中之實質的方法步驟相同的參考符號標 註元件與在圖1至圖3中之那些相同或者是相對應，並且 一重覆的描述正被加以說明如下。 根據圖4 ，一閘極絕緣層3 (要次微影技術地被加以4 to 4D show a simplified cross-sectional view and a simplified plan view for illustrating the same method steps in the fabrication of a lithography gate structure for a field effect transistor. The symbolizing elements are the same as or corresponding to those in Figs. 1 to 3, and a repeated description is being explained as follows. According to FIG. 4, a gate insulating layer 3 is applied to the lithography technique.
圖案化）結構性地被加以形成在被加以微影技術地圖案化 的負型遮罩Μ〇上，而這包含例如BPSG (硼磷矽氧化 物玻璃）或者是一被加以沉積的氧化物，至少在該半導體 基材1的表面上，即帶有由其參考表面所生相同的厚度。 籍由實施例中的方法，一閘極電介質材料例如石夕的氧化 物，氧氮化物，及/或是一具有高的相對電容率（高Κ材 料）被加以沉積而覆蓋整個在這個例子中之面積°此外一 平當的沉積操作，然而亦有可能地去形成一熱氧化物在該 主導體基材1的開放泣置1該閘極絕緣層3只有在這些位 |置被加以形成。Patterned) is structurally formed on a negative mask that is patterned by lithography, and this includes, for example, BPSG (borophosphonium oxide glass) or an oxide to be deposited, At least on the surface of the semiconductor substrate 1, i.e. with the same thickness produced by its reference surface. By the method of the embodiment, a gate dielectric material such as a cerium oxide, an oxynitride, and/or a high relative permittivity (sorghum material) is deposited to cover the entire sample in this example. The area is also a flat deposition operation, however it is also possible to form a thermal oxide on the main body substrate 1 of the open weep 1 which is only formed at these bits.
第12頁 1264071 冗 種 -i'J匕 -ρτ ,!Γ1> 一雪：' ΐ - ¾t:. _ 4,一 主V.容 ΪΤ一 ： ,rx rr 人一口 金 景 TJ.----^ 丁」1丄 -V Thi 高 是 "L 稱 -.! " *1 '七'可 ."V— 是 φ.'\ c 相 i A.-'J J丄 -ττ ΤΓ 古向 ' i. 右“. 具ir 是ft 韵氧 音二 料% 碎子 K ^. 等 巨 ，.不； 一又 常 王丨 T 良 改 以 加 被 以 是 者 或 同 9:1 4-十 有 帶 ϊ;.ν· 材 種 ， 六此 S電 電漏 制地 控別 的特 少由 減理 r.f 固 —\ /X.. 加這 被T4 以為 是度 即卮丁 意的 ,¾ 質地 t一分 合充 偶有 極具 極 閘 亥 、νθ 在 少 至 成 形 以 加 被 地 性 構 ο結 少 4 減層 以極 加閘 被 一 地， 分後 充之 以 加 並被 。 面 度表 厚體 的導 同半 目 玄 士一口 地在 質有 實只 有層 帶緣 ’絕 是極 即閘 意該 面子 表例 AMV L 白 汰 3 Τ 層為 緣’ 且 絕 一渡 ，濺 法一 方由 勺·vifc.曰 白 芏汗 你， 施中 實子 用例 利個 。這 壁於 側響 之 〇以 Μ加 罩被 遮作 該操 在積 而沉 ’的 成性 形構 以結 法原 積是 沉或 相\ 氣及 學、J 化法 一 D ，L \ly A 法C D法 V積 P沉 .(. 層 法子 積原 沉 一 相， 氣} 理法 物D 是V 者C 或ί 子層化學氣相沉積法（A L C V d法）。 當該閘極層4在圖案化之後只具有一.非常小的寬度或 者是厚度時·金屬性材料，例如氮化组（T a N )，釕 (R u )，氧化釕（：R u〇），顧（P t )等優選地被力口 以使用，而除了高的已#入之據結晶性半導體材料之外， 如該閘極層4 。此種金屬性材料具有一充分地高的電導 ί 丨度，為了這個理由，它使得一場效應電晶體充分驅動，而 i甚至在次微影技術圖案化之後。 ί i 在這個洌子中，該金屬材料利用依據所意欲之工作功Page 12 1264071 Redundant -i'J匕-ρτ ,!Γ1> One snow: ' ΐ - 3⁄4t:. _ 4, one main V. Rong Yiyi: , rx rr One person Jin Jing TJ.---- ^丁"1丄-V Thi高是"L--!! " *1 '七'可."V- is φ.'\ c相 i A.-'JJ丄-ττ ΤΓ 古向' i. Right ". With ir is ft rhythm oxygen tone two material% broken K ^. Other giant, . No; one often Wang Yi T good change to add to the person or the same 9:1 4- ten belt ϊ;.ν· The species, the six S electric power leakage control is particularly limited by the reduction of rf solid-\ /X.. plus this is T4 thought it is the degree of 卮 意, 3⁄4 texture t a The charge has a very extreme sluice, νθ is less than formed to add to the ground structure, and the knot is less than 4, and the layer is added to the ground, and the charge is added to the ground. The same half of the Xuanshi in the quality of the real only the layer of the edge of the 'extremely the gate is the meaning of the face of the table AMV L white 3 Τ layer for the edge' and the first crossing, splashing one by the spoon · vifc. You sweat, you can use it in a practical case. The 响 〇 被 被 Μ 被 被 被 被 被 Μ Μ Μ Μ 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 ' ' ' ' ' ' ' Product P sink. (. Layer method sub-product sinking phase, gas} Method D is V C or ί sub-layer chemical vapor deposition (ALCV d method). When the gate layer 4 is only patterned after patterning A very small width or thickness · metallic materials, such as nitrided group (T a N ), 钌 (R u ), yttrium oxide (: R u 〇), Gu (P t ), etc. are preferably force The mouth is used, except for the high crystalline semiconductor material, such as the gate layer 4. This metallic material has a sufficiently high conductance, for this reason, it makes a The effect transistor is fully driven, and i is even after the sub-lithography technique is patterned. ί i In this dice, the metal material utilizes the work according to the intended work.
第13頁 1264071Page 13 1264071
X bJE 以 數 Γ:~7 敢 該 被 利 地 成 目 上 的 電 數 同 m /—·! 層 A 極 <士 發明說明：9: 而定或者是浓據各半導體材料之#入而定的方弍而被加 選擇：該金屬性閑極f的厚度更退一步地依據複數個參 而定，該等參數洌如一所意欲的闊極長度，一所意欲的 終厚度，以及同時依據該金屬沉積操ί乍的接構性而定： 次微影技術閘極結構的一閘極長度實質地利用其厚度而 加以定義。 利用相同的方式，複數個序列同時可以在該閘極層4 用不同的沉積方法而被加以形成。在這個例子中，特別 ，一合適的閘極層（未加以圖示說明）直接地被加以形 在該閘極絕緣層3的表面上，而為了調整一工作功能的 的，並且一具有最低可能阻抗之閘極層被加以沉積於其 原則上，它必 材料被加以使用 晶體之各個鞘電 個結構，以及用 時而可想而知。 根據圖4 Α ^ 度之氧氮化物層 3而覆蓋在該半 體1的表面以及 層4例如可以利 1其具有大約1 一工作功能到該 須在這個例子中被加以點出的是相對應 於調整該工作功能或者是用於定義各個 壓，帶有複數層而用於調整工作功能複 於實現加以要求之高電導度之進一步層 具有大約一奈米 利用實施例的方式 (S 1〇N )被加以形成如該閘極絕緣 導體晶圓上或者是在該遮罩Μ〇，該半 在其中垂直的側壁上之整個面積。該閘 用一 T a Ν調節閘極層的形式被加以沉 〇奈米至5 0奈米的厚度，並且提供調 半導體材料上，而這隨著有一具有5〇X bJE is a number of Γ:~7 Dare to be the same as the electricity number of the m / -·! Layer A pole <Shi invention description: 9: depending on the thickness of each semiconductor material The thickness of the metallic idler f is further determined by a plurality of parameters, such as an intended width of the width of the pole, an intended final thickness, and at the same time Depending on the connectivity of the metal deposition process: the gate length of the sub-lithography gate structure is essentially defined by its thickness. In the same manner, a plurality of sequences can be simultaneously formed in the gate layer 4 by different deposition methods. In this example, in particular, a suitable gate layer (not shown) is directly formed on the surface of the gate insulating layer 3, and in order to adjust a working function, and one has the lowest possible The gate layer of the impedance is deposited in principle, and it must be materialized using the various sheath structures of the crystal, as well as imaginable from time to time. Covering the surface of the half body 1 according to the oxynitride layer 3 of FIG. 4 and the layer 4 can, for example, have a function of about 1 to the point that the whisker is to be pointed out in this example. Further layers for adjusting the working function or for defining individual pressures, with multiple layers for adjusting the operational function to achieve the required high electrical conductivity, have approximately one nanometer using the embodiment (S 1〇N ) is formed on the gate insulating conductor wafer or on the mask Μ〇, the entire area of the half on the vertical sidewalls. The gate is immersed in a T a Ν regulated gate layer in the form of a thickness of 50 nm and is provided on a semiconductor material, and this has a 5 〇
第14頁 1264071 _、货明說明（10,， 到1 0 0奈米厚度之鎢（W )或者是矽化鎢（W S i )層 而作為低電容率閘極層。 根據圖4： B ，在一附隨發生的方法步驟之中，一非等 方向性蝕刻方法被加以實行為了去形成該次微影閘極結構 S G至少沿著該遮星Μ ◦的惻壁：該非等方向性蝕刻方法 優選地利用反應性離子蝕刻（R I Ε反應性離子蝕刻法） 的方式在該金屬閘極層4而被加以進行，結果所意欲次微 影間隙物或者是閘極結構S G被加以獲得而帶有臨界尺寸 之最小功能。Page 14 1640071 _, the description of the goods (10,, to the thickness of 1000 nm tungsten (W) or tungsten telluride (WS i) layer as a low-capacitance gate layer. According to Figure 4: B, in In an accompanying method step, an unequal etch method is performed in order to form the lithography gate structure SG at least along the sidewall of the occultation: the omnidirectional etching method preferably The method is carried out by means of reactive ion etching (RI Ε reactive ion etching) on the metal gate layer 4, and as a result, the sub-micro-gap spacer or the gate structure SG is obtained with a critical value. The smallest function of size.
之後，該閘極絕緣層3同時可以在未被次微影閘極結 構S G覆蓋的區域而被加以移除。一濕式化學移除正被加 以進行而其例如是利用兩步驟法。利用相同的方式，該閘 極層4以及該絕緣層3同時可以利用一單一方法之步驟或 者是利用複數方法之步驟如圖4 Β所圖示說明地被加以圖 案化。該閘極絕緣層3可選擇地同時可以維持如遮蔽層而 用於一離子植入，而隨及第被加以進行。Thereafter, the gate insulating layer 3 can be removed at the same time in an area not covered by the sub-lithographic gate structure S G . A wet chemical removal is being carried out which is for example a two step process. In the same manner, the gate layer 4 and the insulating layer 3 can be simultaneously patterned by a single method or by the steps of the complex method as illustrated in Fig. 4 . The gate insulating layer 3 can optionally be maintained at the same time as an obscuring layer for an ion implantation, and is subsequently carried out.
最後地，根據圖4 C ，該硬遮罩Μ〇同時以及構成基 底的微影技術問極絕緣層2在該開口〇的區域中被加以移 除，結果該次微影閘極結構S G不被加以覆蓋。在這個例 子中，為了進一步的加工程序，可能存在知一閘極絕緣層 3可以保持在該次微影技術閘極結構S G的側壁。 ’ 圖4 D顯示一進一步次微影技術閘極結構S G之微影 技術圖案化步驟的簡化平面圖，其係利用一用於分割機體 此微影技術閘極結構S G成複數個次微影技術閘極結構的Finally, according to FIG. 4 C , the hard mask Μ〇 and the lithography technology constituting the substrate are removed in the region of the opening ,, and as a result, the MEMS gate structure SG is not Cover it up. In this example, for further processing, there may be a known gate insulating layer 3 that can remain on the sidewall of the lithography gate structure S G . Figure 4D shows a simplified plan view of the lithography technique patterning step of a further lithography gate structure SG, which utilizes a lithography structure SG for dividing the body into a plurality of lithography gates. Pole structure
第15頁 1264071 極 由 蓋 或 獲 結 圖 者 如 絕 形 後 隨 材 中r明.¾:- 刻遮 7TT 於這 填充 根 絕緣 5玄切 白勺區 者是 得。 例 構S 4 G 是曾 相 藉由 緣層Λ ， ."人 側被 絕緣 即地 之 1的 倒壁 罩C Μ來進行。這個 方法步骤之後被加以 個步驟而藉由次微影 以及平面化而被加以 據圖4 D ，利用實施 層 之正交 微 影技 刻遮罩C Μ而被加以 域能夠利用平常蝕刻 平行次微影技術閘極 步驟可以倒如在根據如圖4 Β 影響·同時也可能可選擇性地 閘極結構S G之間為覆蓋區域 實行，而其用於保護的目的3 例的方法，只有在帶有保持閘 術閘極結構S G的中心區域籍 覆蓋。為了這個理由，未被覆 方法而被加以移除。兩個相反 結構部份利用這個方式被加以 如為了 G之場 方法之 ，為了 關地， 一濕式 5可以 並且， 加以形 層在次 非等方 後，所 表面1'吏 絕緣層 利用這 效應電 步驟， 這個理 根據圖 触刻方 在該次 I itb — 成。在 地被加 向性被 稱作連 用次微 5同時 個方式完成形成 晶體， 相同參 進一步可 由，一 4 E ^ 法或者 微影技 例子之 這個例 以結構 力口以！虫 接摻入 影技術 考符號再 重覆的描 在該硬遮 是一氧化 術閘極結 中，同時 子之中， 性地沉積 刻回來。 區域6 ( 閘極結構 極絕绫體 具有次 能進行 次標註 述被加 罩Μ〇 物I虫刻 構S G 在該閘 利用實 而覆蓋 微影技 有關圖 相同的 以說明 移除之 方法， 的側壁 極絕緣 方包例白勺 整個面 術閘極 4 Ε至 元件或 如下。 後，例 一側壁 被加以 層3的 方式， 積以及 延伸）在該半導體基 S G而被加以形成， 3可能地垂直地存在Page 15 1264071 The pole is covered or the figure is obtained. If it is absolutely shaped, it will be covered with the material. 3⁄4:- Cover 7TT is used to fill the root insulation. The conventional structure S 4 G is performed by the edge layer C, and the human side is insulated by the inverted wall cover C Μ. This method step is followed by a step by sub- lithography and planarization. According to Figure 4 D, the orthogonal lithography technique of the implementation layer is used to mask the C Μ and the domain can be used to etch the parallel sub-micro The shadow technology gate step can be implemented as a coverage area between the gate structure SG and the gate structure SG according to the influence of FIG. 4, and the method for protecting the 3 cases is only Keep the center area of the gate gate structure SG covered. For this reason, it was removed without the method. The two opposite structural parts are applied in this way as in the case of the G field method. For the grounding, a wet type 5 can be and after the layer is sub-equal, the surface 1'吏 insulating layer utilizes this effect. The electric step, which is based on the graph, is in the Iitb. The addition of the ground is called the simultaneous use of the sub-micro 5 to complete the formation of the crystal, and the same reference can be made by the example of the 4 E ^ method or the lithography example. Insects are incorporated into the shadow technique. The symbol is repeated. The hard mask is in the gate of the oxidized gate, and is deposited in the same manner. Zone 6 (the gate structure is extremely 绫 具有 具有 具有 具有 被 被 被 被 被 被 被 被 被 被 被 被 被 被 被 被 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在The sidewall is insulated, for example, the entire surface of the gate is 4 Ε to the component or as follows. Thereafter, the sidewall is formed by layer 3, and the extension is formed in the semiconductor SG, 3 may be vertical Presence
第16頁 1264071 而作為一遮罩’一連接的渣入I A優選地正被加以進行： 々如——一氣i匕物被加以使用而作為用於該第一 ί_璧絕緣層 5之材料。 根據圖4 F ^ —第二ί則壁絕緣層了隨即地利用與該第 一側壁絕緣層b之相同的方式而被加以形成在該第一惻壁 絕緣層5的惻壁，例如氮化矽（S i 3 Μ 4 )正被加以使用 而作為絕緣體材料。使用這個第二間隙物或者是側壁絕緣 層7同時與帶有間極絕緣層3該第一側壁絕緣層b以及該 次微影技術閘極結構S G，源極/沒極摻入區域8隨即被 加以形成在該半導體基材1之中，一源極/汲極離子植入 I s , / D優選地被加以進行。 最後地，根據圖4 G，一純化層9 ，利用一平面化步 驟以及次微影閘極結構S G最後為了形成所要求的源極、 汲極以及閘極接觸而被加以形成在整個區域，並且被加以 拉回，而其用於連接該源極/汲極摻入區域8同時與該次 微影技術閘極結構S G。利用實施例的方式，B P S G (硼磷矽氧化物玻璃）或者是一氧化物可以被加以使用而 作為該純化層9 。 利用這個方式，帶有次微影閘極結構結構之該所意欲 的場效應電晶體在該圖1 B之區域〇中被加以獲得。 這個新穎的製造方法的優點，特別地，事實上，在利' 用微影技術所形成於一硬遮罩側壁上之一間隙物，不作為 闬於隨即蝕刻步驟之一進一步硬遮罩·而該步驟用於製造 一次微影閘極結構但相當於已經建構最終次微影閘極結Page 16 1264071 As a mask, a connected slag I A is preferably being carried out: for example, a gas is used as the material for the first insulating layer 5. According to FIG. 4 F ^ - the second λ wall insulating layer is then formed in the same manner as the first sidewall insulating layer b in the sidewall of the first sidewall insulating layer 5, such as tantalum nitride (S i 3 Μ 4 ) is being used as an insulator material. Using the second spacer or the sidewall insulating layer 7 simultaneously with the first sidewall insulating layer b with the interpole insulating layer 3 and the sub-lithographic gate structure SG, the source/depolarization doping region 8 is then Formed in the semiconductor substrate 1, a source/drain ion implant I s , / D is preferably carried out. Finally, according to FIG. 4G, a purification layer 9 is formed over the entire region by using a planarization step and a sub-lithographic gate structure SG to form the desired source, drain and gate contacts. It is pulled back and it is used to connect the source/drain doping region 8 to the lithography gate structure SG. By way of the embodiment, B P S G (boron phosphide oxide glass) or a monooxide may be used as the purification layer 9 . In this manner, the desired field effect transistor with a sub-lithographic gate structure is obtained in the region 该 of Fig. 1B. The advantages of this novel manufacturing method, in particular, the fact that one of the spacers formed on the sidewall of a hard mask by lithography is not used as a hard mask for one of the random etching steps. The step is used to fabricate a lithography gate structure but is equivalent to having constructed the final lithography gate junction
1264071 flfr 第 .¾池於 方法是重 所稱 個例子中 影閘/極長 被加以排 對於所有 性。相關 構，而其 度。 當在 影閘極結 (平台堅 圖5 交次微影 第一實驗 步驟，相 及 重覆 根據 S G的切 可能的去 1 ϋ录 白勺3 作”閘 ，同時 度之平 列的結 點範圍 地 7 — 同時具 利用一 構出現 )的方 Α以及 結構S 洌之此 同的參 ]的描 圖5 A 割之前 形成一 米之 〜Γ、 太t、 、 短 工程艮不被加以要4 及精卻|丨、生充汐κ % ♦ η 太土 5 a η 太土 ^ (山L 旦' I- '3 H 丄 二士 π人 iX 1'1LJ ;^j fei tr I岛了這 丄乂 ^ 善 ' L間以及特 勺此種製造 極修整”的加工程序不再被加以要求在這 原則上有可能地去製造具有不同量的次微 面電晶體。再者，特別地，對於以4 5度 構線，例如，以這個方法，使得能夠實現 帶有一最小的間隔以及最高的可能精確 製造方法能夠被加以使用而形成閘極結 有非常大以及中等以及次微影超短閘極長 閘極接觸製造接觸時如前面所描述的次微 問題·用來;製造所稱作閘極接觸平台區域 法被加以描述如下。 圖5 B顯示一帶有調節閘極絕緣層3之正 G的簡化平面圖，而用於圖示說明有關一 種閘極接觸平台區域製造之中實質的方法 考符號標註相同的或者是相對應的元件以 述被加以說明如下。 ，仍在揋據圖4 D之次微影技術閘極結構 ，以及特別地同時在該遮罩Μ 0之前，有 問極接觸平台區域，而用於在該正交次微1264071 flfr No. 3⁄4 pool in the method is called the example of the shadow gate / very long is placed for all sex. Relevant structure, and its degree. When in the shadow gate pole (the first experimental step of the lithography of the platform, the phase and the repetition are based on the SG's possible to go to 1 ϋ 白 白 作 ” , , , , , , , , , , , , , The ground 7 - at the same time using a frame appears) and the structure S 洌 the same parameter of the drawing 5 A before the cut formed a meter ~ Γ, too t,, short engineering 艮 not to be required 4 and fine丨 丨 生 生 生 生 生 生 生 生 生 5 5 5 5 5 5 5 ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ I I I I I I I I I I I I I I I I I I I I I I I I I I I I The processing procedure of good 'L and special spoons is no longer required. In principle, it is possible to manufacture sub-micro-surface transistors with different amounts. Furthermore, especially for 4 5 The structuring line, for example, in this way, enables a very precise and precise manufacturing method with a minimum spacing and the highest possible manufacturing method to form a gate junction with very large and medium and sub-micro-image ultra-short gate long gates Sub-micro problems when used in contact with manufacturing contacts, as described above; The touch-panel area method is described below. Figure 5B shows a simplified plan view of a positive G with a regulated gate insulating layer 3, and is used to illustrate the methodological labeling of the substance in the fabrication of a gate contact landing area. The same or corresponding elements are described below as follows. Still in the lithography gate structure of Figure 4D, and particularly before the mask Μ 0, there is a pole contact platform area. And used in the orthogonal sub-micro
第18頁 1264071 影技術閘極結構S G之一個別的長邊。Page 18 1264071 Shadow technology gate structure S G one of the individual long sides.
相關地，籍由利闬一光學遮遮罩P Μ — A ·實質地正 方開口〇A在每個例子中都被加以形成於該次微影結構閘 極結構S G的一區域之中°該微影技術被加以圖案化之遮 遮罩Μ〇同時與該填充層使用所述的遮罩P Μ — A而被加 以移除，其中該填充層可選擇性地被加以填充在該次微影 劑設閘極結構SG之間，因而，在所述開口〇A中區域之 次微影技術閘極結構完全地不被加以覆蓋。之後，該開口 〇A藉由利用一電性傳導材料而被加以填充，金屬材料優 選地被加以沉積並且隨即地被加以平面化而與該遮罩Μ〇 一樣遠。在這個優選地C Μ Ρ (化學機械研磨）方法之 後，如圖5所加以圖解說明之次微影閘極結構S G之平面 圖被加以獲得，所被稱作為閘極接觸平台區域1 0 Α在此 正被加以形成於早先開口〇A的區域之中，而這使得接觸 利用一簡單的方式以該次微影技術閘極結構S G而被加以 製作。 然而，有關於此種方法之缺點特別地為用·於光學遮罩 Ρ Μ — A對準的精準性所相關的高度要求。Relatedly, the illuminating mask PA is substantially formed in each region of the lithography structure gate structure SG. The mask that is patterned by the technique is simultaneously removed from the fill layer using the mask P Μ - A, wherein the fill layer is selectively filled in the lithographic agent Between the gate structures SG, the sub-lithographic gate structure of the region in the opening 〇A is thus completely uncovered. Thereafter, the opening 〇A is filled by using an electrically conductive material, which is preferably deposited and then planarized as far as the mask Μ〇. After this preferred C Μ (Chemical Mechanical Polishing) method, a plan view of the sub-lithographic gate structure SG as illustrated in Figure 5 is obtained, referred to as the gate contact plateau region 1 0 Α It is being formed in the region of the previous opening 〇A, and this allows the contact to be made in a simple manner with the lithography gate structure SG. However, the disadvantages associated with this method are in particular the height requirements associated with the accuracy of the optical masking A-A alignment.
圖6 A以及圖6 B因此表示一剖面圖以及一已被加以 簡化的平面圖，而這用來圖解說明製造根據一被加以簡化 的第二實驗例中閘極接觸平台區域，相同的參考符號再次 標註相同的元素或者是層，為了這個理由，一重覆了的描 述被加以說明如下。 裉據圖6 A ，根據該第二實驗洌該光學微影遮罩Ρ Μ6A and FIG. 6B thus show a cross-sectional view and a plan view which has been simplified, and this is used to illustrate the manufacturing of the gate contact platform region according to a simplified second experimental example, the same reference symbol again. Labeling the same elements or layers, for this reason, a repeated description is described below. According to FIG. 6A, according to the second experiment, the optical lithography mask Ρ Μ
第19頁 1264071 一 iB在此不異有細別的開口 0 A ， 但是相當具有一果一 士：長聞α ’‘其運到超過該次散影技術閑極結搆S G兩個長 i則雙、這個開口 Ο Β優選地具有一與該次微影闊極結構S G對面長ί則壁之間的距離充分地較大長度、因此充分地減 >:、由光學ί啟影技術遮I Ρ Μ — Β設置精確性的要求。 為了能避免在該閘極接觸平台區域1 0Β之間的一短 電路·而在該次微影閘極結構S G側壁，然而一替代性的 填充方法在此被加以進行。Page 19 1644071 An iB here has a different opening 0 A, but it has quite a fruit: a long smell α '' it is transported beyond the astigmatism structure SG two long i is double, The opening Ο Β preferably has a length that is opposite to the lithographic wide-pole structure SG, and the distance between the walls is sufficiently large, and thus is sufficiently reduced: by the optical illuminating technique I Ρ Μ — Β Set the accuracy requirements. In order to avoid a short circuit between the gate contacting the land area 10 Β and at the side of the lithography gate structure S G , an alternative filling method is hereby carried out.
根據圖6 Β ，利用實施例的方式，有可能去進行一化 學氧化或者是一選擇性的氧化物沉積於一閘極接觸絕緣層 2 Α之中，該絕緣層帶有1 〇奈米的厚度，例如，在該半 導體基材1上。為了這個例子，其中該閘極接觸平台區域 1 0 B被加以形成於一半導體區域之中，而其已經具有溝 隔離體（例如，S T I ，淺溝隔離體），此種閘極接觸絕 琢層2 A能夠被加以獲得。According to Fig. 6 Β, by way of example, it is possible to perform a chemical oxidation or a selective oxide deposition in a gate contact insulating layer 2, the insulating layer having a thickness of 1 〇 nanometer. For example, on the semiconductor substrate 1. For this example, the gate contact pad region 10B is formed in a semiconductor region that already has a trench isolation (eg, STI, shallow trench isolation) that is in contact with the gate layer 2 A can be obtained.
之後，一電性傳導層再次地被加以形成，並且優選地 選擇性地被加以沉積在該次微影閘極結構S G之閘極層， 一金屬層或者是一高度地被加以換入的聚隙層再次地正被 加以沉積覆蓋在整個面積。最後地，一種非等方向性敍刻 方法被加以進行為了形成該間隙物。為了形成間隙物結構 如圖6 B所加以圖解說明，因而防止介於該個別的閘極接 觸半台區域1 0 B以及增加一充分大的平台墊。 因當這個加工程序自行對齊，對齊精確度所生之要求 在這第二實驗例之刿子中被充分地加以減小。Thereafter, an electrically conductive layer is again formed and preferably selectively deposited on the gate layer of the sub-lithographic gate structure SG, a metal layer or a highly exchanged poly The gap layer is again being deposited to cover the entire area. Finally, a non-isotropic characterization method is performed in order to form the spacer. To form the spacer structure as illustrated in Figure 6B, it is thereby prevented that the individual gate contacts the half region 10B and adds a sufficiently large platform pad. Since the alignment procedure is self-aligned, the requirements for alignment accuracy are sufficiently reduced in the dice of this second experimental example.
第20頁 1264071 圖ί A到圖V C顯示一些簡化平面圖而用來解釋說明 王製邊積體場一效應電晶體反向器結構之實質的方法步 雜·如雨IB7所描述之該足敵景；技術間極結構被加以使用5 這裡所被加以描述的方法是特別地適合S〇I (矽在絕緣 體上；晶圓，因而相同閘極材料且特別的是相同金屬能夠 *這個例子中對各種不同F E T s而被加以使用。 在根據圖7A ，首先地，該第一傳導型態η之一第一 丼摻八區域1 1 ，以及在後面一第二晶摻入區域1 2於該 第二傳導型態ρ ，相對該第一傳導型態而而被加以形成於 該半導體積材1之中。如前所加以描速之微影技術地已被 加以刻化圖案的正型遮罩Μ〇一 I在這個例子中利用正交 的方式被加以形成在該半導體積材1上，利用此種方式， 一第一部份截面被加以形成在該第一井摻入區域1 1上， 並且該第二部份截面被加以形成在該第二井摻入區域 1 2 。根據圖1 A，由一正行遮罩Μ〇一 I製造之使用， 在其中，實質地一半落於該井摻入區域1 1中以及其另外 一半落於該第二井摻入區域12中。 - 根據圖7 Β ，之後，根據如前面所描述的方法步驟， 一正交的次微影閘極結構S G帶有其閘極絕緣層3 ，在該 正型遮罩Μ〇一 I的側壁被加以形成，並且該遮罩隨及第 被加以移除。然而，該次微影閘極結構S G的分割不被加 以進行。 之後，如前面所加以描述的，汲極摻入區域實質地被 如以形成在該正交閘極結構S G之中，以及源極推入區域Page 20 1264071 Fig. A to Fig. VC shows some simplified plan views to explain the essence of the structure of the king-edge integrated field-effect transistor invertor. The inter-technical pole structure is used. 5 The method described here is particularly suitable for S〇I (矽 on the insulator; the wafer, thus the same gate material and especially the same metal can* Different FETs are used. In accordance with FIG. 7A, first, one of the first conductivity types η is first doped with an octagonal region 1 1 , and at a later second second fused region 12 is at the second A conduction pattern ρ is formed in the semiconductor material 1 relative to the first conductivity type. A positive mask that has been patterned by lithography as described above. An I is formed on the semiconductor material 1 in an orthogonal manner in this example, in such a manner that a first partial cross section is formed on the first well doping region 1 1 and a second partial section is formed in the second The well is incorporated into the region 1 2 . According to Figure 1 A, the use of a positive row mask is used, wherein substantially half of the well is in the well-incorporated region 1 1 and the other half is in the second The well is doped into the region 12. - According to Fig. 7 Β, then, according to the method steps as described above, an orthogonal sub-lithographic gate structure SG has its gate insulating layer 3 in which the positive mask The sidewall of the first I is formed, and the mask is removed as follows. However, the division of the lithography gate structure SG is not performed. Thereafter, as described above, the bungee The doping region is substantially formed in the orthogonal gate structure SG, and the source push-in region
第21頁 1264071 f質地死π以哥：攻么該正交閑極結構S G之外'側而在Η 第一以及第二景# ..>、區域2 2以1 1 2之中 ' 當然地——原 怪以及汲極#入區域對於個別丼彳參入區域具有相對應相對 # ·〜.:ι 一共用的閘極接觸I台區域1 〇 C在此被加以形成在 介於該第一以及第該第二井摻入區域1 1以及1 2之間一Page 21 1644071 f texture dead π 哥哥: attack what is the orthogonal idle structure SG outside the side and in the first and second scenes #..>, area 2 2 to 1 1 2 'of course The ground - the original blame and the bungee # into the area has a corresponding relative to the individual 丼彳 入 # · · · · 共用 共用 共用 共用 共用 共用 共用 共用 共用 共用 共用 共用 共用 共用 共用 共用 共用 共用 共用 共用 共用 共用 共用 共用 共用 共用 共用 共用 共用 共用And a second second incorporation region 1 1 and 1 2
接合處的區域之中，在一糾子中，然而，次微影值閘極結 構S G之長惻之相對的部份，在此被加以允許而電性地連 接到另一。最後地，為了與該源極摻入區域接觸，源極S 只在該垂直的次微影閘極結構S G外側被加以形成，以及 用於與汲極摻入區域相接觸之汲極接觸D ，只有在該垂直 的次微影問極結構S G之中被加以形成，一閘極接觸G正 在該共用的閘極接觸平台區域1 0 C被加以形成。 這得到該場效應電晶體反向器，而其被加以圖示解說 如在圖8之中利用簡化形式之等電流圖，以及具有一特別 地簡單以及省空間的構造。 本發明基於一垂直的次微影閘極結構已經被加以描述 於上。然而，它並不被加以設限於此，並且同時包含替代 的形式，或者是利用這個方式的結構。Among the regions of the joint, in an entanglement, however, the opposite portion of the long 恻 of the sub-lithographic value gate structure S G is allowed to be electrically connected to the other. Finally, in order to be in contact with the source doping region, the source S is formed only outside the vertical sub-lithographic gate structure SG, and the drain contact D for contact with the drain doping region, Only in the vertical sub-lithographic interrogation structure SG is formed, a gate contact G is formed in the common gate contact land region 10C. This results in the field effect transistor inverter, which is illustrated as a current diagram in a simplified form as in Fig. 8, and with a particularly simple and space saving configuration. The present invention has been described above based on a vertical sub-lithographic gate structure. However, it is not limited to this, and it contains either an alternative form or a structure that utilizes this method.
再者，一反向器結構已經被加以描述有汲極摻入區 域1以及^所相關聯的汲極接觸，其落於該垂直的閘極結構 之中。然而，利用這個方式這些同時可以落於該垂直閘極 結構外惻，因此該源極摻入區域以及所相關聯的源極接觸 向内移動。Furthermore, an inverter structure has been described with a drain contact region 1 and associated drain contacts that fall within the vertical gate structure. However, in this manner these can simultaneously fall outside the vertical gate structure, so that the source doping region and the associated source contact move inward.
第22頁 1264071 S 1 Λ以及園1 B顯示用於圖解說明在一微影技術已被園 云。c之遮置的製造中實質的方法布戰的簡化吾丨面圖。 3 2顯示微影技術已圖案化之_型遮罩的放大頗面圖。 1 3顯示微影技術已圖案化之正型遮置的放大頗面圖。 圈4 A到圖4 C顯示用於圖解說明在一次微影閘極結構之 的製造♦實質的方法步驟的簡化剖面圖。 圖4 D顯示用於圖解說明在一次微影閘極結構之裁切的製 造中貫質的方法步驟的簡化剖面圖。Page 22 1264071 S 1 Λ 园 1 B display is used to illustrate the fact that a lithography technique has been used. The simplification of the actual method of manufacturing in the manufacture of c-shielding. 3 2 shows the magnified face of the patterned _ type mask. 1 3 shows an enlarged face view of the positive-type mask that has been patterned by lithography. Circles 4A through 4C show simplified cross-sectional views for illustrating the fabrication of a lithographic gate structure. Figure 4D shows a simplified cross-sectional view of the method steps for illustrating the mechanization in the fabrication of a lithographic gate structure.
圖4 E到圖4 G顯示用於圖解說明在一具有次微影閘極結 構之場效應電晶體的製造中實質的方法步驟的簡化剖面 圖3 圖5A以及圖5 B顯示用於圖解說明在一關於第一實施例 之閘極接觸平台區域的製造中實質的方法步驟的簡化剖面 圖° ，6 A以及圖6 B顯示用於圖解說明在一關於第二實施洌 之閘極接觸平台區域的製造中實質的方法步驟的簡化剖面 圖。 -Figure 4E to Figure 4G show a simplified cross-sectional view for illustrating substantial method steps in the fabrication of a field effect transistor having a sub-lithographic gate structure. Figure 5A and Figure 5B are shown for A simplified cross-sectional view of a substantial method step in the fabrication of the gate contact land region of the first embodiment, 6A and 6B, is shown for illustrating a gate contact platform region in relation to the second embodiment A simplified cross-sectional view of the method steps in the manufacture. -
圖7A到圖7 C顯示用於圖解說明在一場效應反向器的製 遣*實質的方法步驟的簡化平面圖。 圖8顯示如圖7圖解說明之場效應反向器的簡等電路圖。 元ί牛符號說明： 丄 丰導體基材 2 微影技銜閘極絕緣層 '6 閘極絕緣層 4 閘極層Figures 7A through 7C show simplified plan views illustrating the method steps for the fielding of a field effect inverter. Figure 8 shows a simplified circuit diagram of the field effect inverter as illustrated in Figure 7. Yuanί牛 symbol description: 丄 Feng conductor substrate 2 lithography technology gate insulation layer '6 gate insulation layer 4 gate layer
第23頁 1264071 丨 u iPage 23 1264071 丨 u i
5 第一惻壁絕緣層 6 連接摻入區域 — 第二側壁絕緣譽 8 焉極/ :¾ _ # Λ、區Η 9 鈍化層 -! 〇 A 1 [ 0 Β Λ 1 0 C 閘 極接 觸點 平台區j 1 1 Λ 1 2 第 一 第 •-- 丼 摻入 區域 S 次 微 影 技 術 閘 極 仕 、々:〇 構 L G 微 影 技 術 閘 極 結 構 〇 0 A 、 〇 Β 遮 罩 開 π Μ 〇 Λ Μ 〇 — I 微 影 技 術 已 圖案 化遮 罩 Ρ Μ — A Λ Ρ Μ — Β 光 學 微 影技 術遮 罩 C Μ 裁 切 遮 罩 S 源極接觸點 D 汲 極 接 觸 點 G 閘極接觸點 第24頁5 The first wall insulation layer 6 is connected to the doping area - the second side wall insulation is 8 bungee / :3⁄4 _ # Λ, zone Η 9 passivation layer -! 〇A 1 [ 0 Β Λ 1 0 C gate contact platform Zone j 1 1 Λ 1 2 First - - 丼 S S S S S 微 微 LG LG LG LG LG LG LG LG LG LG LG LG LG LG LG LG A A A A A A 遮 遮 遮 遮 遮Μ 〇 — I lithography technology patterned mask Ρ Μ — A Λ Ρ Μ — 光学 Optical lithography mask C 裁 Cutting mask S Source contact point D Contact point G Gate contact point 24 page
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| DE2002160234 DE10260234A1 (en) | 2002-12-20 | 2002-12-20 | Method for producing a sublithographic gate structure for field effect transistors, an associated field effect transistor, an associated inverter and an associated inverter structure |
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| US4358340A (en) * | 1980-07-14 | 1982-11-09 | Texas Instruments Incorporated | Submicron patterning without using submicron lithographic technique |
| US4419809A (en) * | 1981-12-30 | 1983-12-13 | International Business Machines Corporation | Fabrication process of sub-micrometer channel length MOSFETs |
| JPS6066861A (en) * | 1983-09-22 | 1985-04-17 | Toshiba Corp | Manufacture of semiconductor device |
| JPS60182171A (en) * | 1984-02-29 | 1985-09-17 | Oki Electric Ind Co Ltd | Manufacture of semiconductor device |
| FR2718287B1 (en) * | 1994-03-31 | 1996-08-02 | Alain Straboni | Method for manufacturing an insulated gate field effect transistor, in particular of reduced channel length, and corresponding transistor. |
| DE19536523A1 (en) * | 1995-09-29 | 1997-04-03 | Siemens Ag | Method of manufacturing a gate electrode |
| US5817561A (en) * | 1996-09-30 | 1998-10-06 | Motorola, Inc. | Insulated gate semiconductor device and method of manufacture |
| US5950091A (en) * | 1996-12-06 | 1999-09-07 | Advanced Micro Devices, Inc. | Method of making a polysilicon gate conductor of an integrated circuit formed as a sidewall spacer on a sacrificial material |
| US6124174A (en) * | 1997-05-16 | 2000-09-26 | Advanced Micro Devices, Inc. | Spacer structure as transistor gate |
| JP4527814B2 (en) * | 1997-06-11 | 2010-08-18 | 富士通セミコンダクター株式会社 | Manufacturing method of semiconductor device |
| US6008087A (en) * | 1998-01-05 | 1999-12-28 | Texas Instruments - Acer Incorporated | Method to form high density NAND structure nonvolatile memories |
| US6225201B1 (en) * | 1998-03-09 | 2001-05-01 | Advanced Micro Devices, Inc. | Ultra short transistor channel length dictated by the width of a sidewall spacer |
| TW561530B (en) * | 2001-01-03 | 2003-11-11 | Macronix Int Co Ltd | Process for fabricating CMOS transistor of IC devices employing double spacers for preventing short-channel effect |
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| WO2004057660A3 (en) | 2005-03-31 |
| DE10260234A1 (en) | 2004-07-15 |
| TW200416900A (en) | 2004-09-01 |
| AU2003289828A1 (en) | 2004-07-14 |
| AU2003289828A8 (en) | 2004-07-14 |
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