TW200416900A - Method for fabricating a sublithographic gate structure for field-effect transistors, an associated field-effect transistor and an associated inverter, and associated inverter structure - Google Patents

Abstract

The invention relates to a method for fabricating a sublithographic gate structure, an associated field-effect transistor and an associated inverter and an associated inverter structure, in which case a sublithographic gate structure (SG) with small fluctuations of the critical dimensions can be fabricated directly at the sidewalls of a lithographically patterned mask (M0,2) by contormally forming a gate insulation layer (3) and a gate layer with anisotropic etching carried out afterward.

Description

200416900 V. Description of the invention π) The present invention relates to the scope of shadow metal. The combination of 1 0 0 is used in the near-meter range of the resistance material, which meets the technical requirements. Because of a manufacturing method, it is used to manufacture a field effect transistor associated with a lithographic gate junction and an associated inverter, in an inverter structure, and in particular, it relates to a method for manufacturing a sub-micro leisure pole. The method, which has a nano-nanofan chemical resistance with a gate length of less than 1,000 nanometers, is called a one-step hair. In this case, the operation is not limited to the cost of the mask. Therefore, this method replaces this method, such as the auxiliary layer mask is transferred by using a method of engraving I, as described in the removal method. This method of shadowing envelops, produces, and covers 15 7 exhibitions, and most of the example theory seeks to make it and is known as the most convenient and convenient auxiliary layer, and has obtained the development of the subpolar layer. Manufactured with nano-lithography used to make non-Chinese materials, these micro-components do their best to this small structure. At the same time, it is also difficult to manage photoresist for microlithography, which is suitable for photolithography. The non-isotropic direction reduces the shadow mask mask knots for forming manufacturing problems, and complex technology is often good. There are no obstacles, and the shadow system method has been used. A kind of ground is added, and its structure is very good. The method of lithography is very good. Especially the resistance to the structure has been removed. Therefore, they have been added to these structures. I used the worm to make use of it. The structure of the shadow gate is next caused by the so-called system. Optical lithography technology 100 times required novel discoveries to completely new materials, development is the result of Nancheng. Introduced as a sub-lithographic side for imaging purposes, this impedance masks an isotropic etching structure. In the same way, this sub-lithographic mask structure can be used at the same time.

Page 6 200416900 V. Description of the invention (2)

The so-called gap method is formed. First, `` a first mask with substantially vertical side walls is being formed and has been patterned, often using optical lithography. Technology to achieve. Thereafter, a very thin further mask layer is deposited on the surface of the first mask to cover the entire area to the estimated thickness. The horizontal layer area of the further mask layer is then removed using a non-isotropic etching method such that the lithographic mask remains on the sidewall of the first mask only once. Finally, the first mask is removed and the only secondary lithographic mask with its estimated thickness and gate length is transferred to the lower gate layer constituting the substrate for forming Purpose of lithography gate structure. However, the disadvantage of this conventional method is that the critical dimension is undesirably mutated in the lithographic gate structure formed by this method, and this essentially originates from the impedance material used, which is used. The impedance chemistry and the money engraving process used.

As the advanced product density, however, semiconductor structures having, for example, a gate length of less than 100 nanometers (e.g., 25 nanometers) are increasingly required and obtained. The gate length realization has a meaningful impact on the electrical properties of a semiconductor object. In addition, there is an increased need to integrate this sub-lithographic `` short channel '' gate structure in a conventional standard processing procedure, and it is used to manufacture the `` long channel '' gate formed by lithographic technology The structure is, for example, to be able to form an integrated circuit of an analog circuit and a digital logic circuit on the semiconductor module. Therefore, the present invention is based on the purpose of providing a manufacturing method for manufacturing a lithographic gate structure, an associated field effect transistor, and a

Page 7 200416900 V. Description of the invention (3) The associated inverter and an inverter structure are realized at the critical size and especially the gate is being reduced and used in combination with the conventional method It can be used to fabricate gate structures for lithography, which are being fabricated in a simple way. According to the present invention, it is measured by a method related to items 1 to 15 of the scope of patent application, and to item 16 and is characterized by the characteristics of an inverter structure related to the 7th scope of patent application. To achieve its purpose.

In particular, the formation of a mask using a patterned lithography technique with a photolithography technique that is substantially a vertical wall on a semiconductor substrate surface may form a gate at least structurally on the surface of the semiconductor substrate. The insulating layer, and then an interrogation layer is formed structurally at least on the surface of the gate insulating layer and the side wall of the mask. After performing a first-order directional coining method and removing the mask, a sub-lithographic gate structure is manufactured with a small critical dimension and without additional transitions directly from a gate layer. The printing step thus leads to a combination that has been improved with the conventional gate fabrication method of lithography. The secondary lithographic gate structure, which is particularly used in logic circuits, can then be formed in a particularly simple manner using the same manufacturing method, with the usual gate structure formed by lithographic technology. Is preferably used in analog circuits.

In particular, when a metal material using an interlayer is used, the metal gate junction of the lithography technique at the first time may be directly formed, and as a result, the electrical properties of the field effect transistor can be fully applied. improve. The gate layer preferably has a complex sequence with a regulating gate layer, which is directly formed on the gate insulating layer and used as a regulator

Page 8 200416900 V. Description of the invention (4) The individual semi- and work functions are used or a special one is to realize the combination factor. The good. In particular, the second pass-through region of the transistor field-effect transistor is used to substantially use the region in this way, and in this example the gate structure is connected between the orthogonal submicron and the positive submicron minimum dimensions. To achieve. The gate material used in the conductor material of the present invention and a preferred metal is then formed thereon. The gate insulating layer is preferably an oxide, an oxynitride has a dielectric with a relatively high dielectric constant. In the example, there is a dielectric material with a high relative permittivity. The insulating layer with a sufficiently large even leakage current property can be fully modified by using a method, and the semi-conductor orthogonal method for the direction of the body being added to the body is manufactured in a sub-lithographic manner to form On a first field effector substrate, one first and second, the relative shadowing technique is added. The shadowing technique is very strong, and a part of the cross section is formed to form a common partial gate junction. The transistor is turned on. The micro-formed cross-section is formed between the gate contact surface to the outside of the structure and the inside of the structure. A commutator structure, a plurality of wells, and gates are applied with a shadowing technique on the half to form the second and first platform areas. The and the use of this can be a product of the structure of the first conductive region to form a first patterned conductor substrate in the first well and into the second region and the second domain to connect the secondary source > pole contact electrode Touching the way, the minimum cost body field effect type and the plural two wells mixed with the mask are directly on, and the wells are pushed into the field. Into the well, lithography only falls on, only a further advantage is added, as described in the scope of further patent applications.

Page 9 200416900 V. Description of Invention (5) Sign. The present invention will be described in more detail with reference to the drawings and the embodiments. Fig. 1A is masked with a pattern, for example, to be added according to Fig. 1. Material 1 is used, and the other one is incorporated. Of course, S0I is used to form an example after using ions, that is, a recessed trench is implemented, and the crystal silicon may be bombarded by a substrate or the like. to make. A is used for the manufacture of the cover in Fig. 1, and the square groove isolation of the corresponding example is used at the same time, and it is selected to be used in the same way. In fact, according to the method of using a standard, there are (S, several wells to replace the material I) female α semi-gas phase expansion gate layer 2-1 silicon, oxygen permittivity lithography gate is used for picture quality The method of the present invention may be added to I), and the doping region is used as a material such as a conductor matrix or a structure L. Then, the solution of the dielectric structure of the nitride illustrates the steps of a lithography technique. Simplified sectional view, followed by lithography gate structure. First, a semiconductor substrate is prepared. In this example, a trench isolation and special

The semiconductor substrate is in the semiconductor semiconductor substrate, I I I material. A dopant is a layer of a solid material G which is formed. An example of this is called high dielectric, which heats one of the base substrates 1 of the insulating layer 2, and at the same time V semiconductors can be, for example, materials. ‘Specify this, and it ’s added, using solid materials’ to deposit or surface

Page 10 200416900 V. Description of the invention (6) The use of custom photoresist materials, which is obtained by optical lithography gate storage or has a gate structure LG with a medium to large gate length LG, and such as special Used in analog circuits. Finally, a masking layer MO is formed to cover the entire area of the lithographic gate insulation layer 2 and the lithographic gate structure LG, and a planarization is performed so as not to cover the lithographic gate structure. For LG, the results are obtained as illustrated in the cross-sectional view illustrated in FIG. 1A. The program of this traditional layer sequence is generated using a plurality of standard methods, and it is possible to realize the sub-lithographic gate structure here.

According to Figure 1B, in this example, using an additional optical lithography method, a further photoresist mask (not shown) is formed, and a specific partial area is exposed Because a photoresist structure can be stripped at least one of the lithography gate structure LG and one of the lithography gate structures thus covered are removed by a common etching method. In the same way, the lithography gate insulation layer 2 is also removed at this position. As a result, the opening is patterned by the lithography technique as illustrated in FIG. 1B. Negative masks are obtained.

Therefore, it is possible to manufacture a gate structure having a medium and a large gate length by using a particularly simple method, and simultaneously use a manufacturing method to fabricate a sublithography gate structure. Only the area of the opening 0 is illustrated as follows. In the example therein, the negative mask M0 patterned corresponding to one of the lithographic techniques of FIG. 1B is illustrated in FIG. 2 and maintained for reference. Symbols to mark

-Page 11 200416900 V. Description of the invention (7) Elements and layers, for this reason. The lithography technique has been described repeatedly with the positive mask M, such as the negative pattern glass substrate with a medium pattern (material). Normal, Bu-, Baiqian Temple is covered by a mask or sequence. The specific components are as follows. Figure 4 to Figure 4 are used to construct the fabric. Figure 1 to the description are being constructed. The first is a structure, the surface is in the middle, and the deposition and operation are performed. In the explanation of D, Fig. 3 The force mouth is added with the gate, and-is added, that is, the patterned mask can be similarly constructed in the same way as illustrated in Fig. 3. In this example, a negative mask can be made substantially according to the standard. The same reference symbols are marked again with the same or. For this reason, a detailed description of the field method is given below. 3 (In the oxygen reference dielectric of the female example 0 there are cross sections of the ground gates of the South It and a simplified photolithography step of a simplified effect transistor. The same reference symbols are identified or corresponded, and the product is positive. The processing engineer used for the type is correspondingly illustrated in FIG. 4A, and the technical gate junction element and a repeated description according to the figure) junction type mask glass) or 1 of the embodiment of the table Likou's deposition body substrate is shown in simplified form. It is explained in practical terms such as an insulating layer to form this. This includes depositing by its own method, a gate and / or a cover covering the whole. However, it is also possible. Put the position 'the secondary lithography technique and the lithography technique BPSG (chemical, at least the surface of the material produced on the surface, for example, the surface of the relative capacitance example) to form a thermal insulation layer. Phosphorus silicon is oxidized at the same thickness as the semiconductor. Oxidation rate of silicon

il_fc

Page 12 200416900 V. Description of the invention (8) However, what is preferably affected is the deposition over the entire area, which is known as one of the high-K materials, which means a dielectric with a high relative permittivity . Examples of such a dielectric are alumina dioxide (H f 00), aluminized silicon oxynitride (Hf Si ON), and the like. In contrast to ordinary silicon dioxide, this material has the same or modified gate coupling properties, meaning that it can have a sufficiently high thickness with a reduced control voltage. For this reason, in particular, the leakage current can be sufficiently reduced. Thereafter, a gate layer 4 is structurally formed at least on the surface of the gate insulating layer 3, that is, with substantially the same thickness. And, for this example, the gate insulating layer is formed only on the semiconductor surface and on the sidewall of the mask MO. Using the method of the embodiment, a structured deposition operation is affected in this example. By a sputtering method or addition, the product is the degree of ruthenium to be sunk or widened, and the electrical phase of the ground is selected. Qi and small N excellent material high school ο Chang a isomorphic method non-T} derivative-D. One it is half-charged, L} has 妲 P properties one} A method with C crystals with methods c D nitrogen-platinum junction with D method V, such as, according to the example of the product of V and C}, the material P sinks, The case C layer A is expected to belong to the method C drawing R, and the original gold deposit method in the sex sacrifice is a genus of 4 ruthenium. This phase is high, and the deposit is golden. Gas} phase pole, when the oxygen is removed by a 4 method airlock, and the layer D learns the degree}, the pole is V when the thick U is used, the C layer is R, and the or {子 者 {以 如

field. Material

And the function Page 13 200416900 V. Description of invention (9) Can be determined or selected. Depending on the number, the final thickness, the lithography technique is defined using phases and different grounds, one suitable for the gate purpose, and the other. The material is in principle several structures of the power crystal. At the same time, it is conceivable to cover the surface layer 4 of the conductor 1 according to the thickness of the oxygen and nitrogen layer 3 of the figure. For example, it has a work function, it must use a Sheath electricity is well known. 4 A, the thickness of the metal gate layer on the half surface and the thickness of the metal gate layer can be about 1 nm to about 1 nm according to the manner of the incorporation of each semiconductor material. The parameters such as a desired gate length, a desired and at the same time depend on the connectivity of the metal deposition operation. A gate length of the surgical gate structure is substantially the same using its thickness, and a plurality of sequences can be formed simultaneously on the gate layer 4 deposition method. In this example, a special gate layer (not illustrated) is directly formed on the surface of the insulating layer 3, and a gate layer having the lowest possible impedance is deposited thereon in order to adjust a working function. What needs to be pointed out in this example is the implementation of further layers corresponding to the adjustment of the working function or for defining the individual pressures, with multiple layers and for adjusting the working function to achieve the required high conductivity. The example method (S10N) is formed as the entire area of the gate insulated conductor wafer or the phase 1i wall in which the half of the mask M0 is vertical. The gate is deposited in the form of a T a N gate electrode layer with a thickness of 0 nanometers to 50 nanometers, and is provided on a conductive conductor material, which in turn has a thickness of 50

Page 14 200416900 V. Description of the invention The tungsten (W) or tungsten silicide (W S i) layer with a thickness of 100 nm to 100 nm is used as the low-permittivity gate layer. According to FIG. 4B, in an accompanying method step, a non-isotropic etch method is implemented to form the sub-lithographic gate structure SG at least along the sidewall of the mask MO. The non-isotropic engraving method is preferably performed on the metal gate layer 4 by using a reactive ion etching method (RI E Reactive Ion Etching Method). As a result, the intended lithography of the interstitial spacer or the gate structure is performed. SG is obtained with minimal functionality in critical dimensions. Thereafter, the gate insulating layer 3 can be removed at the same time in an area not covered by the sub-lithographic gate structure SG. A wet chemical removal is being performed and it is, for example, using a two-step process. In the same way, the gate layer 4 and the insulating layer 3 can be simultaneously patterned using a single method step or a plurality of method steps as illustrated in FIG. 4B. The gate insulating layer 3 can optionally be simultaneously maintained as a shielding layer for an ion implantation, and can be performed as soon as possible. Finally, according to FIG. 4C, the hard mask MO and the lithography gate insulator layer 2 constituting the substrate are removed in the region of the opening 〇. As a result, the lithography gate structure SG does not Be covered. In this example, for further processing procedures, there may be a known gate insulation layer 3 that can be held on the side wall of the gate structure SG of this sublithography process. Figure 4D shows a simplified plan view of the lithography patterning step of the further lithography gate structure SG, which uses a lithography gate structure for dividing the body into a plurality of sub-lithography gates Structural

Page 15 200416900 V. Description of the invention π) Cut the mask CM to perform. This step can be influenced, for example, after the method steps shown in FIG. 4B, and may also be selectively used in this step by filling and covering the coverage area between the sub-lithographic gate structures SG. It is carried out for protection purposes. According to FIG. 4D, using the method of the embodiment, only the central area of the gate structure S G of the orthogonal sub-lithography technology with the holding gate insulating layer 3 is covered by the cut mask C M. For this reason, uncovered areas can be removed using the usual #engraving method. Two opposite or parallel sublithographic gate structures were obtained in this way. For example, in order to use this method to complete the formation of a field effect transistor with a sub-lithography gate structure SG, it is further possible to perform the steps related to the method of FIG. 4E to FIG. 4G. The same reference symbols are used to mark the same elements or once again. For this reason, repeated descriptions are explained as follows. Relatedly, according to FIG. 4E, after the hard mask MO is removed, for example, by a wet etching method or an oxide etching method, a sidewall insulating layer 5 can be formed at the gate of the sub-lithography technology. The side wall of the structure SG is formed, and in this example, is also formed on the rear side of the gate insulating layer 3 at the same time. In this example, using the method of the embodiment, an insulating layer is structurally deposited on the ground to cover the entire area and then anisotropically etched back. After that, the so-called connection doped region 6 (extension) is formed on the surface of the semiconductor substrate 1 using a sub-lithography gate structure SG. The wall insulation layer 5 and the gate insulator 3 may be formed at the same time. Ground exists vertically

Page 16 200416900 V. Description of the invention (12) As a mask, a connected implantation I A is preferably being performed. For example, an oxide is used as a material for the first sidewall insulating layer 5. According to FIG. 4F, a second sidewall insulation layer 7 is then formed on the sidewall of the first sidewall insulation layer 5 in the same manner as the first sidewall insulation layer 5, such as nitride nitride (S i 3 N 4) is being used as an insulator material. Using this second spacer or the sidewall insulation layer 7 simultaneously with the gate insulation layer 3, the first sidewall insulation layer 5 and the sub-lithography gate structure SG, the source / drain doped region 8 is immediately Likou Yizhan 'the main tomb of the priests in the tomb 1 night,-^,: / 5, /,: Fin Lianyi ·? • Gu Is / D is preferably performed. Finally, according to FIG. 4G, a purification layer 9, using a planarization step and a sub-lithographic gate structure SG, is finally formed over the entire area in order to form the required source, drain, and gate contacts, and It is pulled back, and it is used to connect the source / drain doped region 8 at the same time as the gate structure SG of the sublithography technique. By way of example, B P S G (borophosphosilicate oxide glass) or an oxide may be used as the passivation layer 9. In this way, the desired field effect transistor with the sub-lithographic gate structure is obtained in the region 0 far from FIG. 1B. The advantages of this novel manufacturing method 1, in particular, the fact that a spacer formed on the side wall of a hard mask using lithography technology is not used as a further hard mask for one of the subsequent etching steps, and this step Used to make a primary lithographic gate structure but equivalent to the final secondary lithographic gate junction

P.17 200416900 V. Description of Invention (13) Structure. Relatedly, a second I engraving process is not required, and for this reason, the setting of the critical size and the refinement are sufficiently improved. This method of manufacture is particularly important for ultrashort-order lithography gate structures ranging in particular from 10 to 50 nanometers and particularly below 10 nanometers.

The so-called "gate trimming" process is no longer required. In this case, it is also possible in principle to manufacture planar transistors with different amounts of sub-lithographic gate lengths. Furthermore, in particular, for structural lines arranged at 45 degrees, for example, in this way, it is possible to achieve a minimum interval for all point ranges and the highest possible accuracy. Relatedly, a manufacturing method can be used to form a gate structure, which simultaneously has very large and medium and sub-lithographic ultra-short gate lengths. When a gate contact is used to make a contact, a problem arises in the sublithographic gate structure as described above. The method used to make the gate contact platform area (platform 璺) is described below.

5A and 5B show a simplified plan view of an orthogonal sub-lithographic structure SG with a regulating gate insulating layer 3 for illustrating the gate contact platform area of the first experimental example. The essential method steps in manufacturing, the same reference symbols are used to identify the same or corresponding components, and a repeated description is explained below. According to FIG. 5A, it is still possible to form a gate contact platform area before cutting the gate structure SG according to the lithography technique of FIG. 4D, and especially at the same time before the mask M0. Used in the orthogonal sub-micro

Page 18 200416900 V. Description of the invention (14,) 'One of the individual long sides of the shadow gate structure SG.

Relatedly, by using an optical mask PM_A, a substantially square opening OA is formed in each example in a region of the sub-lithographic structure gate structure SG. The lithography technique is patterned with a masking mask MO and removed simultaneously with the filling layer using the mask P M — A, wherein the filling layer can be selectively filled in the submicron The shadowing agent is provided between the gate structures SG, and therefore, the gate structure of the secondary lithography technology in the area in the opening OA is not completely covered. Thereafter, the opening OA is filled by using an electrically conductive material, and the metallic material is preferably deposited and then planarized as far as the mask MO. After this preferred CMP (Chemical Mechanical Polishing) method, a plan view of the lithographic gate structure SG illustrated in FIG. 5 is obtained, which is referred to as the gate contact platform area 1 〇Α here It is being formed in the area where the OA was opened earlier, and this allows the contact to be fabricated in a simple manner with the lithography gate structure SG. However, the disadvantages associated with this method are particularly high requirements related to the accuracy of the alignment of the optical masks PM-A.

6A and 6B thus show a cross-sectional view and a simplified plan view, which are used to illustrate the gate contact flat stage area in the manufacturing according to a simplified second experimental example, the same reference The symbols again label the same elements or layers, and for this reason, repeated descriptions are explained below. According to FIG. 6 A ′ according to the second test case of the optical lithography mask PM

Page 19-200416900 V. Description of the invention (15) A B does not have individual openings 0A, but rather has a single elongated opening, which reaches two long walls that exceed the gate structure SG of the sublithographic technique. This opening OB preferably has a sufficiently large distance from the long side wall opposite to the secondary lithography gate structure SG, thereby sufficiently reducing the requirement for the accuracy of the optical lithography mask P M — Β to be set. . In order to avoid a short circuit between the gate contact platform region 10B and the lithographic gate structure SG side wall, an alternative filling method is performed here.

According to FIG. 6B, it is possible to perform a chemical oxidation or a selective oxide deposition in a gate contact insulating layer 2 A using the embodiment, and the insulating layer has a thickness of 10 nm. For example, on the semiconductor substrate 1. For this example, where the gate contact platform region 10 B is formed in a semiconductor region, and it already has a trench insulator (for example, Sing I, shallow trench insulator), this gate contact insulation Layer 2 A can be obtained.

Thereafter, an electrically conductive layer is formed again, and is preferably selectively deposited on a gate layer, a metal layer or a highly doped polymer layer of the sub-lithographic gate structure SG. The interstitial layer is once again being deposited to cover the entire area. Finally, a non-isotropic etching method is performed in order to form the spacer. In order to form the spacer structure, it is illustrated in Figure 6B, thus preventing the individual gates from contacting the platform area 10B and adding a sufficiently large platform pad. Because this processing procedure aligns itself, the requirements imposed by the alignment accuracy are sufficiently reduced in the example of this second experimental example.

Page 20 200416900 V. Description of the invention (16) Figures 7A to 7C show some simplified plan views to explain the essential method steps in manufacturing the integrated field-effect transistor inverter structure, as described above. This time the lithography gate structure was used. The method described here is particularly suitable for SOI (silicon on insulator) wafers, so that the same gate material and especially the same metal can be used in this example for a variety of different F E T s. According to FIG. 7A, firstly, one of the first conduction patterns η is doped in the first well region 1 1, and a second crystal is doped in the region 1 2 later.

A second conductivity type ρ is formed in the semiconductor material 1 with respect to the first conductivity type. As described earlier, the lithographic technique has been patterned with a positive mask M01. In this example, it is formed on the semiconductor material 1 in an orthogonal manner, using this method, A first partial cross section is formed on the first well incorporation region 1 1, and a second partial cross section is formed on the second well incorporation region 1 2. According to FIG. 1A, the use is made by a forward mask MOI, in which substantially half falls in the well-incorporating region 11 and the other half falls in the second-well incorporation region 12.

According to FIG. 7B, after that, according to the method steps described above, an orthogonal sub-lithographic gate structure SG with its gate insulating layer 3 is applied on the side wall of the positive mask MOI. Is formed, and the mask is removed at first. However, the segmentation of the lithographic gate structure SG is not performed. Thereafter, as described previously, the drain-doped region is substantially formed in the orthogonal gate structure SG, and the source-doped region is formed.

Page 21-200416900 V. Description of the invention (17) is substantially formed on the outside of the orthogonal gate structure SG, and the first and second scenes are incorporated into the regions 22 and 12, of course. The source and drain doping regions have corresponding insertions for individual well doping regions. A common gate contact platform region 1 0 C is formed here in a region between a junction between the first and second well doped regions 11 and 12, in one example However, the opposite part of the long side of the sub-lithographic gate structure SG is allowed here to be electrically connected to another. Finally, in order to make contact with the source doped region, the source S is formed only outside the vertical sub-lithographic gate structure SG, and a drain contact D for contact with the drain doped region, Only in the vertical sub-lithographic gate structure SG is formed, and a gate contact G is formed in the common gate contact platform area 10 C. This results in the field-effect transistor inverter, which is illustrated diagrammatically as in FIG. 8 using a simplified form of an equivalent current diagram, and having a particularly simple and space-saving construction. The present invention has been described above based on a vertical sub-lithographic gate structure. However, it is not limited to this, and it also contains alternative forms or structures that make use of this approach. Furthermore, an inverter structure has been described with the gate doped region and the associated drain contact, which falls into the vertical gate structure. However, in this way these can also fall outside the vertical gate structure at the same time, so the source incorporation region and the associated source contacts move inward.

Page 22 200416900 Figures Patterns Figures Figures Drawings Drawings Drawings Drawings Drawings Drawings Brief Description 1 A and Figure 1 B are used to illustrate the manufacture of a mask in which a lithography technique has been patterned Simplified sectional view of essential method steps. 2 shows a magnified view of a negative mask patterned by lithography. 3 Shows a magnified view of a positive mask that has been patterned by lithography technology. 4A to 4C show simplified cross-sectional views illustrating the essential method steps in the fabrication of a lithographic gate structure. 4D shows a simplified cross-sectional view illustrating the essential method steps in the fabrication of a lithographic gate structure. 4 E to 4 G show simplified cross-sections illustrating the essential method steps in the fabrication of a field effect transistor with a sub-lithographic gate junction. 5 A and FIG. 5 B show diagrams illustrating Simplified cross-sections of substantial method steps in the manufacture of the gate contact platform region of the first embodiment 0 6 A and FIG. 6B show schematic method steps used in the manufacture of a gate contact platform region of the second embodiment The simplified cross sections C-7 A to 7 C show simplified plan views illustrating the essential method steps in the construction of a field effect inverter. 8 shows a simplified circuit diagram of a field effect inverter as illustrated in FIG. 7. 2 Lithography Technology Gate Insulation Layer 4 Gate Layer Element Symbol Description: 1 Semiconductor substrate 3 Gate insulation layer Logical circle m

200416900 Brief description of the drawing 5 First sidewall insulation layer 6 Connection doped region 7 Second dart wall insulation layer 8 Source / drain doped region 9 Passivation layer 1 0 A, 1 〇B, 1 〇C Gate contact Platform area 11, 12 First and second well doped areas SG sub-lithography gate structure LG lithography gate structure 0, 0A, 0B Mask openings M0, M0-I Patterned masks P M — A, P M — B Optical lithography technology mask C M Cutout mask S source contact point D drain contact point G gate contact point

Page 24

Claims (1)

200416900 VI. Scope of patent application 1. A method for manufacturing a secondary lithographic gate structure for a field-effect transistor a Material: Basic take i — Basic bean: \ Guiding half of the next prepared bean (manufacture.} .) Wall 1 side I 〇 Straight M vertical, ground 2 texture 'real 〇 face M surface C cover / ^ X cover 1 dagger C / 1 case material map base shadow micro guide half into this shape) with b With its 3 / (layer edge absolute gate-the forming geomorphic structure should be at least as low as the above table d layer edge absolute wall-^ the I is less than I to 0 to M) 2 4, (0 layer M pole C gate cover is covered with the shape and the ground surface is constructed}) 3 side wall cover should be used in the way and carved in the way, ^ 'X] / Sex G to S square C and other non-structured poles The gate into the shadow) micro; e times into OM 2 OM. () Cover G Cover S The C destructuring and transfer} Pole f Gate shadow Micro times Hai = Mouth exposure in the shape of Shen Rjia plus step by step • In the 2 incorporation and in the incorporation. Chinese ^ 4 " The basics, a) method, 1 side away from the spacer of the trough, the base of the groove, the first guide of the ditch body, half of the vanilla Yuli Chengzhu master month a well-or step Weiweiwei, work in progress In its shape, in terms of French and Canadian terms, the} term, 2 2, the 0th or M term, C 1-i, the concealed type Fan Yili. Special, cover Please cover the application of the case • b Figure 3 λ 1 / b of the sudden shadow gathers the step 3 of its legal method. 1, 巳 $ v #-专 主 弓 = σ as 4 25 Page 25 200416900 VI. 91 layers in the scope of the patent application. The micro-gate C of the pole surface gate on the edge of the C} material G base L body C guide structure half-junction the pole at the gate into f; Add the micrograph of the absolute gate to form the quilt \) / GL / (\ struct., The micrograph of the upper surface gate}-2 less C to the layer edge and the \) / 2 / (\ edge Absolute pole gate Hai = ° in formation; plus 3 by G \) / I— ^ ο (Μ Structure C junction layer pole shield gate shadow 1 micro-Hai Shi 5 to structure pole gate shadow micro-as low as Exposure to travel to increase the process and pass the dagger; / 1 Tan} flat G structure 2 junction gate, shadow 0 μM C cover 2 cover the negative edge of the C-type layer should be a polar gate to shadow, remove The basic shifting is based on one plus one band and one G less L steps. In the shape, they are added and are added by the method} of the second, item I 2-0 or M item C 1 cover the envelope type. Fan Zheng The cover is a cover, and the special case is Ifli like a shadow. B micro 5 is one of the method or method, and the item is one of the item 1 of the oxygen item 5, and the second item is the chemical item of oxygen 1 1 No. Wei Zhong Benefits: Special C Please apply the steps as shown in Figure 6 to form a solid surface to add a quilt. Electricity} 3 rate C The capacitance of the capacitor's electrical edge to the absolute phase of the gate should be adjusted in order to have a tool. In the square of the law, add 1 to the 4th term of the C 6th level of the J to the gate term r ~ H, and the range of the middle circle / -X and d. Please follow the steps. 7 in the middle Page 26 at the gate. It should be added as appropriate, and the sequence is layered on one side, and the table pole items are many. The gates are one of the three resistances, and the resistance is in the C resistance. Go to the gate level. Item plus 9 this and this} 1 is surrounded by 4th / -X and surrounded by 4 normal patterns with layers ^ (benefit, extremely profitable layer can only be added to the gate, please apply for the gate application) as the claim If 4 works like, · —all at the same time. The middle layer should be 9 of which 1 is extremely conformable. 200416900 6. Application for patent scope 8 · For the method of applying any one of the patent scope items 1 to 7, in which the The gate layer (.4) is formed of a metal material. 1 1. The method according to any one of claims 1 to 10 in the scope of patent application, wherein, in step e), the gate layer ( 4) and the gate insulation layer (3) is patterned in a method step or in a plurality of method steps. 1 2 · The method according to any one of claims 1 to 11 in the scope of patent application, wherein, before or after step f), the lithographic patterning of the sub-lithographic gate structure (SG) is performed by a A cutting mask (CM) is performed to divide the integrated sub-lithographic gate structure (SG) 1 into a plurality of sub-lithographic gate structure elements. 1 3 · If you apply for any of the items 1 to 12 of the patent scope Page 27 200416900 6. Scope of Patent Application Page 28 200416900 6. Scope of Patent Application Form the source, drain, and gate contacts. 1 6 · A method for manufacturing an integrated field effect transistor inverter with a lithographic gate structure, which has the following steps: forming a plurality of field effect currents of a first conductor type and a second conductor type Crystal, the second conductor type is relative to the first conductor type, as described in item 15 of the scope of patent application, where In step a), in a first well incorporation region (1 1) of the first conductor type (η), a second well incorporation region of the second conductor type (ρ) is formed. In the semiconductor substrate (1), in step b), the lithographic patterned mask (MO-I) is formed on the semiconductor substrate (1) in a right-angled manner and in a consistent manner, using this method A first part is formed on the first well insertion area (1 1) and a second part is formed on the second well insertion area (1 2); in step f), a A vertical sub-lithographic gate structure (SG) is formed, which is located in the first and second well doped regions (11, 12), A common gate contact platform region (1 0 C) is formed in this way between the first and the second well-doped regions (1 1, 1 2), so that the sub-lithographic gate structure The opposite part of (SG) is connected to another; and the source contact (S) in the example is formed only outside the vertical sub-lithographic gate structure (SG), Page 29 200416900 VI. Patent Application Drain contact (D) is formed only in the vertical sub-lithographic gate structure (SG), and gate contact (G) is in the common gate contact platform area ( 10 ° C :) was formed. The first guide is the first to the second and the second one, the first part and the second part have the first} to the concrete, the first phase, the second, the second, and the second. 1 Junction Yu Junjie} {The polar domain dielectric device becomes the η domain gate region, and the gate crosses into the C region} The reverse state is entered, a positively doped C-junction, a type I doped well, and a crystal guide. Well ¾. The second ^ ~ -electricity 1 of the second conduction layer, the C response ^ ~ ^, the first transmission edge and the field connection C, the first area of the area, the first pole of the interbody area is at P The integration of the gates into a single phase in the contact area with the mid-state pairs is very close to the shape of a well in the junction area.一} Guide system physical gate mixed with 7th first state transfer zone with one well, one, one, two, and two wells, and domain two: two; area number} ^ other platform and G and G leveling s S to C to C Touching a structure and a structure} followed by the first and the last G pole, the pole and the pole, the gate is closed at the gate D and the transaction is completed, with the shape of the positive S, and the area of C plus the plus contact area Accessed place} 地} pole dopant 2 quality 2 gate {{1 {及 1 and ?? 1 «7 y 〇 domain 1 domain 1, domain contact area 1 ^ polar area access C into C into} Doped domain, doped C, polar region, polar region Page 30