1262571 玖、發明說明 【發明所屬之技術領域】 本發明係關於一種檢測方法，且特別是有關於一種半導體 製程之檢測方法。 【先前技術】 在*積體電路的製程中，每個製程的完成度都會影響到 其後續製程的精密度與完善性，I而影響到整個積體電路 的效能。因此在重要製程前後的檢測程序，除了可以針對 此片晶圓做必要之改善外，更可確保其後之製程不會受此 道製成程序影響’而造成晶圓毀損，$而全面性的提升製 私良率’以提南生產效率，辦λα成太4、， —^ 文羊私加成本效盈。所以缺陷檢測 實是製程改進的重要依據。 尤其對於半導體產品（如晶圓、晶片、iC)，盆成口往 ，牵涉多個製程步冑，若未能確實於每—道製程；驟；即 日*=3*發現重要製程缺陷，掛於德續所推― 曰对於傻，所進仃之多道製成程序， 會成為一種無意義之浪費。 然而，影響每-道製程步驟之缺陷並不相同 一道製程步驟前或後，均進行全面柯 母 費時間的。尤其在半導體製程中，可 田浪 U明日守間即是金 能有效率地降低每個待測品的測試時間，對於待 右 此龐大的廠家而言，無疑地將會節省 “里如 汁夕的成本支出。 5 1262571 口此，如果能夠找出一種能同時兼顧半導體產品 效率血立口# u ^ 一，、叩貝之檢測方法，將會是一件非常具有產業價值 的工作。 、 【發明内容】BACKGROUND OF THE INVENTION 1. Field of the Invention This invention relates to a detection method, and more particularly to a method of detecting a semiconductor process. [Prior Art] In the process of *integrated circuits, the degree of completion of each process affects the precision and perfection of its subsequent processes, and affects the performance of the entire integrated circuit. Therefore, in addition to the necessary improvements in the wafer process before and after the important process, it can ensure that the subsequent process will not be affected by the process of the process, resulting in wafer damage, and a comprehensive Improve the production and production rate to 'Tennan's production efficiency, do λα 成太4,, ^^ Wenyang private cost-effective. Therefore, defect detection is an important basis for process improvement. Especially for semiconductor products (such as wafers, wafers, iC), basins are involved in the process, involving multiple process steps, if not sure in every process; sudden; today *= 3 * found important process defects, hanging on Desirable to push - 曰 For stupidity, the multi-channel manufacturing process that becomes involved will become a meaningless waste. However, the defects affecting each process are not the same. A full length of time is spent before or after a process step. Especially in the semiconductor manufacturing process, the company can effectively reduce the test time of each product to be tested. For the huge manufacturer to be right, it will undoubtedly save "little juice". Costs. 5 1262571 If you can find a way to consider the efficiency of semiconductor products at the same time, the detection method of mussels will be a very industrial value. content】
口因此本發明主要目的係在於提供一種能同時兼顧產 口口生產效率與其品質之檢測方法。 、 本务明之另一目的係在於提供一種能即時警告使用者 進行缺卩63修復之檢測方法，避免後續製程步驟之浪費。 本發明之再一目的係在於提供一種藉由特定缺陷之數 目’來預測晶粒電性特性之檢測方法。 π〜根據上述之目的，本發明提供一種檢測方法，可於一 ^疋層上，藉由對特定缺陷類別進行檢測，同時計數此缺 陷類別在單一晶粒上之數目，進行晶粒良率預測。 根據本發明之檢測方法，首先對一晶圓特定層上之缺 陷進行分類，同時計數相對應之缺陷數目，來決定出此選 定層中最主要之缺陷類型，接著預測一晶粒不良，當晶粒上 之缺陷數目大於m，其中此特定值係藉由比對歷史紀 錄之製造完成後之晶粒良率與對應之特定類別缺陷數目所定 出此外Hx明還包3建立檢測晶粒良率之缺陷數目關鍵 值的方法，其係比對歷史紀錄之一製程後晶圓上各晶粒之特 定缺陷類型之缺陷數目，與歷史紀錄之完成製造時，對應上 述各晶粒之電性測試結果，來建立失敗晶粒缺陷數目模型， 6 1262571 獲得一關鍵缺陷數目。 於進行晶粒良率預測時 陷數目大於此關鍵缺陷數目 電性失敗。亦可預測晶圓於 【實施方式】 ，當單元晶粒上之特定類型缺 時，即可依此預測最終晶粒之 製造完成後之不良晶粒之數目。 鲁根據本發明之檢測方法，本發明會先針對每—道製程 輊序，分別建立對應之晶粒失敗缺陷數目模型，藉以分別 作為每-道製程程序之比較基準。第i圖所示心據：發 明=佳實施例建立晶粒失敗缺陷數目模型之流程圖。值^ 注意的是，本發明之流程方法可適用於任何半導體產品。 換言之，使用者可根據不同之半導體產品，來分別建=其 關鍵層之晶粒失敗缺陷數目模型，以作為晶圓良 ς 基準。 平乂 π —依此，在步驟丨00中，使用者於一晶圓之製造流程中， 鲁遠疋欲建立晶粒失敗缺陷數目模型之半導體製程。接著於 步驟102,於此選定半導體製程所形成之選定層上，進行 缺陷檢測，根據本發明之較佳實施例’任何習知之缺陷檢 =方法均可用於本發明中，例如可使用習知之自動缺陷叶 數和分類功能，讓工程人員得知單位面積缺陷數目，並可 據材料性夤或指定的特性參數來進行缺陷分類作業，以 •=得各缺陷類別對應之數據。藉由此數據，工程人員可判 定出現在此選定層中主要之缺陷類別，和各類別平均出現 1262571 之缺陷數目。 例如，根據本發明之較佳實施例’利用一習知之缺陷 計數功能，來掃瞄此晶圓上之選定層，即可描繪出如第2A 圖所示選定層中每一單位晶粒之缺陷數目’其中區域 201、202和203分別代表不同之缺陷平均數目。接著，可 再以習知之缺陷分類功能，對此選定層上檢測出之缺陷進 行分類，以描繪出如第2B圖所示於此選定層上，各種不 同類型缺陷分佈狀況，其中區域204、205、206和207分 別代表不同之缺陷類別。接著，可將第2A圖和第2B圖之 檢測圖形進行比對，來判定出影響此選定 類別。例如，若第2 A圖中，區域2〇丨所 ' 均數目最多，而對應至第2B圖， 之之、曰、’ 別。因此，依此推出影響此選定層1為/= 204之缺陷類 均數目Μ在第2C圖中之區域2〇8處特。《缺陷類別和其平 接著進行此晶圓後續之製程步驟，去 均完成後，於步驟1G4，進行 =所有之製程步驟 圓上各晶粒之電性測試結果。接著於測4，藉以獲得晶 進行之選定層缺陷檢：者：=;。6中，會將步 終晶圓電性測試做-關連性^驟叫所進行之最 和此選^層*特定類型缺陷數 二得出電性失敗晶粒 缺陷數目模型，此模型 …來建立失敗晶粒 模型建立後，即可在得知缺關鍵缺陷數目。當此 預測’亦#，可根據較層之同時進行晶粒之良率 粒之良率預測’當此選定層中：2_、陷數目來進行最終晶 早凡晶粒上之特定類型缺 8 1262571 陷數目大於此闕鐽缺 ^ ^ ^ # ^ a,噼數目柃，即可依此模型進行判定， 會造成取終晶粒之電 到疋 成後導致晶粒不良之數广進一步預測晶圓於該製程完 建立之晶粒失敗缺Λ二：依據複數個關鍵製程所 、 曰數目核i所得之晶粒不良做$ 级 以推測製造完成後之曰π μ曰1 个氏做資對，耩 之日日圓上晶粒不良總數目。 多閱第3圖，為根據本發明之方法所立 敗晶粒缺陷數目模型。並 之特疋層失 成工甘姑^ /、中第3圖所不之選定層為閘氧化 層’而/、特疋之缺陷類型為 為曰形（Plt)缺陷，第3圖之 X軸為母一個晶粒上所且缺 品V 土上 卜4.、目,丨气社罢 I之缺數目，而Υ軸為對應之電 性仏口果，於此測試甲，分為兩種失效測試（Fai… r m^ "，J"] ^ (S〇〇d die} ° ^ ^ ^ ^ u所建立之失敗晶粒缺陷數目模型，纟關鍵數目為 48。亦言之’當半導體製程於完成閘氧化層後，本發明之 檢測方法會進行晶圓缺陷之全面性檢測，並針對㈤陷形缺 陷進行計數，來統計出各單位晶粒上之凹陷形缺陷數目/，、 當此缺陷數目大於48個，可即時判定出此缺陷會造成&成 晶粒之電性失敗。值得注意的是，使用者可任;選擇^進 行檢測之製程步驟，例如，金屬蝕刻製程或閘氧化蝕刻製程 等，並不僅限於上述所述之閘氧化層。 參閱第4圖所系為一比較圖，其係用以比較使用本發 明模型進行晶粒電性失敗預測和依序完成所有製程之晶^ 電性測試結果。由圖中可看出，根據本發明方法所預測出 之第一晶圓中（wafer 1 )中，約有五個晶粒將造成電性失 敗，而實際上，於完成所有製程後之測試結果亦約有五個 1262571 晶粒是失敗的。而於圖中’亦 因此，可明顯看出，利用本發：：晶圓的比較結果’ 失敗’幾乎等同於實際情況。換」μ進行預測晶粒是否 高度之預測準確性。 、。之’本發明之方法具有 根據本發明之檢測方法 出，在選定檢測之層中合、Α 士 a建杈型日守，即以先決定 陷。換言之，在進行檢二，敗之特定類型缺 定類型缺陷數目進行計數，.，&疋層中僅需針對此特 缺陷數多於1鍵數目^加快檢測速度。且當 晶粒失敗，同時通知 ：預測出此缺陷數會造成 路連線使用，藉以即時通知相關°且可搭配任何網 綜上所述，本發明 ' 終晶粒電性特性合造成& = ^ ,，係先判定選定層中對最 陷類別下，、生^ H之缺陷類別，再決定出，於此缺 數目。：造=一晶粒電性失敗之缺陷數目，做為-關鍵 特：：進仃檢測此選定層時，在每一晶粒上，僅需針對此 關鍵：行缺陷數目計數，當此缺陷數目超過設定之 關鍵數目時，即可對此晶粒進行良率預測。 以pp雖然本發明已以一較佳實施例揭露如Λ，然其並非用 神民，本發明，任何熟習此技藝者，在不脫離本發明之精 〜la圍内，當可作各種之更動與潤飾，因此本發明之保 範圍當視後附之申請專利範圍所界定者為準。 81式簡單說明】 10 1262571 第1圖所示為根據本發明較佳實施例建立晶粒失敗缺 陷數目模型之流程圖； 第2a圖至第2c圖所示為根據本發明較佳實施例之檢 測圖形； 第3圖所示為根據本發明之方法所建立之特定層失敗 晶粒缺陷數目模型；以及 第4圖所示為使用本發明模型進行晶粒電性失敗預測 和依序完成所有製程晶粒間之比較圖形。 【元件代表符號簡單說明】 100至108 ··步驟 201至208 :區域Therefore, the main object of the present invention is to provide a detection method capable of simultaneously taking into account the production efficiency and quality of the mouth. Another purpose of the present invention is to provide a detection method capable of promptly warning the user to perform the defect 63 repair, thereby avoiding waste of subsequent process steps. It is still another object of the present invention to provide a method of detecting the electrical characteristics of a crystal grain by the number of specific defects. π~ According to the above object, the present invention provides a detection method for predicting grain yield by detecting a specific defect category on a layer and simultaneously counting the number of defects in a single grain. . According to the detection method of the present invention, first, the defects on a specific layer of a wafer are classified, and the number of corresponding defects is counted to determine the most important defect type in the selected layer, and then a grain defect is predicted. The number of defects on the granule is greater than m, wherein the specific value is determined by comparing the grain yield after the completion of the manufacturing of the historical record with the corresponding number of defects of the specific category, and the defect of detecting the grain yield is established by the Hx The method of determining the number of key values, which is the number of defects of a specific defect type of each die on the wafer after one of the historical records, and the electrical test result of each of the above-mentioned dies when the historical record is completed. Establish a model of the number of failed grain defects, 6 1262571 to obtain a critical defect number. The number of traps for grain yield prediction is greater than the number of critical defects. It is also possible to predict the number of defective dies after the completion of the final dies, when the specific type of the die on the cell is missing. According to the detection method of the present invention, the present invention first establishes a corresponding model of the number of die failure defects for each process sequence, thereby respectively serving as a comparison benchmark for each process. Figure i: The flow chart of the model for establishing the number of die failure defects in the preferred embodiment. Values ^ Note that the flow method of the present invention is applicable to any semiconductor product. In other words, the user can separately build a model of the number of die failure defects in its key layer according to different semiconductor products, as a benchmark for wafers. Ping 乂 π - Accordingly, in step 00, the user in the manufacturing process of a wafer, Lu Yuanyi wants to establish a semiconductor process of the number of die failure defects. Next, in step 102, a selected layer formed by the semiconductor process is selected for defect detection. According to a preferred embodiment of the present invention, any conventional defect detection method can be used in the present invention, for example, conventional automatic use can be used. The number of defective leaves and the classification function allow the engineer to know the number of defects per unit area, and can perform defect classification operations according to material properties or specified characteristic parameters, and obtain data corresponding to each defect category. Using this data, the engineer can determine the major defect categories that appear in this selected layer, and the average number of defects in each category of 1,262,571. For example, in accordance with a preferred embodiment of the present invention, a conventional defect count function is used to scan selected layers on the wafer to delineate defects in each of the selected layers in the selected layer as shown in FIG. 2A. The number 'where the regions 201, 202, and 203 represent the average number of different defects, respectively. Next, the defects detected on the selected layer can be further classified by the conventional defect classification function to describe the distribution of various types of defects on the selected layer as shown in FIG. 2B, wherein the regions 204, 205 , 206 and 207 represent different defect categories, respectively. Next, the detection patterns of Figs. 2A and 2B can be compared to determine the influence of the selected category. For example, in the second picture A, the area 2 has the largest number, and corresponds to the 2B picture, 曰, '. Therefore, the number of defect classes affecting the selected layer 1 of /= 204 is accordingly introduced in the region 2〇8 in the 2C chart. The defect type and the level of the subsequent process steps of the wafer are completed. After the completion of the process, in step 1G4, the electrical test results of the respective grains on the circle are performed. Then, at the test 4, the selected layer defects detected by the crystal are obtained: ::; In the 6th, the end-of-line wafer electrical test will be done-related, and the number of defects of the specific type will be determined. After the failure grain model is established, the number of critical defects is known. When this prediction 'Yes #, can be based on the comparison of the grain yield yield of the grain at the same time. 'When the selected layer: 2_, the number of traps is used to make the final crystal grain, the specific type of grain is missing 8 1262571 If the number of traps is larger than this ^ ^ ^ # ^ a, the number of turns is 柃, and the model can be judged according to this model, which will result in the number of die defects caused by the power of the final die. The failure of the die set up after the completion of the process is as follows: According to the number of key processes, the number of defects obtained by the number of cores i is made to the level of 曰μμ曰1, after the completion of the manufacturing. The total number of grain defects on the Japanese yen. Referring more to Figure 3, there is a model for the number of grain defects that are defeated in accordance with the method of the present invention. And the special layer of the lost layer is not the same as the selected layer of the gate oxide layer 'and /, the characteristic defect type is the lt-shaped (Plt) defect, the X-axis of the third figure For the mother, one of the grains is missing and the V is on the soil. 4. The purpose is that the number of the sputum is the number of defects, and the axis of the sputum is the corresponding electrical sputum. Test (Fai... rm^ ", J"] ^ (S〇〇d die} ° ^ ^ ^ ^ u established the number of failed grain defects, the key number is 48 48. Also say 'when the semiconductor process is After the gate oxide layer is completed, the detection method of the present invention performs comprehensive detection of wafer defects, and counts (5) trap defects to count the number of recessed defects on each unit crystal grain, and the number of defects More than 48, it can be immediately determined that this defect will cause & morphing electrical failure. It is worth noting that the user can do; select ^ to perform the process steps of detection, for example, metal etching process or gate oxide etching process And the like, and is not limited to the above-mentioned gate oxide layer. Referring to Fig. 4, it is a comparative diagram, Used to compare the results of the crystal electrical failure prediction using the model of the present invention and sequentially perform the crystallographic test results of all processes. As can be seen from the figure, the first wafer predicted by the method of the present invention (wafer 1), about five dies will cause electrical failure, but in fact, after completing all the processes, there are about five 1,261,751 dies that fail. In the figure, it is obvious. It can be seen that the comparison result of the wafer: 'failure' is almost equivalent to the actual situation. The "μ" is used to predict whether the grain height is predicted or not. The method of the present invention has the detection according to the present invention. In the method, in the selected detection layer, the Α a 杈 杈 杈 杈 , , , , , , , 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 In the layer, only the number of defects is more than 1 key, and the detection speed is accelerated. When the die fails, it is notified that the number of defects is predicted to cause the connection to be used, so that the relevant time can be notified and can be matched with any In summary, the present invention's final grain electrical characteristics result in & = ^ , which determines the defect category of the selected layer in the most trapped category, and then determines the defect number. :: = the number of defects in a die electrical failure, as a key feature:: When detecting this selected layer, on each die, only need to target this key: the number of row defects, when this defect When the number exceeds the set critical number, the yield prediction of the die can be made. pp Although the present invention has been disclosed in a preferred embodiment, it is not used by the gods, the present invention, anyone skilled in the art. It is to be understood that the scope of the invention is defined by the scope of the appended claims. Brief Description of Type 81] 10 1262571 FIG. 1 is a flow chart showing a model for determining the number of die failure defects according to a preferred embodiment of the present invention; FIGS. 2a to 2c are diagrams showing detection according to a preferred embodiment of the present invention. Figure 3; Figure 3 shows the model of the number of failed grain defects for a particular layer established by the method of the present invention; and Figure 4 shows the prediction of die electrical failure using the model of the present invention and sequentially completing all process crystals. Comparison graph between grains. [Simplified description of component representative symbols] 100 to 108 ··Steps 201 to 208: Area
1111