JPH08274139A - Test method of semiconuctor device - Google Patents

Abstract

PURPOSE: To provide a simple method by which the time required for testing a semiconductor device having many test items and many semiconductor chips to be tested in the stage of a wafer can be shortened. CONSTITUTION: The sampling locations from which wafers are to be sampled at the time of sampling wafers from one lot of wafers (11) are decided in advance by taking the in-plane distribution of the wafers into consideration and semiconductor wafers are selected only from the sampling locations and tested on all test items (12 and 13). Based on the results of the tests, the quality of the wafers is discriminated (14) and the acceptance of the lot is discriminated (15). Since the wafers discriminated as defectless wafers are not subjected to the succeeding tests to be performed next on semiconductor chips to be tested, the measuring time can be shortened.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for testing a semiconductor device, and more particularly to a method for testing a semiconductor device which shortens the test time at the wafer stage.

[0002]

2. Description of the Related Art In recent semiconductor devices, the number of semiconductor chips formed per wafer is increasing due to the densification of manufacturing processes and the expansion of wafer size.
The cost of electrical property testing at the wafer stage has also increased proportionally.

First, referring to FIG. 4, which shows an example of a conventional wafer test method in a process diagram, the wafer test method of this example first executes a test T1 when measurement is started ( (Fig. 4-401) If defective, move to the next chip, and if it is a non-defective product, execute up to test Tn through test Ti (Fig. 4-403 to 406), and if all test results are judged to be non-defective products (Fig. 4-403). 4-407) Calculate the number of non-defective products (Fig. 4-409) and move to the next chip (Fig. 4-41).
0).

That is, for all semiconductor chips in one wafer, all test items from the first test to the nth test are tested in order.

As a result, if a defect occurs, the measurement of the chip is terminated halfway and the test of the next chip is started.

However, due to improvements in semiconductor manufacturing technology, there are semiconductor devices that have stably obtained extremely high yields, and semiconductor chips sampled while the semiconductor device is still in a wafer state maintain high yields. If it does, the overall yield tends to be high even when viewed by lot.

Also, semiconductor devices in the same lot tend to exhibit similar characteristics, including that the manufacturing process of semiconductor devices is basically batch processing, and the overall characteristics are inferred from the characteristics of sampled chips. can do.

Next, based on the above-described tendency of yield state, an example in which some tests are omitted from the test items in a general semiconductor device test method is disclosed in Japanese Patent Laid-Open No. 60-42664.
No., published in Japanese Unexamined Patent Publication No. Referring to FIG. 5 in which the flow chart described in the publication is compared with the flow chart used in the embodiment of the present invention, the test method is similar to the general flow described above until the middle of the measurement flow. At the time of counting the number of non-defective products, it is compared with a preset value of the number of non-defective products (FIG. 5-501). If the number of non-defective products in the comparison result is less than the reference value, all test items are tested on all wafers (FIG. 5-502).

The characteristics of the lot will be examined based on the measurement results when the number of non-defective products up to the middle reaches the set value N. First, the total number of tests and the number of non-defective products are counted, and the measurement results of each test item Ti are saved. When the number of non-defective products exceeds the set value N, the measurement is interrupted and the test results up to that point are examined. Enter (Fig. 5-503). The yield was obtained by dividing the number of non-defective products by the total number of tests (Fig. 5-504), and then statistical data such as the average value and standard deviation of each test item was calculated from each measurement data (Fig. 5-505). Comparison with similar statistical data and reference values of past lots is performed (Fig. 5-506, 50).
7). As a result, the test item whose data is within the reference value is skipped (FIG. 5-508), and the skipped test item is not tested for the rest of the chip under test.

In the skip measurement (FIG. 5-509), if the test is skipped (FIG. 5-510), the test Ti is skip-measured (FIG. 5-511). If the test result is a non-defective product, the number of non-defective products is counted, and if it is defective, the next chip is moved (FIGS. 5-512 to 515).

As described above, in Conventional Example B, the skip of each test item is determined without changing the configuration of the entire measurement flow, and the total test time is shortened.

On the other hand, another conventional example in which some tests are omitted is described in JP-A-60-226132.
Referring to FIG. 6 in which the process diagram described in the publication is also shown in comparison with the process diagram used in the embodiment of the present invention, the test method is such that at the time of counting the number of non-defective products, the preset value of the number of non-defective products is preset. It is the same as the above-described conventional example up to the point where the yield data is calculated (Fig. 6-601 to 604).

Next, when the measurement result is examined, the change of the measurement order of each test item is considered. That is, when the measurement result is examined, the number of defects by test item is totalized and the test item is reviewed (FIGS. 6-605 and 606). For the content of the review, omit the test items that have no defects (Fig. 6).
-608), the order is changed so that the test is performed from a test item having a large number of defects and a test item having a short test execution time (Fig. 6-609), and the test is executed by the flow after the order change (Fig. 6-609). -610). Through this review, defects can be detected earlier than when the order is not changed, and at the same time, tests are omitted for test items that do not generate defects, with the aim of shortening the total test time.

[0014]

These conventional semiconductor device testing methods are described in the conventional example described with reference to FIG.
In addition to counting the number of non-defective products for each test item of the chip under test, it is necessary to secure a data area or storage device for storing actual measurement data and similar past data, and whether test items can be omitted. Since the standard is obtained from the measurement results of the same type of semiconductor device in the past, a larger data storage area or storage device is required in proportion to the increase in the production amount, the number of test items, and the number of chips under test.

On the other hand, in the conventional example described with reference to FIG. 5, the measurement order of the test items is changed, but this method also increases the processing time for changing the test order in proportion to the increase of the test items. Becomes

Therefore, in these conventional examples, due to the recent increase in the number of test items of the semiconductor device, the cost other than the pure test time of the semiconductor chip under test greatly increases.

The object of the present invention is made in view of the above-mentioned measures, and shortens the test time by a simpler method for the test of the test items and the semiconductor device having a large number of semiconductor chips to be tested at the wafer stage. To provide.

[0018]

The semiconductor device test method of the present invention is characterized by a semiconductor manufacturing method in which a semiconductor chip group is formed on a wafer, and a semiconductor for measuring electrical characteristics of the semiconductor chip is measured using an IC tester. In the device testing method, the first step and the first step of selecting all of the wafers in the lot and selecting the predetermined semiconductor chip located at a predetermined sampling test application position on these wafers. The second step of collecting the yield data for each wafer by performing all the predetermined test items only on the chips under test selected by, and dividing the number of non-defective products from the total number of chips under test from the yield data. A third step of classifying the wafers into predetermined classification items according to the obtained non-defective product rate, and a predetermined measurement determined in advance using the classification result of the third step. Lies in having a fourth step of selecting the lot from the flow.

Further, after the third step, it is possible to have a step of removing, from the wafers classified in the second step, those having a good chip quality of less than the second good product rate.

Further, the predetermined classification items are: wafers with good chips being at least a first good rate, and wafers having good chips being less than the first good rate and having a second good rate or higher. It is also possible to classify non-defective chips into wafers having the second non-defective product rate or less, and prepare a flag for each classification.

[0021] Further, the predetermined measurement flow includes a lot in which the number of good wafers in which the wafers for which the flag of the first non-defective rate is equal to or higher than the third non-defective rate is high are high, The wafer for which a flag equal to or higher than the non-defective product rate of 1 is obtained is the third non-defective product ratio or less,
Lots in which the existence of good wafers occupying more than the non-defective rate is medium, and lots in which the number of good wafers in which the flag having the flag of the first non-defective rate is less than the fourth non-defective rate are low It is also possible to have a flow divided into

Furthermore, in the measurement of the electrical characteristics, all predetermined measurement items are carried out for the total number of chips selected in the first step, and the second data based on the resulting yield data is used. In the third step, the total number of the wafers classified in the step or the remaining wafers after the wafers whose good chips are equal to or lower than the second non-defective rate are removed are classified in the third step and classified. As a result, the first of the lots of wafers in which the good wafer is high
For wafers having a non-defective product rate or higher and for wafers having the first non-defective product ratio or more and the second non-defective product ratio or more, only the peripheral portion is marked and the subsequent tests including untested chips are omitted. Among the wafers with a medium number of wafers, the wafers with the above-mentioned first non-defective rate or higher are marked only in the peripheral part and the subsequent tests are omitted including the untested chips. All the predetermined measurement items can be performed, and all the wafers in the lot in which the existence of good wafers is low can perform all the predetermined measurement items.

[0023]

DESCRIPTION OF THE PREFERRED EMBODIMENTS First, the present invention will be described with reference to the drawings.

FIG. 1 is a process diagram of a test method of a first embodiment of the present invention, and FIG. 2 is a plan view of a wafer showing sampling positions of semiconductor chips measured in this embodiment. Referring to FIG. 1 and FIG. 2 in combination, when measuring the electrical characteristics of a semiconductor chip using an IC tester, sampling points after the start of measurement are taken into consideration in consideration of the in-plane distribution of the wafer. Has been determined (indicated by black circles in FIG. 2), and all the test items are measured at the sampling points on all the wafers (FIG. 1-11).

Next, the process shifts to a process for examining the result of sampling measurement (FIG. 1-12). As a result of the sampling measurement, a value obtained by dividing the number of non-defective products for each wafer by the number of measured wafers is set as the yield of this wafer (FIG. 1-13). According to the obtained yield, the wafer yield is very good (90% or more in the example of FIG. 1), the yield is very bad (less than 10% in the example of FIG. 1), and the remaining yield is Classify into moderately good levels (10% or more and less than 90% in the example of FIG. 1) and set flag data for identification (FIG. 1-14).

At this time, the level at which the yield is extremely low ((c) in FIG. 1) is not removed. However, even if it is a defective wafer, if the extraction ratio is small, it will be measured to some extent in the total number of subsequent processes. This is because there is a possibility that the non-defective product can be saved. However, the measurement time is longer than that in the second embodiment described later.

Next, the wafer determination result is examined and lot determination processing is performed (FIG. 1-15). This lot determination is based on the number or ratio of good wafers in the lot, which is obtained by collecting the flag data set in the previous process.

The numerical value of the judgment criteria in FIG. 1 is one example, but when there are a large number of good wafers, that is, in the lot in which 90% or more of the wafers are judged to have 90% or more of good chips in step 14. In the case ((d) of FIG. 1), the number of good wafers is medium, that is, step 1
In the case of a lot in which 50% or more of the wafers determined to have 90% or more non-defective chips in 4 exist ((e) in FIG. 1), the number of good wafers is small, that is, step 14
In the case of lots in which less than 50% of the wafers were judged to have 90% or more non-defective chips in (1), the chips to be tested that were not measured depending on what level the lot corresponds to Processing is decided (Fig. 1-1.
5).

The processing of the semiconductor chips to be tested for which the lot is determined (FIG. 1-16) is not sampled in step 11 as the first processing when there are many good wafers ((d) in FIG. 1). It can be estimated that most of the unmeasured semiconductor chips under test are also good products, but at the semiconductor device manufacturing stage,
Especially when transporting diffused wafers to the storage stage, it is generally known that the peripheral area will be damaged by contact with transportation jigs, etc., so the peripheral area of a good wafer is considered defective and should be removed in advance. There is a need to.

Therefore, the lot (FIG. 1 (d); 90% or more) in which the ratio of good wafers is very high was only removed by the peripheral marking of the good wafers (the chip yield was 90% or more) and was not sampled. Steps in which the unmeasured semiconductor chip under test is not tested (Fig. 1-1
Select 7). A flow that selects only the removal of the wafers with a moderate proportion of the remaining good wafers (wafers having a good chip ratio of 90 to 10%) by the peripheral marking and omits the test of the unmeasured chips under test that are not sampled is selected. (FIGS. 1-18).

Since the test time in this case is (time required for sampling measurement + time required for determination), it depends on the sampling rate, but is greatly shortened compared to the normal measurement method.

Next, as the second processing, when the ratio of good wafers is medium (FIG. 1 (e); 50% to 90%),
For good wafers (having a good chip rate of 90% or more), the process of step 17 is applied to remove only by peripheral marking (Fig. 1-18), but for the remaining wafers, unmeasured semiconductor chips have the total lot. Since the possibility of defective outflow in the post-process is close to 50% at maximum, select the flow for 100% measurement (Fig. 1-18).

The measurement time in this case can also be calculated in the same manner as in the first process, but since there is a total measurement of 50% at the maximum, it can be shortened even in this case when the sampling ratio is small compared to the normal case.

Finally, as a third process, when the ratio of good wafers is low (FIG. 1 (f); less than 50%), unmeasured chips under test further increase the possibility of defective outflow, so wafer determination is performed. Select the flow for 100% measurement regardless of the result (Fig. 1-18). In this case, the test time will be longer than usual because practically all items are measured for all items and there is a study process for omitting the measurement.

Referring to FIG. 3 which is a process diagram of the test method of the second embodiment of the present invention, the difference from the first embodiment is that the non-defective rate in the wafer determination step in the first embodiment. Is to remove the defective wafer determined to be less than 10%. The other processing steps are the same as those in the first embodiment, and therefore the description thereof is omitted here.

That is, since the wafer having a very poor yield is removed at the time of wafer determination after the sampling measurement, the second embodiment is more effective when only shortening the measurement time is considered. is there.

According to the above-described test methods of the first and second embodiments, when performing sampling measurement after the start of measurement for each wafer in one lot, the sampling points are taken into consideration in consideration of the in-plane distribution of the wafer. Is determined, only the semiconductor chip chip at the sampling location is selected, and the quality of each wafer and the quality of the entire lot are determined based on the results of all item tests. With respect to the wafer determined to be good, the subsequent test of the semiconductor chip under test is omitted, which is effective in reducing the measurement time.

In particular, when it is applied to a test of a semiconductor device having a small size, a large number of chips per wafer, and a very good yield as a result, the extraction ratio can be set small, which is very effective. For example, when the sampling rate is set to 10%, the test time for a good wafer is 1/10 of the normal test method (all-chip all-item measurement method) except for the time required for determination. If the lot is composed of all good wafers, the measurement time for the lot is about 1
It will be 1/0.

Even if the test time becomes long as a result of the measured lots having low yields, if most of the other lots have very high yields, the application of this test method as a whole is This is very effective in reducing the test cost of the semiconductor device.

Even if the untested chips are defective, there is no final reliability problem because they are all tested in the screening test after the assembly process.

[0041]

As described above, according to the present invention, all the wafers in the lot are targeted, and the first step of selecting a predetermined semiconductor chip located at a predetermined sampling test application position on these wafers is performed. The second step of collecting yield data for each wafer by performing all predetermined test items only on the chips to be tested selected in the first step, and the number of non-defective products is checked from the obtained yield data. A lot is determined from a third process in which the wafers are classified into predetermined classification items according to the non-defective product rate obtained by dividing by the total number of test chips, and a predetermined measurement flow which is predetermined by using the classification result of the third process. The fourth step of selecting, selecting only the semiconductor chip chip at the sampling point, and judging the quality of each wafer and judging the quality of the whole lot based on the results of all item tests That. With respect to the wafer determined to be good, the subsequent test of the semiconductor chip under test is omitted, which is effective in reducing the measurement time.

Even if the test time becomes long as a result of the measured lots having a low yield, if most of the other lots have a very high yield, this test method cannot be applied. As a whole, there is a great effect in reducing the test cost of the semiconductor device. There is no final reliability problem because all tests are conducted in the screening test.

[Brief description of drawings]

FIG. 1 is a process drawing showing a test method of a first example of the present invention.

FIG. 2 is a plan view of the wafer showing the situation of the sampling measurement of FIG.

FIG. 3 is a process drawing showing the test method of the second example of the present invention.

FIG. 4 is a process chart of an example of a conventional semiconductor device testing method.

FIG. 5 is a process diagram of another example of the conventional semiconductor device testing method.

FIG. 6 is a process diagram of still another example of the conventional semiconductor device testing method.

[Explanation of symbols]

11-20 Processing step in the test method of the first embodiment 21 Wafer 22 Chip that is not a sampling measurement target 23 Chip that is a sampling measurement target 31-41 Processing step in the test method of the second embodiment 401-410, 501-525 , 601 to 610
Treatment process in the conventional test method

Claims (5)

[Claims] 1. A method of testing a semiconductor device, wherein an IC tester is used to measure electrical characteristics of a semiconductor chip in a process of manufacturing a wafer on which a group of semiconductor chips is formed, targeting all of the wafers in a lot. First step of selecting a predetermined semiconductor chip located at a predetermined sampling test application point on these wafers, and performing all predetermined test items only on the chip under test selected in the first step The second step of collecting yield data for each wafer and classifying the wafers according to predetermined classification items based on the yield rate obtained by dividing the yield data by the total number of chips under test from the yield data And a fourth step of selecting the lot from a predetermined measurement flow predetermined using the classification result of the third step. A method for testing a semiconductor device, comprising: 2. The method according to claim 1, further comprising a step of removing, from the wafers classified in the second step, wafers having good chips and having a second non-defective rate or less after the third step. Semiconductor device testing method. 3. The predetermined classification items are: wafers with good chips having a first good product rate or higher, and wafers with good chips having a first good product ratio or lower and a second good product ratio or higher. 2. The method of testing a semiconductor device according to claim 1, wherein the good chips are classified into wafers having the second non-defective rate or less, and a flag is prepared for each classification. 4. The predetermined predetermined measurement flow includes lots in which the number of good wafers in which the wafers for which the flag of the first non-defective rate is equal to or higher than the third non-defective rate is high are high, The number of non-defective wafers in which the number of non-defective wafers having the flag of 1 or more is equal to or less than the third non-defective rate and the number of non-defective wafers occupies the fourth non-defective rate is medium. 2. The method for testing a semiconductor device according to claim 1, further comprising a flow for dividing the wafer for which the flag is obtained into lots in which the number of non-defective wafers occupying the fourth non-defective rate is low. 5. The measurement of the electrical characteristics is carried out by carrying out all predetermined measurement items for the total number of chips selected in the first step, and by the yield data as a result of the second measurement. The total number of the wafers classified in the process or the remaining wafers after the removal of wafers whose good chips are equal to or less than the second good product rate are lot-classified and classified in the third process. As a result, among the wafers of the lots in which the good wafers are present in high numbers, the wafers having the first good product rate or more and the first good product rate or less and the second
For non-defective wafers above, the peripheral part is marked and untested chips are skipped, and subsequent tests are omitted. For wafers marked with only the peripheral part, the subsequent tests including the untested chips are omitted, and all other wafers perform all the predetermined measurement items. Is a semiconductor device testing method according to claim 1, wherein all the predetermined measurement items are carried out.