twfl.doc/006 95.1.12 y广 / 九、發明說明： 【發明所屬之技術領域】 本發明是有關於一種半導體元件結構的缺陷檢測方 法，且特別是有關於一種電性檢測的定位方法與半導體元 件結構的電性缺陷檢測方法。 【先前技術】 隨著超大型積體電路（ULSI)技術的持續發展，積 體電路的積集度也日漸提昇，而於製程中所產生的極 微小的缺陷就成為影響積體電路品質的關鍵。近年 來，用來檢測製程中所產生缺陷的缺陷檢測，已成為 製程中的不可或缺的標準步驟。 一般來說，缺陷檢測分為物理缺陷檢測與電性 缺陷檢測，以增進產品的良率。在電性缺陷檢測，半 導體元件電路的設計階段便會進行晶片電性缺陷檢測 的定位，亦即首先利用電路佈局與設計規則（design rule)等之資訊預測出晶片的電路物理位置（physical location)與電路檢測分析中電性位置（electrical location) 的相互關係，，以判定出電性缺陷的所在物理位置。 然而，預測晶片的電路物理位置會出現預測錯誤之判斷 或是電路檢測中程式錯誤，而造成電路檢測所顯示之 位置無法與物理位置相對應。 為解決上述問題，晶片電性檢測上還有一定位方 法。當晶片在經過半導體製造過程之後，晶片上的結構 往往會在製程過程中受到損害而產生一些缺陷，首先 5 猫 twfl .doc/006 95.1.12 I、有缺陷的晶片進行電性檢測’再將此晶片進行物 理分析（physical analysis)，如電子掃描顯微铲八 找出電性檢測所對應之物理位置，若：者戶’ :果r續應時，則修正電性檢測程式或：址打散丈 力月b (address s⑽mble funeti()n)，直到判定之缺 所在物理位置可對應電性檢測結果。另方= 利工照光的方式來觀看晶片上的缺 於： 位置，以致於在比對數據結果時，因數 崔= 而無法正確判斷缺陷的所在位置。此外I般的缺ί =測需要耗費大量的時間以及人力，而增加““ 【發明内容】 、、兵的目的疋提供—種晶片電性檢測的定位方 法，可用來修正檢測晶片的裝置。 ^發明的另-目的是提供一種半導體元件結構的電性 力本可減少電性檢測缺陷時所耗費㈣ 本發明另提出—種晶片紐檢_定位方法，此 、=提供-晶片，此晶片上已形成有經電路 二 3結構，其中此至少一導電結構包括具有物理位置㈣ 丄/—I缺陷。接著，利用電性檢驗裝置對晶片進行· 而得到邏輯數據結果。然後，將此邏輯數據結果^ 曰曰片上之假缺陷的物理位置資料進行比對。之 ς 1262^. wfl.doc/006 95.1.12 性檢驗裝置的修正。 、、依照本發明實施例所述之“·檢_定位方法， 上述之假缺陷是由導電結構經處理而短路或斷路所造成。 依：本發明實施例所述之晶片電性檢測的定位方法， w之處理例如為使用聚焦離子束(foGus _ ^，剛。 依照本判實施觸叙W雜檢剩定位方法， 極:之導電結構例如為金屬内連線、位元線接觸窗、或閘 法，工種元件結構的電性缺陷檢測方 結構。=對:二電；=成經電路設計的導電 的已知物理位置上萝作空小一加从a 、此彳迅、、、口構上 驗梦署盤μμ曰μ ^二乍至夕一假缺。然後，利用電性檢 來，、將此、羅二曰㈣订電性檢驗而得到邏輯數據結果。接下 後，修二二假缺陷的物理位置進行比對。之 "电私1双衣置。然後，利用修正後的電性;壯 置對晶⑽導電結構妨檢驗。 料驗裝 檢所述之半導體元件結構的電性缺陷 、/上以之處理例如為使用聚焦離子束。 依照本發明實施例所述之半導體 檢測方法，上诫>制从s, 僻〜电性缺陷 社槿卜沾甘t衣作至少一假缺陷的方法例如為使導带 、”σ構上的某—物理位置產生短路或斷路。 ¥电 檢測::本?，，所述之半導體元件結構的電性缺陷 、/ h之導電結構例如為金屬内連線、#_ 、 觸窗、或閘極線。 、、、位兀線接 12625忍 twfl.doc/0〇6 95.1.12 之後本為是在晶片上形成經電料計的導電結構 晶片谁二出電性上之假缺陷於已知物理位置上，再對 _!的道二电性缺陷檢測，修正電性檢驗裝置，可避免晶片 缺點。此外，太L 扣找不出正確物理位置的 行定位的牛把^在對晶片進行電性缺陷㈣前，先進 作= ^先利用聚焦離子束於晶片上製 到的邏輯數據結果與已知物理位㈨將所付 根據比對&果㈣μ ^置的缺進行比對，然後 片進行====驗裝置進行修正之後，才對一般晶 陷檢驗f置之r二、Q的所在位置。此種方式可避免因缺 =衣置之_度不高的_，而造成輯 且即名了檢測時間與人力。 勺决是 易懂二士?和其他目的、特徵和優點能更明顯 明如下。+ ‘貫施例，並配合所附圖式，作詳細說 【實施方式】 圖1為假缺陷的製作步驟流程圖。 f缺陷是用來作為電性缺陷檢測中的修i基準！^作出的 1，百先，於步驟100中，提曰 ％芩照圖 電路設計的導電处I。# ，、 "a ，b曰曰片上已形成經 構進行處理二收中’對此導電結 元線接觸窗插塞或減繼侧^ I焦離子束打在導電結構 j如疋使用 再將¥兒結構上的某-物理位 95.1.12 12625忍 twfl.d〇c/006 置連接起來而產生短路或切斷而產生斷路。Twfl.doc/006 95.1.12 y wide / IX, invention description: [Technical field of the invention] The present invention relates to a defect detection method for a semiconductor device structure, and in particular to a positioning method for electrical detection and A method of detecting an electrical defect in a semiconductor device structure. [Prior Art] With the continuous development of ultra-large integrated circuit (ULSI) technology, the accumulation of integrated circuits is increasing, and the extremely small defects generated in the process become the key to affect the quality of integrated circuits. . In recent years, defect detection used to detect defects in the process has become an indispensable standard step in the process. In general, defect detection is divided into physical defect detection and electrical defect detection to improve product yield. In the electrical defect detection, the positioning of the chip electrical defect detection is performed at the design stage of the semiconductor component circuit, that is, the circuit physical layout is first predicted by using information such as circuit layout and design rules. The relationship between the electrical location and the electrical location in the circuit detection analysis to determine the physical location of the electrical defect. However, predicting the physical location of the circuit of the chip may result in a prediction error or a program error in the circuit detection, and the position detected by the circuit detection cannot correspond to the physical position. In order to solve the above problem, there is also a positioning method on the electrical detection of the wafer. After the wafer has undergone the semiconductor manufacturing process, the structure on the wafer tends to be damaged during the process and some defects are generated. First, the cat is twfl.doc/006 95.1.12 I. The defective wafer is electrically tested. The wafer is subjected to physical analysis, such as an electronic scanning microshovel to find the physical location corresponding to the electrical detection. If the household is 'remaining', then the electrical detection program is corrected or: The address b (address s (10) mble funeti () n) until the physical location of the missing position can correspond to the electrical detection result. The other side = the way to watch the wafer is missing: position, so that when comparing the data results, the factor Cui = can not correctly determine the location of the defect. In addition, the I-like lack of measurement requires a lot of time and manpower, and the addition of ""the invention", the purpose of the soldier, and the positioning method of the wafer electrical detection can be used to correct the device for detecting the wafer. Another object of the invention is to provide an electrical component of a semiconductor device structure which can reduce the cost of electrical detection defects. (IV) The present invention further proposes a wafer inspection-positioning method, which provides a wafer-on-wafer. A circuit 2 structure has been formed, wherein the at least one conductive structure includes a physical location (4) 丄 / -I defect. Next, a logical data result is obtained by performing an on-chip on the electrical inspection device. Then, the physical location data of the false defects on the logical data result is compared. ς 1262^. wfl.doc/006 95.1.12 Correction of the sex test device. According to the "detection_positioning method" according to the embodiment of the present invention, the above-mentioned false defect is caused by short circuit or open circuit of the conductive structure. According to the positioning method of the wafer electrical detection according to the embodiment of the present invention The processing of w is, for example, the use of a focused ion beam (foGus _ ^, just. According to this judgment, the method of performing the tracing W miscellaneous detection remaining, the pole: the conductive structure is, for example, a metal interconnect, a bit line contact window, or a gate Method, the structure of the electrical defect detection of the structure of the component type. = Pair: two electricity; = the known physical position of the conductive circuit designed by the circuit is made up of a small one from a, this fast, and the mouth The auditor's disc is μμ曰μ^二乍至夕一一假缺. Then, using the electrical test, this, Luo Erqi (4) electrical test to get the logical data results. After the next, repair two or two false The physical position of the defect is compared. The "Electricity 1 pair of clothes. Then, using the modified electrical properties; the strength of the crystal (10) conductive structure can be checked. The electrical properties of the semiconductor component structure are checked and checked. The defect, / is treated by, for example, using a focused ion beam. According to the semiconductor detecting method of the embodiment of the present invention, the method for making at least one false defect from the s, the singularity, the electrical defect, the smear, and the sigma A physical position generates a short circuit or an open circuit. ¥Electrical detection:: The electrical defect of the semiconductor device structure, / / conductive structure of / h such as metal interconnect, #_, contact window, or gate Line, , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , In the position, the _! of the second electrical defect detection, the correction of the electrical test device, can avoid the shortcomings of the chip. In addition, too L buckle can not find the correct physical position of the row positioning of the cattle ^ in the electrical Before the defect (4), the advanced work = ^ first use the focused ion beam on the wafer to produce the logical data results and the known physical bits (9) to compare the missing according to the & fruit (four) μ ^ set, and then the film == == After the device is corrected, the general crystal trap test is set to r, Q In the position, this way can avoid the lack of _ _ _ _ _, and the name and the name of the detection time and manpower. The spoon is easy to understand the two men? And other purposes, features and advantages can be more It is apparent that the following is a description of the steps of the fabrication of the false defect. The defect is used as a reference for the detection of electrical defects. !^1, 100 first, in step 100, 导电 芩 芩 芩 芩 电路 电路 电路 电路 电路 电路 电路 电路 导电 导电 导电 导电 导电 导电 导电 导电 导电 导电 导电 导电 导电 导电 导电 导电 导电 导电 导电 导电 导电 导电 导电 导电 导电 导电 导电 导电 导电 导电 导电Conductive junction line contact window plug or reduction side ^ I focus ion beam hit in the conductive structure j such as 疋 use and then a certain physical position on the structure of the child 95.1.12 12625 endure twfl.d〇c/006 It is short-circuited or cut off to cause an open circuit.
圖2為依照本發明一第一實施例之晶片電性檢測的定 位方法之步驟流程圖。請參照圖2，首先，於步驟2〇〇中， 提供一晶片，此晶片上已形成有經電路設計的至少一導電 結構’其中此導電結構包括具有物理位置資料的至少一個 假缺陷。其中，假缺陷是由導電結構經處理而短路或斷路 所k成。在一實施例中，例如是使用聚焦離子束打在導電 結構上’將導電結構上的某一物理位置連接起來而產生短 路或切斷而產生斷路。另外，導電結構例如為金屬内連線、 位元線接觸窗、或閘極線等。 接著，於步驟202中，利用電性檢驗裝置對晶片進行 電性檢驗而得到邏輯數據結果。在一實施例中，電性 裝置例如是Mosaid測試機台。 览队 ^然後，於步驟204中，將此邏輯數據結果與晶片上之 假缺陷的物理位置進行比對。之後，於步驟中， 電性檢驗裝置的修正。 仃 圖3為依照本發明一第二實施例之動態隨機存 體結構的電性缺陷檢測步驟流程圖。請參照圖3，、，1 μ 於步驟300中，提供一晶片，此百， 的導電結構。 片上㈣―電路設計 接著，於步驟302 ’對此導電結構進行處理 結構上的某一物理位置製作至少—假缺陷。在 + ΐ導ΙΪ構可以是動態隨機存取記憶體的金屬内ΐ二的 弟一至屬層，且製作這種假缺陷的方式可於動態隨== 126^m twfl.doc/006 95.1.12 記憶體製作完成後，先將覆蓋於第 ::===内部介電 短路 存取記憶體的第二金屬層中，且作 疋動㈣機 金S的保_乾式物 ;上:二使:㈡ 可以是動態隨機存取記憶體的位元線二= 這種假缺陷的方式係於位元線結構製二=基而製作 離子束打在位元線接觸窗插塞或位元^=使用聚焦 路，再完成動態隨機存取記憶體之後續f 短路或斷 數據結果。d耻仃紐檢㈣得到邏輯 接下來，於步驟306中，將 的物理位置進行比對。然後，在步驟3耳〇8 f吉：與:缺陷 驗裝置。之後，於步驟310中，利用修、正電性檢 置再對晶片的導電結構進行檢驗，直^邏輯檢驗裝 的物理位置比對結果一致。 ^璉軏數據與假缺陷 上形成具有物理^ 電性缺陷檢測，是於晶片 損害。此外上的導電 在對曰曰片進行電性缺陷檢測前，先剎 10 1262^¾ wfl.doc/006 95.1.12 用水焦離子束於晶片上製作出已知物理位置的缺p 此晶片進行電性檢測，將所得到的電性數據結果‘ f將 =置Γ嶋行比對’然後根據比對結果對缺陷撿.二 進仃I正，進行定位後再對—般晶片進行檢:衣 陷的所在位置。此種方式可避免因缺陷檢驗 斤=缺 ^而在輯時產生誤差，糾料讀其不 且郎省了檢測時間與人力。 、 雖然本發明已以實施例揭露如上，然其並非用以限定 本發明1任何熟習此技藝者，在不脫離本發明之精神和範 =内^可作些§午之更動與潤飾，因此本發明之保護範圍 當視後附之申請專利範圍所界定者為準。 【圖式簡單說明】 圖1為假缺陷的製作步驟流程圖。 圖2為依照本發明一第一實施例之晶片電性檢測的定 位方法之步驟流程圖。 圖3為依照本發明一第二實施例之動態隨機存取記憶 體的缺陷檢測之步驟流程圖。 【主要元件符號說明】 100〜102、200〜206、300〜310 :步驟2 is a flow chart showing the steps of a positioning method for wafer electrical detection according to a first embodiment of the present invention. Referring to Figure 2, first, in step 2, a wafer is provided having at least one electrically conductive structure designed to be formed thereon, wherein the electrically conductive structure includes at least one dummy defect having physical location information. Among them, the false defect is formed by short-circuiting or breaking of the conductive structure. In one embodiment, for example, a focused ion beam is used to bond a physical location on the conductive structure to create a short or cut to create an open circuit. In addition, the conductive structure is, for example, a metal interconnect, a bit line contact window, or a gate line. Next, in step 202, the wafer is electrically verified by an electrical inspection device to obtain a logical data result. In one embodiment, the electrical device is, for example, a Mosaid test machine. The team ^ Then, in step 204, the logical data result is compared to the physical location of the false defect on the wafer. Thereafter, in the step, the correction of the electrical test device is performed. Figure 3 is a flow chart showing the steps of detecting electrical defects in a dynamic random access structure in accordance with a second embodiment of the present invention. Referring to FIG. 3, 1 μ in step 300, a wafer, a hundred, conductive structure is provided. On-chip (4) - Circuit Design Next, at step 302 ', the conductive structure is processed to make at least a false defect at a physical location on the structure. The + ΐ ΙΪ 可以 可以 可以 可以 可以 可以 可以 可以 可以 可以 可以 可以 可以 可以 可以 可以 可以 可以 可以 动态 动态 动态 动态 动态 动态 动态 动态 动态 动态 动态 动态 动态 动态 动态 动态 动态 动态 动态 动态 动态 动态 动态 动态 动态 动态 动态 动态 动态 动态 动态 动态After the memory is completed, it will be covered in the second: metal layer of the internal dielectric short-circuit access memory of the first::===, and it will be used as the protection of the (4) machine S. (2) Bit line 2 which can be dynamic random access memory = The method of this kind of false defect is based on the bit line structure 2 = base and the ion beam is made in the bit line contact window plug or bit ^= Focus the way, and then complete the subsequent f short circuit or broken data result of the dynamic random access memory. d Shame New Test (4) Get Logic Next, in step 306, the physical positions are compared. Then, in step 3, deaf 8 f: with: defect inspection device. Then, in step 310, the conductive structure of the wafer is inspected by the repair and positive charge test, and the physical position of the logical test package is consistent. ^ 琏軏 Data and false defects are formed on the surface with physical ^ electrical defects detected, which is damage to the wafer. In addition, before the electrical defect detection of the cymbal is performed, the first step is to make a known physical position on the wafer by using a water coke beam. Sex detection, the obtained electrical data results 'f will = set the line alignment' and then according to the comparison results for the defect 二. 二进仃I positive, after positioning, then the general wafer inspection: clothing Where it is. In this way, it is possible to avoid the error caused by the defect test, which is lack of ^, and the correction of the reading does not save the detection time and manpower. The present invention has been disclosed in the above embodiments, but it is not intended to limit the invention to those skilled in the art, and the invention may be modified and retouched without departing from the spirit and scope of the invention. The scope of protection is subject to the definition of the scope of the patent application. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a flow chart showing the steps of manufacturing a false defect. 2 is a flow chart showing the steps of a positioning method for wafer electrical detection according to a first embodiment of the present invention. 3 is a flow chart showing the steps of defect detection of a dynamic random access memory in accordance with a second embodiment of the present invention. [Main component symbol description] 100~102, 200~206, 300~310: Step