JP3913393B2 - Semiconductor defect analysis system and method - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor defect analysis system and method for analyzing defects on a semiconductor wafer. In particular, the present invention relates to a semiconductor defect analysis system and method for facilitating estimation of a defect occurrence factor based on defects on a semiconductor wafer.
[0002]
[Prior art]
In the semiconductor manufacturing process, in order to improve the product yield, defects on the surface of the semiconductor wafer are inspected in the middle of the process to analyze the state of the semiconductor manufacturing line. As a wafer defect analysis method, information such as the position and size of defects on the wafer surface is collected during the process, and by comparing the information with the design data, it can be determined whether or not the defects can cause defects in the product. There is something to judge. However, the design data of the semiconductor chip is enormous, and it is almost impossible to use the data online during the process.
[0003]
In recent years, a defect analysis method has been proposed in which the probability distribution of a product is determined by statistical probability processing of defect size distribution and semiconductor chip design data. Hereinafter, this method is referred to as a defect-induced yield analysis method. In this defect cause yield analysis method, a function indicating an area where a defect occurs is calculated from design data in advance using the defect size and the cause of the defect as parameters, and the defect occurrence probability for an actual defect is obtained using the function. . In this method, the amount of data to be held is very small, and it can be used online during the process. However, there are many unknown parts in the defect information, and the defect detection sensitivity is not sufficient. In addition, the definition of the defect size distribution is uncertain, and there is a problem in its measurement accuracy. Therefore, in order to make this method effective, it is necessary to evaluate the validity of the defect size distribution.
[0004]
[Problems to be solved by the invention]
An object of the present invention is to provide a semiconductor defect analysis system and method for solving such problems, ensuring the effectiveness of a defect-caused yield analysis method, and facilitating estimation of cause of failure based on defects on a wafer. And
[0005]
[Means for Solving the Problems]
In order to solve the above problems, the present invention provides a first means for obtaining the number of probable defects from a defect size distribution on a semiconductor wafer and design data of a semiconductor element formed on the semiconductor wafer, and an electrical failure of the semiconductor element. A second means for determining the estimated number of defects by classifying the patterns, and a third means for comparing the number of probable defects with the estimated number of defects and correcting the defect size distribution so that the number of probable defects matches the estimated number of defects. And a semiconductor defect analysis system characterized by comprising:
[0006]
According to the present invention, the reliability of the number of probability defects obtained by statistical probability processing can be improved. Therefore, it is possible to identify a failure factor based on a defect that occurs during the process. As a result, it is possible to effectively support countermeasures against defects during the process and to take measures to improve product yield at an early stage.
[0007]
DETAILED DESCRIPTION OF THE INVENTION
FIG. 1 is a diagram showing a configuration of a semiconductor defect analysis system according to an embodiment of the present invention. The semiconductor defect analysis system according to the embodiment of the present invention provides defect data of defects generated on a semiconductor wafer using optical means or the like (for example, appearance features such as defect coordinates, size, shape, and color). The defect inspection unit 1 for detecting the defect, the first database 2 for storing the defect data detected by the defect inspection unit 1, the defect is classified based on the defect data stored in the first database 2, and the classification result Are classified into a first database, a tester 4 that electrically measures a semiconductor device on a semiconductor wafer and detects defective bits, and a second database 5 that stores defective bit data detected by the tester 4 Then, an estimated defect is obtained by classifying the defective pattern (fail bit map) from the defective bit data stored in the second database 5, and the second data An estimated defect calculating section 6 to be stored in the over scan 5, has a butt portion 7 match probability number of defects and the estimated number of defects, and a probability defect calculator 8 for calculating the number of probability defects.
[0008]
[Means for Solving the Problems]
In order to solve the above problems, the present invention provides a first means for obtaining the number of probable defects from a defect size distribution on a semiconductor wafer and design data of a semiconductor element formed on the semiconductor wafer, and an electrical failure of the semiconductor element. Second means for determining the estimated number of defects by classifying patterns, and third means for comparing the number of probable defects with the number of estimated defects and correcting the defect size distribution so that the number of probable defects matches the estimated number of defects. And a semiconductor defect analysis system comprising at least means for monitoring a correction value of the defect size distribution .
[0009]
The butting part 7 has two roles. (1) The matching unit 7 obtains a defect size distribution for each type of defect from the defect data, and passes the defect size distribution to the probability defect calculation unit 8. (2) The matching unit 7 compares the total number of probability defects and the total number of estimated defects, and corrects the defect size distribution if there is a difference between the total results. The matching unit 7 includes display means for simultaneously displaying the result of counting the number of probable defects and the result of counting the estimated number of defects, and input means for inputting a correction value for the defect size distribution from the outside. Further, the matching unit 7 may automatically correct the defect size distribution.
[0010]
The probability defect calculation unit 8 obtains the number of probable defects that cause an electrical failure using a statistical probability method based on the defect size distribution given from the matching unit 7 and the design data of the semiconductor chip prepared in advance. Specifically, a function indicating the extent to which a defect cause defect such as a short circuit, an open circuit, or a leak is generated from the design data of the entire chip of the semiconductor device, and the size of the given defect using the function is created. The defect probability for the distribution is calculated. Then, the number of probable defects is obtained by determining a defective chip from this defect probability. Here, “the number of probable defects” refers to the number of defects that cause electrical failure with a certain probability.
[0011]
Next, the operation of the embodiment of the present invention will be described with reference to FIG. First, the defect inspection unit 1 detects defect data of defects generated on a semiconductor wafer using an optical means such as an optical microscope. Then, the defect inspection unit 1 stores the detected defect data in the first database 2. The defect data is sent to the defect classification unit 3 to classify the defects. For example, the position of the defect is determined by the defect coordinates, and the type of defect is determined by the appearance characteristics such as the circularity and color of the defect. The defect size is also determined by optical inspection. After the classification is completed, the defect classification unit 3 registers the defect classification result in the first database 2. FIG. 2 is a diagram showing an example of the defect classification result registered in the first database 2. Since the defect data detected by the defect inspection unit 1 is based on optical means, not all existing defects are detected.
[0012]
The estimated defect calculation unit 6 obtains the estimated defect by classifying the defective pattern from the defective bit data detected by the tester 4. Random defects during the semiconductor manufacturing process cause electrical defects in the product locally or entirely. This electrical failure can be confirmed by the final electrical measurement of the semiconductor device. In particular, in a memory product, a defective bit can be determined for each memory cell, and the defective pattern is caused by the structure of the memory. Therefore, if the defect patterns are classified, the defect generation process and the cause of the defect can be known. Note that not all of the defects obtained by the estimated defect calculation unit 6 are detected by the defect inspection unit 1. Therefore, the defect obtained by the estimated defect calculation unit 6 is referred to as “estimated defect” here. FIG. 3 is a diagram illustrating an example of the estimated defect obtained by the estimated defect calculation unit 6.
[0013]
The matching unit 7 obtains the defect size distribution based on the defect classification result shown in FIG. The defect size distribution is obtained for each type of defect, and the number of defects for each defect size distribution is displayed. FIG. 4 is a diagram illustrating an example of a defect size distribution. The probability defect calculation unit 8 obtains the number of probability defects that cause electrical failure using a statistical probability method based on the defect size distribution shown in FIG. 4 and the design data of the entire chip. In addition, the matching unit 7 adds up the estimated defects shown in FIG. 3 and obtains the estimated number of defects. Then, the matching unit 7 matches the number of probability defects and the estimated number of defects. FIG. 5 is a diagram in which the number of probable defects and the estimated number of defects are matched. As a result of the matching, when the number of probable defects and the estimated number of defects are greatly different, the number of probable defects is corrected so that the number of probable defects matches the estimated number of defects. Since the probability defect number is calculated based on the defect size distribution, the defect size distribution is corrected and the probability defect number is calculated again. The correction may be designated from the outside, or the matching unit 7 may automatically perform the correction.
[0014]
Further, the validity of the defect size distribution correction value can be evaluated by defining the correction coefficient r as r = the number of probable defects / the estimated number of defects and monitoring the correction coefficient r over a long period of time. If a reliable correction value is obtained, the defect size distribution is corrected using that value, and if the number of probable defects is obtained, highly reliable defect factor estimation can be performed. FIG. 6 is a diagram illustrating an example of a trend graph of the correction coefficient r.
[0015]
According to the embodiment of the present invention, it is possible to guarantee the effectiveness of the defect-induced yield analysis method. Therefore, this method can be used to identify a failure factor based on a defect generated during the process.
[0016]
【The invention's effect】
ADVANTAGE OF THE INVENTION According to this invention, it becomes possible to support the defect countermeasure in the middle of a process effectively, and to take the countermeasure of the product yield improvement at an early stage.
[Brief description of the drawings]
FIG. 1 is a diagram showing a configuration of a semiconductor defect analysis system according to an embodiment of the present invention.
FIG. 2 is a diagram illustrating an example of a defect classification result.
FIG. 3 is a diagram illustrating an example of an estimated defect.
FIG. 4 is a diagram illustrating an example of a defect size distribution;
FIG. 5 is a diagram in which the number of probable defects and the estimated number of defects are matched.
FIG. 6 is a diagram illustrating an example of a trend graph of a correction coefficient r.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Defect inspection part 2 First database 3 Defect classification part 4 Tester 5 Second database 6 Estimated defect calculation part 7 Matching part 8 Probability defect calculation part

Claims (4)

A first means for obtaining a probability defect number from a defect size distribution on a semiconductor wafer and design data of a semiconductor element formed on the semiconductor wafer;
A second means for obtaining an estimated number of defects by classifying an electrical failure pattern of the semiconductor element;
A third means for comparing the number of probable defects with the estimated number of defects and correcting the defect size distribution so that the number of probable defects matches the estimated number of defects ;
A semiconductor defect analysis system comprising at least means for monitoring a correction value of the defect size distribution .   2. The semiconductor defect analysis system according to claim 1, wherein the first means obtains the number of the probability defects by performing a statistical probability process on the defect size distribution and the design data.   2. The semiconductor defect analysis system according to claim 1, wherein the third means includes means for inputting a correction value of the defect size distribution from the outside. A first step of obtaining a probability defect number from a defect size distribution on a semiconductor wafer and design data of a semiconductor element formed on the semiconductor wafer;
A second step of obtaining an estimated number of defects by classifying an electrical failure pattern of the semiconductor element;
Comparing the probability defect number with the estimated defect number, and correcting the defect size distribution so that the probability defect number matches the estimated defect number ;
And a step of monitoring a correction value of the defect size distribution .

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