JP2002368056A - Method for providing yield conditions, method for determining production conditions, method for fabricating semiconductor device and recording medium - Google Patents

Abstract

PROBLEM TO BE SOLVED: To analyze the factor for enhancing the yield with high precision in a short term. SOLUTION: Data of wafer inspection and probe inspection is pigeonholed and abnormal values are deleted (steps S101-S103), probe inspection terms are predicted (step S105) from the results of data mining (step S104), and the yield is predicted (step S106) from the results of the steps S103 and S105. A decision is then made whether correlation is present between the predicted value of yield and an actually measured value (steps S107, S108) and optimal conditions are determined from the order of influence of the yield (step S109). Trial manufacturing is performed for recognition if the conditions satisfy a target spectfication, otherwise splitting is performed for each category according to an orthogonal table (step S201), a semiconductor wafer is produced by way of trial according to trial production conditions thus obtained and abnormal values are deleted from probe inspection data (steps S202-S204), and then the conditions are optimized by analyzing the causes (steps S205, S206).

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to an improvement in the manufacturing yield of a semiconductor device.
The present invention relates to a technique that is effective when applied to prediction of yield conditions.

[0002]

2. Description of the Related Art With the recent progress of miniaturization technology in semiconductor devices, the factor of deterioration in yield tends to increase rapidly.
A technology that provides conditions for improving the yield in a short period of time is important.

As a technique for obtaining a condition for improving the yield, for example, a technique for performing a simulation using a parameter provided by a yield improving parameter providing company is widely known.

According to the study by the present inventors, an example of a simulation technique using parameters is as follows.
TEG (Test E) is a test element group mounted on a semiconductor chip for evaluation of circuit characteristics and process characteristics.
In some cases, a simulation is performed on the basis of a trial production result of the element group to determine conditions for improving the yield.

A technique for determining the manufacturing conditions is disclosed in, for example, Japanese Patent Application Laid-Open No. 7-37883, which describes a method for determining the manufacturing conditions when manufacturing a semiconductor device.

[0006]

However, the present inventor has newly found that the simulation technique using the above-described parameters has the following problems.

That is, as described above, since the analysis is carried out by using both the TEG and the simulation, the condition for improving the obtained yield is the optimum condition under the detailed condition of the selected chip. However, it is not necessarily the condition that the yield is improved in the actual product.

[0008] Further, since the parameters are not organized by category, there is a problem that it is difficult to determine the parameters that cause the yield deterioration.

An object of the present invention is to provide a method of providing a yield condition, a method of determining a manufacturing condition, a method of manufacturing a semiconductor device, and a recording medium capable of performing a factor analysis for improving a yield in a short period of time and with high accuracy. Is to do.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0011]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

The present invention provides a computer system comprising:
It provides a yield condition of semiconductor device manufacturing,
(A) a step of arranging data of various inspection items in wafer inspection and probe inspection; (b) a step of deleting abnormal values of the arranged data; and (c) data mining of data in which abnormal values have been deleted. Performing, (d) estimating a probe inspection item from the wafer inspection item determined from the data mining result, and (e) estimating the yield from the estimated probe inspection item and the data mining result. ,
(F) Compare the predicted yield value and the actual measurement value to determine whether or not there is a correlation between them, and if there is a correlation, extract the degree of influence on the yield for the wafer inspection item. Optimizing the yield condition.

An outline of another invention of the present application will be briefly described in sections. That is, 1. Manufacturing method of semiconductor device: Various inspection items in wafer inspection and probe inspection are rearranged, abnormal values of the rearranged data are deleted, and data mining of the data in which the abnormal values are deleted is performed. Predict the probe inspection item from the wafer inspection item that has been predicted, predict the yield from the predicted probe inspection item and the result of data mining, compare the predicted value of the predicted yield with the measured value, and have a correlation between them It is determined whether or not there is a correlation, and if there is a correlation, the degree of influence on the yield for the wafer inspection item is extracted to determine an optimized yield condition. 2. A method of determining manufacturing conditions for manufacturing a semiconductor device including the following steps: (a) a step of shunting manufacturing conditions belonging to the same inspection item according to an orthogonal table in the Taguchi method, and prototyping a semiconductor wafer based on the obtained manufacturing conditions; (B) verifying the probe inspection data of the semiconductor wafer obtained thereby and deleting an abnormal value; and (c) determining the manufacturing conditions by performing factor analysis on the data from which the abnormal value has been deleted. 3. A recording medium storing a program to be executed by a computer system including the following steps: (a) a step of arranging data of various inspection items in wafer inspection and probe inspection; and (b) a step of deleting abnormal values of the arranged data. (C) performing data mining of the data from which abnormal values have been deleted; (d) estimating a probe inspection item from a wafer inspection item determined from the data mining result; Estimating yield from probe inspection items and data mining results;
(F) comparing the predicted yield value with the actual measurement value, determining whether or not there is a correlation between them, and extracting the degree of influence on the yield for the wafer inspection item when there is a correlation, A step of optimizing the yield condition.

[0014]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 is an explanatory view showing a procedure for providing a condition for improving the yield of semiconductor device manufacturing according to one embodiment of the present invention, and FIG. 2 is a diagram showing a procedure for manufacturing a semiconductor device according to one embodiment of the present invention. FIG. 3 is a block diagram of an electronic system for calculating a condition of a yield, and FIG. 3 is an explanatory diagram showing an example of various inspection item data arranged by calculating basic statistic values and process capabilities according to an embodiment of the present invention; 4 is an explanatory view showing another example of FIG. 3, FIG. 5 is an explanatory view showing a result obtained by analysis of variance according to one embodiment of the present invention, and FIG. 6 is a comparison of analysis of variance in FIG. Fig. 7
FIG. 8 is an explanatory diagram showing an absolute value of a correlation matrix between a probe inspection item and a wafer inspection item according to one embodiment of the present invention. FIG. 8 is a probe inspection using a stepwise method according to one embodiment of the present invention. FIG. 9 is an explanatory view showing an example in which an optimum wafer inspection item is mathematically extracted to predict the item.
FIG. 10 is an explanatory diagram when ranking is performed based on the fit of the probe test items according to the embodiment of the present invention and the probe test items effective for the yield, and FIG. 10 shows the results of data mining according to the embodiment of the present invention. FIG. 11 is an explanatory view showing an example of a comparison between a predicted value of an expected probe test item and an actually measured value. FIG. 11 is an explanatory view showing another example of FIG.
2 is an explanatory diagram showing predicted probe inspection data according to an embodiment of the present invention and a predicted value of a yield predicted from data mining results, and FIG. 13 is a yield according to an embodiment of the present invention. FIG. 14 is a diagram showing an example of a prediction function, FIG. 14 is an explanatory diagram showing how a correlation coefficient is applied between a predicted value and a measured value of a predicted yield according to an embodiment of the present invention, and FIG. Explanatory diagram showing an example of determination of the yield influence rank according to an embodiment of the present invention,
FIG. 16 is an explanatory diagram showing an example in which parameters belonging to the same category are assigned to an L18 orthogonal table according to an embodiment of the present invention. FIG. 17 is an explanatory diagram showing an example of the parameters assigned to FIG. FIG. 19 is an explanatory diagram showing an example of probe inspection data obtained from a prototype of 18 semiconductor wafers according to an embodiment of the present invention. FIG. 19 is an explanatory diagram showing an example of verification in the probe inspection data of FIG.
FIG. 21 is a correlation diagram between a margin defect and a yield when an abnormal value is deleted according to an embodiment of the present invention. FIG. 21 is a diagram showing a factor effect when an abnormal value is deleted according to the embodiment of the present invention. 22 is a factor analysis diagram of FIG. 21, FIG. 23 is an explanatory diagram showing a relationship between a yield improvement condition and a predicted yield according to an embodiment of the present invention, and FIG. 24 is a graph showing an abnormal value examined by the inventor. FIG. 25 is a diagram showing a factor and effect when not deleted, and FIG. 25 shows a MISFE which is a semiconductor device according to an embodiment of the present invention.
FIG. 26 is a process flow showing a method of manufacturing T, and FIG.
FIG. 27 is a view showing a wafer probe according to an embodiment of the present invention.

In this embodiment, the procedure of a method for providing a condition for improving the yield of semiconductor device manufacturing is shown in FIG.
As shown in FIG. 5, when roughly divided, a procedure (steps S101 to S111) using a multivariate analysis, which is a technique for analyzing data on which a plurality of items are simultaneously investigated,
A procedure (Steps S201 to S206) using an orthogonal table in the Taguchi method well known in quality engineering,
These are procedures that are internally processed by an electronic system (computer system) 1 such as a computer.

As shown in FIG. 2, the electronic system 1 includes an input unit 2, a central control unit 3, and an output unit 4. The input unit 2 is, for example, a keyboard capable of inputting various data, and a central control device 3 is connected to the input unit 2.

The output unit 4 includes a display, a printer, and the like, and displays data output from the input unit 2 and results calculated by the central control unit 3 and prints out the data.

The central control unit 3 includes a control unit 3a, a storage unit 3
b, a program storage unit (recording medium) 3c, and a statistical calculation unit 3d. The storage unit 3b, the program storage unit 3c, and the statistical calculation unit 3d are connected to the control unit 3a.

The control section 3a controls all controls in the central control device 3. The storage unit 3b stores a RAM (Rando)
m Access Memory), and stores data input from the input unit 2, data of a calculation result by the statistical calculation unit 3d, and the like.

The program storage section 3c stores a ROM (Rea)
d Only Memory) or a storage device such as a hard disk device, and stores a program that is internally processed by the electronic system 1. The statistical calculation unit 3d calculates an optimum yield improvement condition using various data stored in the storage unit 3b, based on the program stored in the program storage unit 3c.

Steps S101 to S111 in FIG.
In the processing of the wafer inspection data actually measured,
Analysis is performed after classifying effective parameters for each category (inspection item) with respect to the probe inspection data.

If the conditions determined by this analysis do not satisfy the target specifications, steps S201 to S2
The process of step 06 provides trial production conditions for optimizing under wider manufacturing conditions, and determines the optimal conditions again based on the trial production results.

Next, a technique for providing conditions for improving the yield of semiconductor device manufacturing will be described for each processing procedure shown in FIG.

First, when various inspection item data of the wafer inspection and the probe inspection have already been input (step S101), after verifying the data, abnormal values of data in these various inspection items are deleted. (Step S102).

Here, the wafer inspection and the probe inspection are for performing an electrical test of a semiconductor chip by applying a probe needle to a bonding pad formed on a semiconductor wafer. , Measurement location, measurement timing, and the like.

From the probe inspection data and the wafer inspection data, data that is clearly considered to be a measurement error is deleted, and data within the same semiconductor wafer is assumed to have a normal distribution. And delete it.

This inspection is performed using, for example, a wafer prober, and FIG. 27 shows an example of a wafer prober. As shown in FIG. 27A, a plurality of semiconductor chips are formed on a semiconductor wafer. As shown in FIG. 27B, a wafer prober evaluates the electrical evaluation of the semiconductor chips formed on the semiconductor wafer. When performing, the electrode of the semiconductor chip, (for example, external terminals such as bonding pads)
This is a device for connecting and moving a probe (probe), which is an electrode of a measuring instrument (tester), and operates under the control of a computer and a tester.

FIGS. 3 and 4 show an example in which data is arranged by the processing in step S103, and various kinds of data inspected by a certain probe inspection or wafer inspection are arranged.

In this example, basic statistical values, calculation of process capability, and the like are performed for each lot, each wafer, and each measurement position. Basic statistics are values that can be easily calculated from raw data such as the average, variance, and maximum of data. The process capability is a value indicating how much quality is achieved when the process is controlled, and specifically,
There is a process capability index Cp and a process capability index Cpk including a deviation from the center value.

After the deletion of the abnormal value of the data is completed, the data is organized (step S103). Then, after the data is arranged, data mining for improving the yield is performed (step S104). This data mining is a technique for finding valuable information from data, and includes, for example, four procedures of data mining 1-4.

In the first procedure, data mining 1, only parameters having variance are extracted by variance analysis, which is one of the above-described multivariate analyses, and initial screening of wafer inspection data is performed. Here, the parameter is a manufacturing condition.

FIG. 5 shows the results of the analysis of variance obtained by the analysis of variance, and FIG. 6 is a diagram comparing which items have what variance from the analysis of variance.

With this analysis of variance, it is possible to filter out parameters that have little variance and do not need to be considered.
In addition, in the process of step S104, in addition to the analysis of variance, a statistical method such as a test, a section estimation, or a multivariate analysis can be used.

In data mining 2, a correlation matrix between a probe inspection item and a wafer inspection item is calculated. FIG.
FIG. 7 is a diagram showing an absolute value of a correlation matrix between a probe inspection item and a wafer inspection item.

Here, a parameter having a large absolute value of the correlation coefficient is extracted. As a result, it is possible to extract the wafer inspection parameters necessary for predicting the probe inspection items.

The correlation coefficient is an index indicating the relationship between two variables, and is a value between -1 and 1. The closer to 1, the stronger the positive correlation, and the closer to -1, the negative correlation. Is strong, and the closer to 0, the less correlation.

In data mining 3, a wafer inspection item (standard partial regression coefficient) necessary for predicting a probe inspection item using the stepwise method for the parameters extracted in data mining 1 and 2 for each probe inspection Is extracted.

FIG. 8 shows that the optimum wafer inspection item for predicting the probe inspection item is mathematically extracted by using the stepwise method, which is one method of the multiple regression analysis in the multivariate analysis. FIG.

By extracting the wafer inspection items by the stepwise method, it is possible to extract parameters sufficient for improving the prediction accuracy.

Thereafter, the processing of data mining 4 is performed. FIG. 9 is a diagram in which the order in which the probe inspection items are applied and the probe inspection items that are effective for the yield are ranked.

In the data mining 4, the probe inspection items which affect the yield and which are expected to be well applied are extracted from FIG. As a result, it is possible to extract sufficient parameters for accurately predicting the yield.

The data mining 1 to 4 can greatly reduce the calculation time of the yield prediction.
Other methods applicable to data mining for improving yield include principal component analysis, discriminant analysis, and cluster analysis.

Then, a probe inspection item is predicted (step S105). FIG. 10 and FIG. 11 are diagrams illustrating a comparison between the predicted value of the probe inspection item predicted from the result of the data mining 3 and the actually measured value.

Since the wafer inspection items (coefficients) necessary for predicting the probe inspection items are determined from the result of the data mining 3, the expected line and the curve for the probe inspection are determined, and the fit of the expected line and the curve is determined. ,
Perform the test.

Here, multiple regression analysis is used, but from the structure and properties of data, logistic regression analysis, general least squares method, principal component regression analysis (Principal)
Component Regression), PL
S regression analysis (PartialLeast Square)
It is necessary to apply fitting by s Regression.

Next, yield prediction is performed (step S1).
06). FIG. 12 shows predicted probe test items and predicted values of yield predicted from the results of data mining 4.

Here, as shown in FIG. 12, a probe inspection item affecting the yield extracted from the result of data mining 4 (expected from a wafer inspection)
Is used to predict the yield.

FIG. 13 is a diagram showing an example of the yield prediction function. This is a regression equation obtained from the results of the probe inspection prediction and the yield prediction, and confirms whether or not the wafer inspection item matches the physical interpretation. If the prediction function matches the knowledge, the change in yield when the value of the wafer inspection item is changed is quantified. If they do not match,
Perform prediction function review. In some cases, an error is captured as an error bar.

Then, the predicted value of the yield predicted in the processing of step S106 is compared with the actually measured value (step S107), and it is determined whether or not there is a correlation between them (step S108). Perform (Step S109).

Whether the predicted yield and the measured value of the predicted yield are applied is determined, for example, from the coefficient of determination adjusted for the degree of freedom of the multiple regression analysis or the Akaike information criterion.

FIG. 14 is a scatter plot of the predicted yield and the actually measured value. If the correlation is strong, it can be determined that the data mining accuracy of the current yield improvement is good.

Further, when the correlation is weak, the combination of the variables extracted by the data mining is bad. Examine the statistics used and perform data mining.

FIG. 15 is a diagram in which the degree of influence on the yield for the selected wafer inspection item is extracted, and the yield influence rank is determined. According to this diagram, the yield improvement condition can be optimized efficiently.

Then, it is determined whether or not the yield improvement condition optimized by the processing of step S109 satisfies the target specification (step S110).
When the yield improvement condition satisfies the target specification, a confirmation prototype is performed based on the yield improvement condition (step S111).

If the yield improvement condition does not satisfy the target specification, a trial production condition for optimizing under wider production conditions is provided, and the optimum condition is determined again based on the trial production result.

If the target specification is not satisfied in the process of step S110, the flow is divided according to the orthogonal table for each category (step S201). FIG. 16 shows an example in which parameters belonging to the same category are assigned to the L18 orthogonal table in the Taguchi method. In FIG. 16, A to H are parameters, and 1 to 18 indicate the number of semiconductor wafers manufactured.

FIG. 17 is a diagram showing an example of parameters to be assigned. In FIG. 17, for example, CM
OS (Complementary Metal Ox)
The parameters that cause a margin defect in the ion implantation process, which is one of the process conditions of the ide semiconductor (device), are assigned.

As this parameter, for example, pM
ISFET (Metal Insulator Sem)
Icon Field Effect T
ransistor), n / p li of nMISFET
gty doped drain (n / p extend
n.), a halo, a dose for forming n ⁺ / p ⁺ source / drain, ion implantation energy, and the like.

By using this L18 orthogonal table,
Usually, the combination of all parameters is 2 × 3 ⁷ = 43
Although the number of patterns becomes 74, the conditions for prototyping can be obtained in 18 types of prototypes, and the number of trial productions can be greatly reduced.

Then, 1 obtained by the L18 orthogonal table
A semiconductor wafer is prototyped under eight different prototype conditions (step S202). That is, by the wafer process,
Semiconductor devices and integrated circuits are fabricated on a semiconductor wafer. For the wafer process, for example, The M
"ULSI TECHNOLOG" issued in 1996 by cGRAW HILL companies, INC.
Y ", Chapter 9, P472 to P495, or
US Seria filed in the United States in March 2000
1 No: 09 / 486,899. Here, these contents are inserted as a reference.

FIG. 25 shows a CMISFET (CMOS
2 shows the process flow of the device. FIG. 26 shows FIG.
2 shows a sectional process flow corresponding to FIG. That is, FIG.
6 (a) corresponds to the cross section after step (e) in FIG. 25 is completed, FIG. 26 (b) corresponds to step (f) in FIG. 25, and FIG. 26 (c) is the step in FIG. FIG. 26D corresponds to steps (h) and (i) of FIG.
It is principal part sectional drawing corresponding to FIG.

FIG. 18 shows a part of probe test data obtained from a trial production of 18 semiconductor wafers.

Then, after verifying the probe inspection data obtained by the trial production (step S203), the abnormal value is deleted (step S204).

FIG. 19 is an example of verification of probe inspection data obtained by the processing in step S203, and is a correlation diagram between yield and margin failure (+ random failure).

Here, since the above-described process conditions of the MOS device are assigned to the L18 orthogonal table, the yield should be uncorrelated with a marginal defect which is an operational defect margin of the MOS device.

The data includes a defect of unknown cause, a so-called random defect. Since this is statistical data of 0, it is added to the yield without considering it as a defect.

However, the correlation coefficient of the data is 0.44, which indicates that the data contains an abnormal value. Looking at the DC failure rate of data that has no correlation with the yield, the failure rate is high in each case.

This DC defect is a defect due to foreign matter.
The defect does not depend on the parameters assigned this time. As in this example, data that has fallen due to many failures in other categories has no correlation.

Therefore, since the yield of data having no correlation depends on a completely different cause from the assigned parameter, it is deleted as an abnormal value. After removing outliers,
Data analysis (factor analysis) is performed (step S205),
The conditions are optimized (step S206), and a confirmation prototype using a semiconductor wafer is performed under the optimized conditions (step S111).

FIG. 20 is a correlation diagram between a margin defect and a yield (+ random defect) when an abnormal value is deleted.
In FIG. 20, the correlation coefficient is 0.95, and data accuracy is guaranteed.

FIG. 21 is a diagram showing a factor effect when an abnormal value is deleted. In FIG. 21, the yield is higher as the parameter is plotted upward, and the yield is lower as the plot is lower. From FIG. 21, it can be seen that the parameters having a large degree of influence among the eight parameters.

FIG. 22 is a factor analysis diagram. From this figure, the yield, the other characteristic values, and the degree of influence of each category can be quantitatively understood.

FIG. 23 is a diagram showing the relationship between the optimum condition for improving the yield and the predicted yield. In FIG. 23, not only the predicted yield but also the DRAM (D
dynamic Random Access Memo
Since other characteristics such as the refresh characteristic of ry) can be predicted, it is possible to perform optimization in consideration of not only the yield but also other characteristics.

FIG. 24 shows a factor-effect diagram in the case where the abnormal value examined by the present inventors is not deleted. In this case, as shown in FIG. 24, it can be seen that the result is completely wrong in the analysis including the abnormal value.

Thus, according to the present embodiment, the following effects can be obtained.

(1) Statistical processing is performed after parameters are classified into categories for wafer inspection and probe inspection, so that yield improvement conditions can be easily provided in a short period of time, and the prediction accuracy of the yield improvement conditions can be provided. Can be significantly higher.

(2) Since only useful items are extracted for each category, unnecessary tuning work is eliminated, and the number of steps required for simulation and subsequent improvement and improvement work can be reduced.

(3) Providing conditions for improving the yield in a short period of time can reduce the development cost of the semiconductor device, reduce the number of defective semiconductor devices, and improve the saturation yield during mass production of products. it can.

Although the invention made by the inventor has been specifically described based on the embodiments of the present invention, the present invention is not limited to the above embodiments, and various modifications may be made without departing from the gist of the invention. Needless to say, it can be changed.

[0081]

Advantageous effects obtained by typical ones of the inventions disclosed by the present application will be briefly described as follows.
It is as follows.

(1) For the wafer inspection and the probe inspection, the manufacturing conditions are classified for each inspection item, and then the statistical processing is performed, so that the yield improvement condition can be easily provided in a short period of time, and The prediction accuracy of the yield improvement condition can be greatly increased.

(2) Since only useful items are extracted for each inspection item, unnecessary tuning work is eliminated, and the number of steps required for simulation and subsequent improvement and improvement work can be reduced.

(3) According to the above (1) and (2), the development cost of the semiconductor device can be reduced, and the manufacturing defect of the semiconductor device can be reduced.

[Brief description of the drawings]

FIG. 1 is an explanatory diagram showing a procedure for providing a condition for improving the yield of manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a block diagram of an electronic system for calculating a condition for improving the yield of semiconductor device manufacturing according to one embodiment of the present invention.

FIG. 3 is an explanatory diagram showing an example of various inspection item data sorted by calculation of a basic statistic, a process capability, and the like according to an embodiment of the present invention.

FIG. 4 is an explanatory diagram showing another example of FIG. 3;

FIG. 5 is an explanatory diagram showing results obtained by analysis of variance according to one embodiment of the present invention.

FIG. 6 is a diagram comparing the analysis of variance in FIG. 5;

FIG. 7 is an explanatory diagram showing absolute values of a correlation matrix between a probe inspection item and a wafer inspection item according to one embodiment of the present invention.

FIG. 8 is an explanatory diagram showing an example in which an optimum wafer inspection item for predicting a probe inspection item is mathematically extracted using a stepwise method according to an embodiment of the present invention.

FIG. 9 is an explanatory diagram when ranking is performed on the basis of the degree of fitting of the probe test items and the probe test items effective for the yield according to the embodiment of the present invention.

FIG. 10 is an explanatory diagram showing an example of a comparison between a predicted value of a probe inspection item and an actually measured value predicted from a result of data mining according to an embodiment of the present invention.

FIG. 11 is an explanatory diagram showing another example of FIG. 10;

FIG. 12 is an explanatory diagram showing predicted probe inspection data according to an embodiment of the present invention and a predicted value of a yield predicted from a result of data mining.

FIG. 13 is a diagram illustrating an example of a yield prediction function according to an embodiment of the present invention.

FIG. 14 is an explanatory diagram showing how a correlation coefficient is applied between a predicted yield value and an actual measurement value according to an embodiment of the present invention.

FIG. 15 is an explanatory diagram showing an example of determining a yield influence order according to an embodiment of the present invention.

FIG. 16 is an explanatory diagram showing an example in which parameters belonging to the same category are assigned to an L18 orthogonal table according to an embodiment of the present invention.

FIG. 17 is an explanatory diagram showing an example of parameters assigned to FIG. 16;

FIG. 18 is an explanatory diagram showing an example of probe inspection data obtained from a prototype of 18 semiconductor wafers according to an embodiment of the present invention.

FIG. 19 is an explanatory diagram showing a verification example in the probe test data of FIG. 18;

FIG. 20 is a correlation diagram between a margin defect and a yield when an abnormal value is deleted according to the embodiment of the present invention.

FIG. 21 is a diagram showing a factor effect when an abnormal value is deleted according to the embodiment of the present invention.

FIG. 22 is a factor analysis diagram of FIG. 21.

FIG. 23 is an explanatory diagram showing a relationship between a yield improvement condition and a predicted yield according to an embodiment of the present invention.

FIG. 24 is a diagram showing a factor and effect when an abnormal value examined by the inventor is not deleted.

FIG. 25 is a process flow showing a method for manufacturing a MISFET which is a semiconductor device according to an embodiment of the present invention.

26 is a cross-sectional process flow of the main part of FIG. 25.

FIG. 27 is a diagram showing a wafer probe according to an embodiment of the present invention.

[Description of Signs] 1 Electronic system (computer system) 2 Input unit 3 Central control unit 3a Control unit 3b Storage unit 3c Program storage unit (recording medium) 3d Statistical calculation unit 4 Output unit

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Takeshi Sendododa 5-2-1, Josuihoncho, Kodaira-shi, Tokyo Within the Semiconductor Group, Hitachi, Ltd. (72) Inventor Mikako Miyama, Kodaira-shi, Tokyo 5-20-1 Mizumotocho F-term in Hitachi Semiconductor Group 4M106 AA01 BA01 DJ20 DJ21 DJ38

Claims (20)

[Claims] 1. A method for providing a yield condition of semiconductor device manufacturing by a computer system, comprising: a step of arranging data of various inspection items in a wafer inspection and a probe inspection; and a step of deleting an abnormal value of the arranged data. Performing data mining of the data from which the abnormal value has been deleted; estimating a probe inspection item from a wafer inspection item determined from the data mining result; and a predicted probe inspection item and data mining. The step of predicting the yield from the result of, comparing the predicted value and the measured value of the predicted yield,
Judging whether or not there is a correlation between them, and if there is a correlation, extracting the degree of influence on the yield for the wafer inspection item and optimizing the yield condition. How to provide yield conditions. 2. A method for determining manufacturing conditions for manufacturing a semiconductor device by a computer system, wherein manufacturing conditions belonging to the same inspection item are diverted according to an orthogonal table in a Taguchi method, and a semiconductor wafer is prototyped based on the obtained trial manufacturing conditions. Verifying the probe inspection data of the semiconductor wafer obtained by the prototype, removing the abnormal value, and performing a factor analysis of the data from which the abnormal value has been deleted to determine the manufacturing conditions. A method for determining manufacturing conditions, comprising: 3. A method for providing a yield condition for manufacturing a semiconductor device by a computer system, comprising: a step of arranging data of various inspection items in a wafer inspection and a probe inspection; and a step of deleting an abnormal value of the arranged data. Performing data mining of the data from which the abnormal value has been deleted; estimating a probe inspection item from a wafer inspection item determined from the data mining result; and a predicted probe inspection item and data mining. The step of predicting the yield from the result of, comparing the predicted value and the measured value of the predicted yield,
Judging whether or not there is a correlation between them, and if there is a correlation, extracting the degree of influence on the yield with respect to the wafer inspection item, optimizing the yield condition, and the optimized yield condition. Is a step of determining whether or not the target specification is satisfied.If the yield condition does not satisfy the target specification, the manufacturing conditions belonging to the same inspection item are diverted according to an orthogonal table in the Taguchi method. According to the obtained prototype conditions, a step of trial production of a semiconductor wafer, a step of verifying probe inspection data of the semiconductor wafer obtained by the trial production, a step of deleting an abnormal value, and a factor analysis of the data in which the abnormal value is deleted And a step of optimizing the yield condition. 4. A method for providing a yield condition for manufacturing a semiconductor device by a computer system, comprising calculating basic statistical values and process capability of various inspection item data of wafer inspection and probe inspection, and calculating data on various inspection items. Arranging the data; arranging, in the arranged data, measurement errors and data that deviate from a normal distribution in the same semiconductor wafer as abnormal values; and performing data mining of the data from which the abnormal values have been deleted. And a step of predicting a probe inspection item from a necessary wafer inspection item extracted from the result of the data mining; the predicted probe inspection item; and a probe inspection item affecting a yield extracted in the data mining. And is likely to fit Comparing the step of predicting the prediction value of the yield from the lobe test items, and the measured and predicted values of the expected yield,
Judging whether or not there is a correlation between them, and if there is a correlation, extracting the degree of influence on the yield for the wafer inspection item and optimizing the yield condition; and A step of determining whether or not the condition satisfies a target specification; and, when the yield condition satisfies the target specification, confirming and manufacturing a semiconductor device, and the yield condition satisfies the target specification. If not satisfied, the manufacturing conditions belonging to the same inspection item are diverted according to the orthogonal table in the Taguchi method, and a prototype of the semiconductor wafer is produced according to the obtained trial production condition, and a probe of the semiconductor wafer obtained by the trial production. Verifying the inspection data, removing the yield of uncorrelated data as an abnormal value, and deleting the abnormal value; And a step of optimizing the conditions by analyzing the factors. 5. The method for providing a yield condition according to claim 1, wherein the step of performing the data mining has a variance by an analysis of variance that is one of multivariate analyses. A first step of extracting only parameters and initially selecting wafer inspection data; a second step of calculating a correlation matrix between a probe inspection item and a wafer inspection item; and the first and second steps for each probe inspection. A third step of extracting a wafer inspection item necessary for predicting a probe inspection item by using a stepwise method with respect to the parameters extracted in the step, and a probe inspection item which is applicable to the probe inspection item and yield. Probe inspection items that affect yield and are expected to fit well. It provides methods yield conditions, characterized by a fourth step of extracting the item. 6. A method for rearranging data of various inspection items in wafer inspection and probe inspection, deleting abnormal values of the rearranged data, performing data mining of the data from which the abnormal values have been deleted, and performing the data mining. Predict the probe inspection items from the wafer inspection items determined from the results, predict the yield from the predicted probe inspection items, and the results of data mining, and compare the predicted value of the predicted yield with the measured value Determining whether or not there is a correlation between them, and, if there is a correlation, extracting a degree of influence on a yield with respect to a wafer inspection item to determine an optimized yield condition. Manufacturing method of a semiconductor device. 7. A manufacturing method belonging to the same inspection item is diverted according to an orthogonal table in the Taguchi method, a semiconductor wafer is prototyped according to the obtained trial production condition, and probe inspection data of the semiconductor wafer obtained by the trial production is verified.
A method for manufacturing a semiconductor device, comprising the steps of: removing an abnormal value; and analyzing the probe test data from which the abnormal value has been deleted to determine an optimized yield condition. 8. A method for rearranging data on various inspection items in wafer inspection and probe inspection, deleting abnormal values of the rearranged data, performing data mining on the data from which the abnormal values have been deleted, and a result of the data mining. Predict the probe inspection items from the wafer inspection items determined from, the predicted probe inspection items, and predict the yield from the results of data mining, comparing the predicted value of the predicted yield and the measured value, It is determined whether or not there is a correlation between them. If there is a correlation, the degree of influence on the yield for the wafer inspection item is extracted to optimize the yield condition, and the optimized yield condition is , To determine whether the target specifications are satisfied,
If the yield conditions do not satisfy the target specifications, the manufacturing conditions belonging to the same inspection item are diverted according to the orthogonal table in the Taguchi method, a semiconductor wafer is prototyped under the obtained prototype conditions, and the semiconductor obtained by the prototype is obtained. A method of manufacturing a semiconductor device, comprising the steps of: verifying probe inspection data of a wafer to delete an abnormal value; analyzing the data from which the abnormal value has been deleted to determine an optimized yield condition. 9. A basic statistic and a process capability are calculated for various inspection item data of wafer inspection and probe inspection, data are arranged for various inspection items, and a measurement error and an identical semiconductor wafer are included in the arranged data. Data that deviates from the normal distribution is regarded as an abnormal value and is deleted, data mining is performed on the data from which the abnormal value is deleted, and a probe inspection item is predicted from necessary wafer inspection items extracted from the data mining result. , The predicted probe test items, and probe test items that affect the yield extracted in the data mining, and predict the predicted value of the yield from the probe test items that are expected to fit well, and Compare the predicted yield with the actual measurement to determine if there is a correlation between them. If there is a correlation, extract the degree of impact on yield for wafer inspection items,
Optimize the yield condition, determine whether the optimized yield condition satisfies the target specification, if the yield condition does not satisfy the target specification, the same inspection items The manufacturing conditions belonging to the Taguchi method are diverted according to the orthogonal table, the semiconductor wafer is prototyped according to the obtained prototype conditions, the probe inspection data of the semiconductor wafer obtained by the prototype is verified, and the yield of data having no correlation is obtained. A method of manufacturing a semiconductor device, comprising the steps of: determining an abnormal yield value and deleting the abnormal value; and analyzing the data from which the abnormal value is deleted to determine an optimum yield condition. 10. A step of arranging data of various inspection items in a wafer inspection and a probe inspection, a step of deleting an abnormal value of the arranged data, and a step of performing data mining of the data in which the abnormal value has been deleted. Estimating a probe inspection item from a wafer inspection item determined from the data mining result; estimating a yield from the predicted probe inspection item and the data mining result; and estimating the expected yield. Compare the value with the measured value,
Determining whether or not there is a correlation between them, and if there is a correlation, extracting the degree of influence on the yield with respect to the wafer inspection item and optimizing the yield condition. A recording medium on which is recorded. 11. A step of diverting manufacturing conditions belonging to the same inspection item in accordance with an orthogonal table in the Taguchi method, and prototyping a semiconductor wafer on the basis of the obtained prototyping conditions. Recording a program for causing a computer system to execute a step of verifying and deleting an abnormal value, and a step of performing a factor analysis of the data from which the abnormal value has been deleted and optimizing a yield condition. . 12. A step of arranging data of various inspection items in a wafer inspection and a probe inspection; a step of deleting an abnormal value of the arranged data; and a step of performing data mining of the data from which the abnormal value has been deleted. Estimating a probe inspection item from a wafer inspection item determined from the data mining result; estimating a yield from the predicted probe inspection item and the data mining result; and estimating the expected yield. Compare the value with the measured value,
Judging whether or not there is a correlation between them, and if there is a correlation, extracting the degree of influence on the yield for the wafer inspection item and optimizing the yield condition; and The step of determining whether or not the condition satisfies the target specification, and, if the yield condition does not satisfy the target specification, diverting the manufacturing conditions belonging to the same inspection item according to the orthogonal table in the Taguchi method. Calculating prototyping conditions; verifying probe inspection data of the semiconductor wafer obtained by prototyping the semiconductor device based on the prototyping conditions; removing abnormal values; analyzing the data from which the abnormal values have been deleted. Recording a program for causing a computer system to execute a step of optimizing conditions. . 13. A method for manufacturing a semiconductor device, comprising: a step of rearranging data of various inspection items in a wafer inspection and a probe inspection; a step of deleting an abnormal value of the rearranged data; Performing a data mining of the obtained data, estimating a probe inspection item from a wafer inspection item determined from the data mining result, and estimating a yield from the predicted probe inspection item and the data mining result. And, comparing the predicted value and the measured value of the expected yield,
Judging whether or not there is a correlation between them, and if there is a correlation, extracting the degree of influence on the yield for the wafer inspection item and optimizing the yield condition; and Manufacturing the semiconductor device using the condition. 14. A method of manufacturing a semiconductor device, comprising: diverting manufacturing conditions according to an orthogonal table in a Taguchi method; and prototype-producing a semiconductor wafer based on the obtained prototype conditions; Verifying data and deleting an abnormal value; performing a factor analysis of the data from which the abnormal value has been deleted to optimize manufacturing conditions; and manufacturing a semiconductor device using the determined manufacturing conditions. And a method for manufacturing a semiconductor device. 15. A method for manufacturing a semiconductor device, comprising: a step of rearranging data of various inspection items in a wafer inspection and a probe inspection; a step of deleting an abnormal value of the rearranged data; Performing a data mining of the obtained data, estimating a probe inspection item from a wafer inspection item determined from the data mining result, and estimating a yield from the predicted probe inspection item and the data mining result. And, comparing the predicted value and the measured value of the expected yield,
Judging whether or not there is a correlation between them, and if there is a correlation, extracting the degree of influence on the yield with respect to the wafer inspection item, optimizing the yield condition, and the optimized yield condition. Is a step of determining whether or not the target specification is satisfied.If the yield condition does not satisfy the target specification, the manufacturing conditions belonging to the same inspection item are diverted according to an orthogonal table in the Taguchi method. According to the obtained prototype conditions, a step of trial production of a semiconductor wafer, a step of verifying probe inspection data of the semiconductor wafer obtained by the trial production, a step of deleting an abnormal value, and a factor analysis of the data in which the abnormal value is deleted Determining a manufacturing condition; and manufacturing a semiconductor device using the optimized manufacturing condition. Manufacturing method of a semiconductor device. 16. A method for manufacturing a semiconductor device, comprising: calculating basic statistical values and process capabilities of various inspection item data of a wafer inspection and a probe inspection; and arranging data in various inspection items. In the data obtained, a step of measuring and removing data that deviates from a normal distribution in the same semiconductor wafer as an abnormal value, performing data mining of the data in which the abnormal value has been deleted, and from the result of the data mining. Estimating the probe inspection item from the extracted necessary wafer inspection item; and the predicted probe inspection item, and the probe inspection item that affects the yield extracted in the data mining, and the fit is expected. Forecast yield from probe inspection items A step, the predicted and measured values of the expected yield compared,
Judging whether or not there is a correlation between them, and if there is a correlation, extracting the degree of influence on the yield for the wafer inspection item and optimizing the yield condition; and A step of determining whether or not the condition satisfies a target specification; and, when the yield condition satisfies the target specification, confirming and manufacturing a semiconductor device, and the yield condition satisfies the target specification. If not satisfied, the manufacturing conditions belonging to the same inspection item are diverted according to the orthogonal table in the Taguchi method, and a prototype of the semiconductor wafer is produced according to the obtained trial production condition, and a probe of the semiconductor wafer obtained by the trial production. Verifying the inspection data, removing the yield of uncorrelated data as an abnormal value, and deleting the abnormal value; And a step of determining a manufacturing condition by analyzing a factor, and a step of manufacturing a semiconductor device using the optimized manufacturing condition. 17. The method according to claim 13, wherein the light emitting device comprises:
In the method of manufacturing a semiconductor device according to the above item, the step of performing the data mining is a step of extracting only parameters having variance by variance analysis which is one of multivariate analyses, and performing initial sorting of wafer inspection data. A second step of calculating a correlation matrix between a probe inspection item and a wafer inspection item; and a probe inspection using a stepwise method for parameters extracted in the first and second steps for each probe inspection. The third step is to extract the wafer inspection items necessary to predict the items, and the probe inspection items that affect the yield are ranked according to the degree of fitting of the probe inspection items and the probe inspection items effective for the yield. And a fourth step of extracting probe test items that are likely to be applicable. The method of manufacturing a semiconductor device according to. 18. The manufacturing conditions belonging to the method are divided according to an orthogonal table in the Taguchi method,
Prototyping a semiconductor wafer, verifying probe inspection data of the semiconductor wafer obtained by the prototyping, and deleting an abnormal value, and performing factor analysis on the data from which the abnormal value has been deleted to determine manufacturing conditions. A program for causing a computer system to execute the steps. 19. A method for providing a yield condition for manufacturing a semiconductor device by a computer system, comprising the steps of: shunting the manufacturing conditions according to an orthogonal table in a Taguchi method, and prototype-producing a semiconductor wafer based on the obtained prototype conditions; Verifying the data of the semiconductor wafer obtained by the above, and removing an abnormal value; and performing a factor analysis of the data from which the abnormal value has been removed to optimize the yield condition. How to provide the condition. 20. The manufacturing conditions are divided according to an orthogonal table, a semiconductor wafer is prototyped according to the obtained prototype conditions, the data of the semiconductor wafer obtained by the prototype is verified, abnormal values are deleted, and the abnormal values are deleted. A method for manufacturing a semiconductor device, comprising a step of determining a manufacturing condition by analyzing a factor of deleted data.