1258180 九、發明說明： 【發明所屬之技術領域】 本發明係關於-種雙載子電晶體及 是一種提昇電流驅動能力之雙裁+带 "'，特別 法。 4子^體及電晶體製造方 【先前技術】 請參考第-圖，為習.知NPN雙載子電晶 狀結構示意圖。MPN雙載子電晶體Q1可以=虎和條 因為其射極—集極（E一c)間白勺電流是由基極;汗愚使用， 間的偏壓電壓VBE來控制，當NPN雙載子電曰體ζ射極（E ) -射極（Β-Ε)是順向偏壓，且Vbe>〇 7v日^極，基極 子就能夠克服在射極（E)和基極（B)間的N斗接） 電位(barrier potential)而進入基極(β),再橫：：;章 的基極（Β)而抵達集極（C)。當ΝΡΝ雙載子電晶體Qf/# 偏壓電壓VBE=0V時，就沒有任何電子從射極（E)射出來# 因此不論在射極（E)和集極（c)之間加上何種偏壓電^， 射極（E)和集極（C)之間都不會產生電流。 迅土 大部份的人之所以使用雙載子電晶體，乃是因為它能 夠放大電子訊號，在正確的工作條件下，射極（E)和集極 (C)間的電流值I。應該等於6乘以進入基極（B)的^流 lb (即Ic=/3x lb; /5二Ic/Ib)，此處的卢是放大係數，通常 在30到100之間。一般吾人所定義之電流增益（current gain)係指輸出與輸入之電流比值，而雙載子電晶體之電 流驅動能力指標係為上面所述之放大係數/5。 請參考第二圖，為習知NPN雙載子電晶體的截面示意 5 1258180 、:NPN雙載子電晶體1 2 3從底層依序有-個彼淡p型雜質 白B型基底10，接著擴散有一很濃的n型深埋 复 疋—層摻有很淡的η型雜質的嶋晶層30，^:ί 30上擴散有-高濃度？型雜質的基 曰曰2 形成有_，子電之基極⑻，〇基極層40上 與-高濃度η型雜質的集極層5卜 有ΝΡΝ雙載子電晶俨】之隹炻πη士二才層51上形成 散有高濃度η型雜“ 一:層:二::層4°中擴 腳雙載子電晶體上^^。50 _5◦上形成有 料^考Λ二圖，習知卿雙載子電晶體擦雜製程中的 =，會導致基極層4〇的周邊表面載子濃度會大於： y勺辰度’如此會使得ΝΡΝ雙載子電晶體丨在正常工作、-f生較大的無效電流Li從基極⑻經臭 表面回流，E)，同時產生較小的驅動電流J；周邊 ，極電流ib為無效電流Ibi與驅動電流&的加總，舷 1 4 Ib]增加時基極電流1b也會跟著增加。而_ 又 電日日體1電流驅動能力的指標/3可以下面式子表 =:U =Ibl+ib2，從式子可知，基極電流丨~ 其電流驅域力的指”會越小，所以在雙載曰 體，政製私中’潘效電流Ibi對NpN雙載子電晶體的電 動能力有決定性的影響，使得NpN雙載子電晶體的電^ 動能力受限於無效電流Ibi。因此‘。 2 體產生的無效電流Ibl實在是目前電晶體產業; 3 重要課題。 4 【發明内容】 5 有鑑於此，本發明提供一種雙載子電晶體及其製造方 1258180 法，係於雙載子電晶體之基極層中並與射極層間的周邊表 面擴散有一低摻雜層，提高基極層到該射極層的周邊表面 順向偏壓，以有效降低從該基極層回流到該射極層的無效 電流，而達到電晶體之高電流增益特性。 本發明一種雙載子電晶體至少包括有一半導體基板； 在該半導體基板上形成有一深埋層；深埋層上有一磊晶 層，屋晶層上分別有一集極層與一基極層；該基極層上具 有一射極層；_低摻雜層，形成於該基極層與射極層間之 周k表面，係可以提南基極層到該射極層的周邊表面順向 偏壓，有效降低從該基極層回流到該射極層的無效電流， 而達到電晶體的高電流增益特性。 本發明一種雙載子電晶體的製造方法，其步驟為： 首先提供一半導體基板；接著於該半導體基板上形成有一 深埋層；然後成長一磊晶層於該半導體基板上；再形成一 基極層與一集極層於該磊晶層中；接下來形成一射極層於 該基極層中·，最後形成一低摻雜層於該基極層與該射^層 之周邊表面間。該低摻雜層形成於該基極層與射極層間2 周k表面，係可以提咼基極層到該射極層的周邊表面順向 偏壓，有效降低從該基極層回流到該射極層的益帝、、☆' 而達到電晶體的高電流增益特性。 一， 以上的概述與接下來的詳細說明皆為示範性質，是為 了進一步說明本發明的申請專利範圍。而有關本發明=其 他目的與優點，將在後續的說明與圖示加以闡述。 、 【實施方式】 、本發明雙載子電晶體及其製造方法，係可適用於Npn 雙載子電晶體與PNP雙載子電晶體及其製作方法。在實施 1258180 例中以NPN雙載子雷$ 彳於…、口口 為摻，麵形式不同二 晶發;^圭實施例之NPN雙載子電 個I浹p型雜質的半導體基斤: 型深埋# 20a，㈣日 傲iUa接者擴政有一很濃的η e . J :、、'、後疋一層摻有报淡的η型雜質的N型磊 :;::=型蟲晶層咖上擴散有-術^ 51:卜曰&契肖濃度0型雜質的集極層51a，隼極層 =上，有_雙載子電晶體u 4〇^ 心=雙;=質的 層甘 體&之射極（E)。一低摻雜 ’形成於錄極層伽與該射極層咖之周邊表面 白周…可以提高基極層術到該射極層50a 射極層低基層〇&回流到該 腿層5_周邊热效電流一，而達到高電流增益之特性。 度二:Ϊ「第ΐ二本發明NPN雙載子電晶體la利用低濃 =周、真二=區介於該基極層4〇a與該射極層50a 柃；二於：士 ：形成低濃度？型摻雜區，該低濃度P型 與該射極層⑽’以提高基極層· 都=極層50a間周邊表面橫向之順向偏屬 載子電晶體la在大電流下的電流增益。 之半雙载子電晶體ia中摻雜低濃度p型雜質 =+¥體到基極層術的周邊表面，以形成低推雜層仙， =?邊表面載子濃度減小，使得腦雙載 电曰曰-a在正㊉工作下，減少從基極⑻經由基極層 81258180 IX. Description of the Invention: [Technical Field of the Invention] The present invention relates to a double-carrier transistor and a double-cut + band <' special method for improving current drive capability. 4 sub-body and transistor manufacturing method [Prior Art] Please refer to the figure - figure for the known NPN bi-carrier electro-crystal structure. MPN bipolar transistor Q1 can be = tiger and strip because the current between the emitter and collector (E-c) is controlled by the base; the use of the bias voltage VBE between the sweat, when NPN dual load The sub-electrode ζ emitter (E)-emitter (Β-Ε) is forward biased, and Vbe>〇7v day ^ pole, the base can overcome the emitter (E) and base (B) The N-port is connected to the base (β), and then the base (Β) of the chapter reaches the collector (C). When the bipolar transistor Qf/# bias voltage VBE=0V, no electrons are emitted from the emitter (E). Therefore, no matter what is added between the emitter (E) and the collector (c) No bias current, no current is generated between the emitter (E) and the collector (C). Xuntu The reason why most people use a bipolar transistor is because it can amplify the electronic signal, under the correct working conditions, the current value I between the emitter (E) and the collector (C). It should be equal to 6 times the flow lb into the base (B) (ie Ic = /3x lb; /5 II Ic / Ib), where Lu is the amplification factor, usually between 30 and 100. Generally, the current gain defined by the current is the ratio of the output to the input current, and the current drive capability of the bipolar transistor is the amplification factor /5 as described above. Please refer to the second figure, which is a cross-section of a conventional NPN bipolar transistor. 5 1258180, NPN bipolar transistor 1 2 3 has a white p-type impurity white B-type substrate 10 from the bottom layer, followed by Diffusion has a very thick n-type deep buried enthalpy-layer with a very light n-type impurity in the twin layer 30, ^: ί 30 on the diffusion - high concentration? The base 曰曰2 of the type impurity is formed with _, the base of the sub-electrode (8), the 集 base layer 40 and the collector layer 5 of the high-concentration η-type impurity have ΝΡΝ 载 载 电 电 η On the layer of the second layer 51, a high concentration of η-type impurity is formed. "One: layer: two:: layer 4° in the expanded double-carrier transistor ^^. 50 _5◦ formed on the material ^ test two map, Xi Zhiqing The = in the double-carrier transistor erasing process will cause the concentration of the carrier on the peripheral surface of the base layer 4〇 to be greater than: y spoon degree 'this will cause the ΝΡΝ-two-carrier transistor to work normally, -f The larger ineffective current Li flows back from the base (8) through the odor surface, E), while generating a smaller drive current J; the peripheral, the pole current ib is the sum of the ineffective current Ibi and the drive current & the side 1 4 Ib] When the time base current 1b is increased, the value of the base current 1b will also increase. The index of the current drive capability of the electric current body /3 can be expressed by the following formula =: U = Ibl + ib2, from the equation, the base current 丨 ~ The electric drive's force index will be smaller, so in the double-loaded carcass, the political system privately, the Pan-effect current Ibi has a decisive influence on the electric power of the NpN bipolar transistor. Such NpN bipolar transistor ^ movable electrical capacity is limited by the reactive current Ibi. therefore'. The ineffective current Ibl produced by the body is indeed the current transistor industry; 3 important issues. 4 SUMMARY OF THE INVENTION In view of the above, the present invention provides a bipolar transistor and a method for fabricating the same according to the method 1258180, which is in the base layer of a bipolar transistor and has a low doping diffusion with the peripheral surface between the emitter layers. The impurity layer increases the forward bias of the base layer to the peripheral surface of the emitter layer to effectively reduce the ineffective current flowing back from the base layer to the emitter layer to achieve high current gain characteristics of the transistor. A bipolar transistor of the present invention comprises at least one semiconductor substrate; a deep buried layer is formed on the semiconductor substrate; an epitaxial layer is disposed on the deep buried layer, and a collector layer and a base layer are respectively disposed on the roof layer; The base layer has an emitter layer; a low-doped layer formed on the surface k between the base layer and the emitter layer, which can be forward biased from the south base layer to the peripheral surface of the emitter layer The effective current flowing back from the base layer to the emitter layer is effectively reduced to achieve high current gain characteristics of the transistor. The invention provides a method for manufacturing a bipolar transistor, the steps of which are: firstly providing a semiconductor substrate; then forming a deep buried layer on the semiconductor substrate; then growing an epitaxial layer on the semiconductor substrate; forming a base a pole layer and a collector layer are formed in the epitaxial layer; an emitter layer is formed in the base layer, and finally a low doped layer is formed between the base layer and the peripheral surface of the emitter layer . The low doped layer is formed on the surface of the base layer and the emitter layer for 2 weeks, and the substrate layer can be forward biased to the peripheral surface of the emitter layer, thereby effectively reducing the return from the base layer to the The emitter layer's Yidi, ☆' achieves the high current gain characteristics of the transistor. The above summary and the following detailed description are exemplary in order to further illustrate the scope of the claims. With regard to the present invention, other objects and advantages will be explained in the following description and drawings. [Embodiment] The bipolar transistor of the present invention and a method for fabricating the same are applicable to an Npn bipolar transistor and a PNP bipolar transistor and a method of fabricating the same. In the implementation of 1258180 cases, NPN double-loaded sub-thunders are used in ..., the mouth is doped, and the surface forms are different from the two crystals; the NPN bi-carriers of the example of the invention are semiconductor I-p-type impurities: Deep buried # 20a, (4) Japanese proud iUa receiver expansion has a very strong η e. J:,, ', after a layer of N-type Lei with a weak η-type impurity:;::=-type insect layer Spread on the coffee - surgery ^ 51: Divin & Dich concentration 0 type impurity collector layer 51a, the bottom layer = upper, there is _ double carrier transistor u 4〇 ^ heart = double; = quality layer The body (E) of the body & A low doping is formed on the peripheral surface of the emitter layer and the peripheral surface of the emitter layer. The base layer can be raised to the emitter layer 50a. The emitter layer is lower than the base layer and is returned to the leg layer 5_ The peripheral thermal efficiency is one, and the high current gain is achieved. Degree 2: Ϊ "The second invention of the invention NPN bipolar transistor la uses low concentration = week, true two = zone between the base layer 4 〇 a and the emitter layer 50a 柃; two: 士: formation a low-concentration type doping region, the low-concentration P-type and the emitter layer (10)' are laterally biased to the carrier substrate la at a high current in order to increase the lateral surface between the base layer and the polar layer 50a. Current gain. The half-bias sub-electrode ia is doped with a low concentration of p-type impurity = +¥ body to the peripheral surface of the base layer to form a low-weighing layer, and the concentration of the surface carrier is reduced. The brain double-loaded eDonkey-a is reduced from the base (8) via the base layer under positive tenth operation.
1258180 、a的周邊表㈣流到射極（E)的周邊無 進而降低基極電流Ib。而NPN雙載子電曰二bl 力的指標/3可以下面式子表示…丨:曰丨體驅動) 基極電流W小其電流驅動能力的指標歸 = 大子可知 衫考第H半導縣板叫係由低濃 ίΐ^Γΐ成，娜細痛高濃度』綠 = Ί 層咖係由低濃度η型摻雜之- 成.層4°a係由高濃度p型摻雜: 2 =組成’魏摻雜層41a係由低濃度p型摻雜 &接下來說明本發明雙載子電晶體之製造方法 = 圖示’為本發明較佳實施例之雙載子電晶 有祀：m剖面示意圖。參考第四，首先是將摻 利用：、、!循^的半導體基板1〇8放在濕氧化環境中，並 回咖循裱來氧化，再將深埋層20a罩幕於氧化層中 口，經由此窗口擴散一很濃的η型深埋層20a。請泉 :第：B圖，接下來在整個晶圓上長一層摻有很淡n』雜 貝的蟲晶層30a，再製作基極區擴散罩幕42a，p型雜質細 由罩幕42a上的窗口在蟲晶層施上擴散出一基極層 a，該基極層4〇a並不接觸到深埋層2〇a。請參考第四〔 圖，再來製作射極與集極罩幕52a，n型雜質經由罩 上的窗口擴散兩個濃度很高，但深度很淺的η龍質區， 在基極層40a内的是射極層5〇a，在基極層4〇a外 極層5la。 疋木 請參考第四D圖，再製作低摻雜層罩幕43&，11型雜質 9 1258180 經由罩幕43a上的窗口擴散後與基極層4〇a相互抵減後形 成的兩個濃度淡且深度淺的p型低摻雜層41a ◦形成低換 雜層41a之後，完成本發明之雙載子電晶體的其他步驟為 習知公用技術，因此不再贅述。請參考第四£圖，為本發 明製造完成之雙載子電晶體剖面示意圖。 請復參考第四E圖，低摻雜層41a使得基極層4〇a的 周邊表面載子濃度減小，使得NPN雙載子電晶體la在正常 工作下，可以減少從基極層4〇a的周邊表面回流到射極層 50a、的周邊無效電流ibl產生，進而降低基極電流^。而腳 雙載子電晶體la電流驅動能力的指標万可以下面式子表 =^Ie/ib，從式子可知，基極電流h越小其電流驅動 月匕力的指標會越大。 如此，本發明一種雙載子電晶體及其製造方法，係可 於胸雙載子電晶體之基極層4〇a與射極層5如周邊表面 間擴散有低摻雜層41a，以有效降低從該基極層術回流 到該射極層5Ga的無效電流，提高基極層術到該射極層1258180, the peripheral table (a) of a flows to the periphery of the emitter (E) without further reducing the base current Ib. The NPN double-carrier electric 曰 two bl force index / 3 can be expressed by the following formula... 丨: 曰丨 body drive) base current W small, its current drive capability index = Dazi knows the shirt test H semi-guide county The plate is called low-concentration , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , 'Wei-doped layer 41a is made of a low-concentration p-type doping& Next, a method of manufacturing the bi-carrier transistor of the present invention = Illustrated' is a bi-carrier electrocrystal according to a preferred embodiment of the present invention: m Schematic diagram of the section. Referring to the fourth, firstly, the semiconductor substrate 1〇8 which is doped with:,, and the like is placed in a wet oxidizing environment, and is oxidized by the etchback, and then the deep buried layer 20a is masked in the middle of the oxide layer. A very dense n-type deep buried layer 20a is diffused through this window. Please: Spring: No. B, next on the entire wafer, a layer of wormhole layer 30a mixed with very fine n-shells is formed, and then a base diffusion mask 42a is formed. The p-type impurity is finely covered by the mask 42a. The window is diffused to the base layer a on the insect layer, and the base layer 4〇a does not contact the deep buried layer 2〇a. Please refer to the fourth [Fig., and then make the emitter and collector mask 52a. The n-type impurity diffuses through the window on the cover two η-long areas with high concentration but shallow depth, in the base layer 40a. The emitter layer 5〇a is in the outer layer 5la of the base layer 4〇a. Please refer to the fourth D diagram for the eucalyptus, and then make the low-doped layer mask 43&, the 11-type impurity 9 1258180 is diffused from the window on the mask 43a and then decomposed from the base layer 4〇a to form two concentrations. After the pale and shallow shallow p-type doped layer 41a is formed into the low-interstitial layer 41a, the other steps of completing the bi-carrier transistor of the present invention are conventional techniques, and therefore will not be described again. Please refer to the fourth figure for a cross-sectional view of the dual-carrier transistor fabricated in accordance with the present invention. Referring to the fourth E diagram, the low doped layer 41a reduces the carrier concentration of the peripheral surface of the base layer 4A, so that the NPN bipolar transistor la can be reduced from the base layer under normal operation. The peripheral surface of a reflows to the periphery of the emitter layer 50a, and the ineffective current ib1 is generated, thereby lowering the base current. The index of the current driving capability of the double-carrier transistor can be as follows: ^Ie/ib. From the equation, the smaller the base current h, the larger the current-driven monthly force index will be. Thus, a bipolar transistor of the present invention and a method of fabricating the same can be used to diffuse a low doped layer 41a between a base layer 4a of a thoracic bipolar transistor and an emitter layer 5, such as a peripheral surface, to effectively Reducing the ineffective current flowing back from the base layer to the emitter layer 5Ga, increasing the base layer to the emitter layer
5 ^i，J NPN 二=t。严°NPN雙载子電晶體因為擴散的特性， 表面載子濃度大於底層濃度，以至於讓 手雷產生較大的無效錢，而騎雙載 子電曰曰流驅動能力。因此，本發明可以有效改益習 ίΓΙίϊ子電晶體因為擴散的特性所造成電流驅動能力 惟 心利他7 為本發㈣佳之―料體實施例之 :=夂ri惟本發明之特徵並不侷限於此，並非用 限制本u，本發明之所有範圍應以下述之申請專利範 10 1258180 圍為準，凡合於本發明申請專利範圍之精神與其類似變化 之實施例，皆應包含於本發明之範疇中，任何熟悉該項技 藝者在本發明之領域内，可輕易思及之變化或修飾皆可涵 蓋在以下本案之專利範圍。 【圖式簡早說明】 第一圖為習知NPN雙載子電晶體的符號和條狀結構示意 圖； 第二圖為習知NPN雙載子電晶體的截面示意圖； 第三圖為本發明較佳實施例之NPN雙載子電晶體的截面示 意圖；及 第四A到第四E為本發明較佳實施例之雙載子電晶體之部 份製程的剖面示意圖。 【主要元件符號說明】 習知： NPN雙載子電晶體1 P型基底10 深埋層20 磊晶層30 基極層40 射極層50 集極層51 本發明： NPN雙載子電晶體la 半導體基板l〇a 1258180 深埋層20a 蠢晶層30a 基極層40a 低摻雜層41a 射極層50a 集極層51a5 ^i, J NPN 2 = t. Due to the diffusion characteristics of the strict-NPN bipolar transistor, the surface carrier concentration is greater than the underlying concentration, so that the grenade generates a large amount of invalid money and rides the double-carrier electric turbulence driving capability. Therefore, the present invention can effectively improve the current driving ability of the sub-transistor crystal due to the characteristics of diffusion, and it is advantageous for the user to be the fourth embodiment of the present invention. The scope of the present invention is not limited by the scope of the invention, and the scope of the invention is to be construed as being limited to the scope of the invention. Any variation or modification that can be easily conceived by those skilled in the art within the scope of the present invention can be covered by the following patents. BRIEF DESCRIPTION OF THE DRAWINGS The first figure is a schematic diagram of the symbol and strip structure of a conventional NPN bipolar transistor; the second figure is a schematic cross-sectional view of a conventional NPN bipolar transistor; A schematic cross-sectional view of a preferred embodiment of the NPN bipolar transistor; and fourth to fourth E are schematic cross-sectional views of a portion of the process of the bipolar transistor of the preferred embodiment of the present invention. [Main component symbol description] Conventional: NPN bipolar transistor 1 P type substrate 10 deep buried layer 20 epitaxial layer 30 base layer 40 emitter layer 50 collector layer 51 The present invention: NPN bipolar transistor la Semiconductor substrate l〇a 1258180 deep buried layer 20a stray layer 30a base layer 40a low doped layer 41a emitter layer 50a collector layer 51a