TWI253131B - Thermally enhanced chip package with high performance - Google Patents

Thermally enhanced chip package with high performance Download PDF

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Publication number
TWI253131B
TWI253131B TW094109881A TW94109881A TWI253131B TW I253131 B TWI253131 B TW I253131B TW 094109881 A TW094109881 A TW 094109881A TW 94109881 A TW94109881 A TW 94109881A TW I253131 B TWI253131 B TW I253131B
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Taiwan
Prior art keywords
wafer
substrate
heat sink
package structure
region
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TW094109881A
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Chinese (zh)
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TW200634943A (en
Inventor
Hung-Hsiang Cheng
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Advanced Semiconductor Eng
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Priority to TW094109881A priority Critical patent/TWI253131B/en
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Publication of TWI253131B publication Critical patent/TWI253131B/en
Publication of TW200634943A publication Critical patent/TW200634943A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16195—Flat cap [not enclosing an internal cavity]

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  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

A thermally enhanced chip package with high performance is provided, which includes a substrate, a chip and at least a surface mount device (SMD) disposed on the substrate, a heat sink located above the substrate, and a stiffener between the substrate and the heat sink. The stiffener is patterned and protrudes from a lower surface of the heat sink. In such a manner, the stiffener can be designed with a void for the SMD in position, such as at a corner or an edge of the substrate, and the SMD can be located on the corner or the edge of the substrate without increasing dimension of the substrate. Accordingly, the electrical function and the protection of the chip package are improved. Also the substrate is prevented from warpage.

Description

1253131 五、發明說明a) 【發明所屬之技術領域】 本發明係有關於一種晶片封裝構造，特別係有關於一 種可容置表面黏著元件（Surface Mount Device，SMD)之 高效能散熱型晶片封裝構造。 【先前技術】 積體電路晶片已廣泛運用在曰常生活中，可以作複雜 的運算、準確的驅動或高容量的記憶儲存，為了增加晶片 之使用哥命’需要對晶片作適當的封裝與散熱處理。 目刖之政熱型晶片封裝構造係將一晶片覆晶接合 (flip chip mounting)至一基板，該覆晶晶片之一背面係 貼e又有一散熱片（h e a t s i n k ) ’以利散熱。如第1圖所示， 一種散熱型晶片封裝構造1係主要包含有一基板丨〇、一覆 晶晶片2 0、一加強環3 〇以及一散熱片4 〇。該覆晶晶片2 〇係 具有一主動面21及一背面22，該覆晶晶片20係以複數個凸 塊2 3接合至該基板1 〇之一上表面11，在該覆晶晶片2 〇之該 主動面2 1與該基板1 〇之該上表面11之間係可形成一底部填 充材24(underfilling material)，以密封該些凸塊23。 此外，該加強環30 (stiffener ring)係設置於該基板1〇之 β亥上表面11，以防止該基板1 〇勉曲變形。該散熱片4 〇係黏 著於該加強環30且以一熱導界面物質5〇 (thermal interface material)熱耦合至該覆晶晶片20之該背面22 為。在該基板1 〇之一下表面1 2係可形成複數個銲球（圖未 繪出）。請參閱第2圖，該覆晶晶片20約略設置於該基板1〇 之該上表面1 1之中央位置；而該加強環4 〇約略設置於該基1253131 V. INSTRUCTION DESCRIPTION a) Technical Field of the Invention The present invention relates to a chip package structure, and more particularly to a high-efficiency heat-dissipation chip package structure capable of accommodating a surface mount device (SMD) . [Prior Art] Integrated circuit chips have been widely used in ordinary life, and can be used for complex calculations, accurate driving or high-capacity memory storage. In order to increase the use of wafers, it is necessary to properly package and dissipate the wafers. deal with. The wafer-heating structure of the wafer is formed by flip chip mounting to a substrate, and one of the backside of the flip chip has a heat sink (h e a t s i n k ) to facilitate heat dissipation. As shown in Fig. 1, a heat dissipating chip package structure 1 mainly comprises a substrate 丨〇, a flip chip 20, a reinforcing ring 3 〇, and a heat sink 4 〇. The flip chip 2 has an active surface 21 and a back surface 22, and the flip chip 20 is bonded to an upper surface 11 of the substrate 1 by a plurality of bumps 2 3, and the flip chip 2 is An underfilling material is formed between the active surface 21 and the upper surface 11 of the substrate 1 to seal the bumps 23. In addition, the stiffener ring 30 is disposed on the upper surface 11 of the substrate 1 to prevent the substrate 1 from being distorted. The heat sink 4 is adhered to the reinforcing ring 30 and thermally coupled to the back surface 22 of the flip chip 20 by a thermal interface material. A plurality of solder balls (not shown) may be formed on one of the lower surfaces of the substrate 1 . Referring to FIG. 2, the flip chip 20 is disposed approximately at a central position of the upper surface 1 1 of the substrate 1 ;; and the reinforcing ring 4 〇 is disposed approximately at the base

第6頁 .1253131 五、發明說明（2) f 2上表面1 1之周邊位置。習知在該覆晶晶片20與該 夕，+之間會留有一間隙31，但由於該基板1 0在該間隙 品知、係為線路密集區，因此，無法設置包含電容、電 電，等功能之表面黏著元件（Surface Mount Device， 二If散熱型晶片封裝構造1係無法整合表面黏著元 =厂土，1 〇，僅能將表面黏著元件設置在例如主機板或 =板巧部印刷電路板，電性連接路徑輕長，或者未連 η 1黏ϊ Γ件導致缺乏晶片保護措施或功能擴充性。 【發明内容】 本發明之主要目的係在於提供一種高效 =構造’：基板之一上表面係定義有一晶片接 τ二Τ於f上表面角隅之表面黏著區，該表面黏著區係 可供至少一表面黏著元件（Surface Mount De 之角隅，至少—加強件（stiffener)係圖案> 心又二熱片：一下表面’該加強件係可為十字形或 疋形專1¾何圖形設計，以容納該表面黏著元件，達到將 表面黏著元件整合至高效能散熱型曰曰曰4封裝構造内之功 效。 本發月之人目的係在於提供一種高效能散熱型晶片 封裝構造之散熱機構，其中至少一圖案化之加強件係突嗖 :一ΐ”;：下表面，以使該散熱片之該下表面上形成 有一第一谷：八以及一第二容置穴，較佳地，該加強件係 一體形成於該散熱片，該第一容置穴係可容納設置於一美 板上之一晶片，該第二容置穴係可容納設置於一基板上ςPage 6 .1253131 V. Description of the Invention (2) The peripheral position of the upper surface 1 1 of f 2 . It is known that a gap 31 is left between the flip chip 20 and the eve, +, but since the substrate 10 is known as a line-dense area in the gap, it is impossible to provide functions including capacitance, electric power, and the like. The surface mount device (Surface Mount Device, 2 If the heat sink type chip package structure 1 can not integrate the surface mount element = factory soil, 1 〇, can only set the surface adhesive component on the printed circuit board such as the motherboard or the board. The electrical connection path is light or long, or the η 1 adhesive element is not used to cause lack of wafer protection measures or functional expandability. SUMMARY OF THE INVENTION The main object of the present invention is to provide an efficient = construction ': one of the upper surface systems of the substrate Defining a surface adhesion region of the wafer to the upper surface corner of the f, the surface adhesion region is available for at least one surface adhesion component (Surface Mount De corner, at least - stiffener pattern) Two further hot films: the lower surface 'the reinforcing member can be a cross-shaped or a scorpion-shaped graphic design to accommodate the surface adhesive component, so as to integrate the surface adhesive component into the high-efficiency energy dispersion The effect of the type 曰曰曰4 package structure. The purpose of this month is to provide a heat dissipation mechanism for a high-efficiency heat-dissipating chip package structure in which at least one patterned reinforcement member is abruptly: The surface of the heat sink is formed with a first valley: eight and a second receiving hole. Preferably, the reinforcing member is integrally formed on the heat sink, and the first receiving hole can be Storing a chip disposed on a US board, the second receiving hole can be disposed on a substrate

第7頁 1253131 -—_ 、發明說明（3) 至少一表面黏著元件。 本發明之再一目的係在於提供一種高效能散熱型晶片 =裝構造，一基板之一上表面係定義有一晶片接合區、一 面f著區以及一在該晶片接合區與該表面黏著區之間之 線路密集區，至少一加強件係圖案化突設於一散熱片之一 下表面’並且該加強件係貼設於該基板之該線路密集區， =利至少一表面黏著元件能接合在該基板之該表面黏著 =，其係有效利用該基板之該線路密集區，在不需要擴大 土板尺寸下將表面黏著元件設置於該表面黏著區以及將一 晶片設置於該晶片接合區。 一依據本發明之高效能散熱型晶片封裝構造，主要包含 「基板、一晶片、至少一表面黏著元件（Surface 右別\)二散熱片以及至少—加強件。㊣中，該基 ，係具有一上表面，該上表面係定義有一晶片接合區以及 置二；上表面角隅之表面黏著區。㉟晶片係設 $於该曰曰片接合區，該表面黏著元件係設置於該 =。該加強件係連接該散熱片之—下表面與該基板之該 表面，以使該散熱片位於該基板之 係圖案化突設於該散埶片之該下裘& 中忒加強件 二電路密集區’以容納該表面黏著元#，即使得 者兀件係能設置於該基板之該上表面之角隅或邊緣， 需要擴大或變更該基板之尺寸。較佳 、、 不 ί 強件之幾何圖案成形。Page 7 1253131 -__, invention description (3) at least one surface adhesive component. A further object of the present invention is to provide a high-efficiency heat-dissipating wafer=package structure in which an upper surface of a substrate defines a wafer bonding region, a surface f region, and a surface between the wafer bonding region and the surface bonding region. In the line-dense area, at least one reinforcing member is patterned to protrude from a lower surface of a heat sink and the reinforcing member is attached to the line dense region of the substrate, and at least one surface adhesive member can be bonded to the substrate. The surface adhesion = which effectively utilizes the line dense region of the substrate, the surface adhesive member is disposed in the surface adhesion region and a wafer is disposed in the wafer bonding region without expanding the size of the soil. A high-efficiency heat-dissipating chip package structure according to the present invention mainly comprises a substrate, a wafer, at least one surface-adhesive component (Surface right), and at least a reinforcing member. The center has a The upper surface defines a wafer bonding region and a surface bonding region of the upper surface corner 。. The 35 wafer is affixed to the yoke bonding region, and the surface bonding component is disposed at the =. The device is connected to the lower surface of the heat sink and the surface of the substrate, such that the heat sink is patterned on the substrate and protrudes from the lower jaw of the heat sink. 'To accommodate the surface adhesive element #, that is, the edge element can be disposed on the corner or edge of the upper surface of the substrate, and the size of the substrate needs to be enlarged or changed. Preferably, the geometric pattern of the strong piece is not Forming.

L貫施方式JIL consistent method JI

第8頁 1253131 五、發明說明（4) ---—- 本發明之咼效能散熱型晶片封裝構造係以下列具 施例配合圖示說明如后。 ^ 睛參閱第3及4圖，一種晶片封裝構造1〇〇主要包含一 基板110、一晶片12〇、至少一表面黏著元件13〇 (以4“6 ount Device，SMD)、一散熱片14〇以及至少一加強件 150。其中，該基板110係具有一上表面1U以及一下表面 I ，该基板11〇應具有電性連接該上表面丨丨丨與該下表面 II 2之線路與導孔結構（圖未繪出），該上表面11 1係用以設 置該晶片120與該加強件50，該下表面112係可供對外電 f導接例如以銲球、插針、銲膏連接至一外部印刷電路 板。請參閱第3、4及5圖，該基板11()之該上表面ηι係定 義有一晶片接合區11 3、至少一表面黏著區丨丨4以及在該晶 片接合區113與該表面黏著區114間之一線路密集區115， 在本實施例中，該晶片接合區113係在該基板11〇之該上表 面ill之中央位置，該表面黏著區114係在該基板11()之該 上表面111之角隅位置。請參閱第5圖，該晶片接合區i i 3 t具有複數個覆晶墊116，其係連接複數個線路117之扇入 端（fan-in end)，以供接合該晶片12〇。該表面黏著區114 係設有複數個連接墊丨丨8與電性導接孔丨丨9，其係連接有該 二線路117之扇出端（fan-〇ut end)。而該些線路117係密 集地通過該線路密集區丨丨5。 請再參閱第3及4圖，該晶片120係設置於該基板丨1 〇之 上表面111之該晶片接合區i i 3，該晶片1 2 0係具有一主動 面121以及一對應之背面122。在本實施例中，該晶片12()Page 8 1253131 V. INSTRUCTION DESCRIPTION (4) ----- The heat-efficiency heat-dissipating chip package structure of the present invention is illustrated by the following examples. ^ Eyes Referring to Figures 3 and 4, a chip package structure 1 〇〇 mainly includes a substrate 110, a wafer 12, at least one surface adhesive component 13 (with 4" 6 ount Device, SMD), a heat sink 14 And the at least one reinforcing member 150. The substrate 110 has an upper surface 1U and a lower surface I, and the substrate 11 has a circuit and a via structure electrically connected to the upper surface 丨丨丨 and the lower surface II 2 The upper surface 11 1 is used to set the wafer 120 and the reinforcing member 50. The lower surface 112 is for guiding the external power f, for example, by solder balls, pins, solder pastes. An external printed circuit board. Referring to Figures 3, 4 and 5, the upper surface ηι of the substrate 11 () defines a die bond region 113, at least one surface adhesion region 丨丨4, and at the wafer bond region 113 In the present embodiment, the wafer bonding region 113 is at a central position of the upper surface ill of the substrate 11 , and the surface adhesion region 114 is attached to the substrate 11 ( The corner position of the upper surface 111. Please refer to Fig. 5, the wafer is connected The area ii 3 t has a plurality of flip pads 116 connected to the fan-in ends of the plurality of lines 117 for bonding the wafers 12. The surface adhesion regions 114 are provided with a plurality of connection pads. The 丨丨8 and the electrical via 丨丨9 are connected to the fan-〇ut end of the two lines 117. The lines 117 are densely passed through the line dense area 丨丨5. Referring to FIGS. 3 and 4, the wafer 120 is disposed on the wafer bonding region ii 3 of the upper surface 111 of the substrate. The wafer 120 has an active surface 121 and a corresponding back surface 122. In this embodiment, the wafer 12()

第9頁 '1253131 五、發明說明（5) 係覆晶接合至該基板11 0，以達到高效能之電性導接，該 晶片1 2係以複數個形成於該主動面1 2 1之凸塊丨2 3接合於該 晶片接合區113之該些覆晶墊116(如第5圖所示）。此外， 可在該晶片1 20之該主動面1 21與該基板11〇之上表面丨丨i之 間提供一底部填充材124 (underfilling material)、無導 電膠（Non- Conductive Paste，NCP)或角隅接合劑 (corner bond material)，以分散該晶片12〇與該基板11〇 間之應力及保護該些凸塊1 2 3。本實施並不局限該晶片1 2 〇 之封裝型態’该晶片1 2 0係可為一晶片尺寸封裝件（ch i p Scale Package, CSP) 〇 請再參閱第3、4及5圖，該表面黏著元件丨30係設置於 該基板110之該上表面113角隅之該表面黏著區114。該表 面黏著元件1 3 0係為表面黏著型態之電容、電 被動元件，或是包含上述功能之電子元件，二電二專連 接至该基板1 1 0在該表面黏著區丨i 4之該些連接墊丨〗8。 如第3圖所示，該加強件15〇係圖案化 U0之一下表面141與該基板11〇之該上表面m，可^亥二 ^片14〇4位於該基板110之上方，且該加強件15〇對應於該 土面黏者兀件130位置（如該基板11〇之角隅或邊緣）為鏤空 ίΐ/:容納該表面黏著元件130。在本實施例中，該加 50係貼設於該基板丨丨。之該線路密集區115。該加強 可與錢熱片14G為相同材質或其它高導熱性金屬， 轨η In加強件150係—體形成於該散熱片140，例如對 该散熱片14〇進行半㈣卜錢或衝壓作業以使該加強件對Page 9 '1253131 V. DESCRIPTION OF THE INVENTION (5) The flip chip is bonded to the substrate 110 to achieve high-performance electrical conduction, and the wafer 12 is formed by a plurality of convexities formed on the active surface 1 2 1 The block 丨 2 3 is bonded to the flip chip pads 116 of the wafer bonding region 113 (as shown in FIG. 5). In addition, an underfilling material, a non-conductive paste (NCP), or an underfilling material (NCP) may be provided between the active surface 1 21 of the wafer 1 20 and the upper surface 丨丨i of the substrate 11 . A corner bond material is used to disperse the stress between the wafer 12 and the substrate 11 and to protect the bumps 1 2 3 . This embodiment is not limited to the package type of the wafer. The wafer 120 can be a chip size package (CSP). Please refer to the figures 3, 4 and 5 again. The adhesive member 30 is disposed on the surface adhesion region 114 of the upper surface 113 of the substrate 110. The surface adhesive component 130 is a surface-adhesive type capacitor, an electric passive component, or an electronic component including the above function, and the second electrode is exclusively connected to the substrate 110 in the surface adhesion region 丨i 4 Some connection pads 丨8. As shown in FIG. 3, the reinforcing member 15 is formed on the lower surface 141 of the patterned U0 and the upper surface m of the substrate 11, and the upper surface 14 of the substrate 11 is located above the substrate 110, and the reinforcement is strengthened. The piece 15 〇 corresponds to the position of the soil surface member 130 (such as the corner 隅 or edge of the substrate 11 镂) is hollow ΐ /: accommodates the surface adhesive member 130. In this embodiment, the 50-series is attached to the substrate. The line dense area 115. The reinforcement may be the same material or other high thermal conductivity metal as the heat sheet 14G, and the rail η In reinforcement 150 is formed on the heat sink 140, for example, the heat sink 14 is subjected to a half (four) money or stamping operation. Make the reinforcement pair

第10頁 ,1253131 五、發明說明（6) 150係一體形成於該散熱片140。請參閱第6圖，由於該加 強件1 5 0係圖案化突設於該散熱片1 4 0之該下表面1 4 1，該 散熱片140之該下表面141上形成有一第一容置穴142及至 少一第二容置穴143。如第3圖所示，該第一容置穴142係 對應於該基板1 1 0之該晶片接合區1 1 3，以容納該晶片 120 ;而該第二容置穴143係對應於該基板ho之該表面黏 著區11 4，以容納該表面黏著元件1 3 〇。在本實施例中，該 第二容置穴1 43係為一缺口狀，以顯露該表面黏著元件 I 3 0，以擴大該基板11 〇之該上表面1丨1可設置該表面黏著 元件130之面積。此外，該第二容置穴丨43係可連通或不連 通至s亥第一谷置穴142。並且可藉由一熱導介面物質160使 該散熱片1 4 0熱耦合至該晶片1 2 0之該背面1 2 2。由於，該 加強件1 50係貼設於該基板1 1 〇之該線路密集區丨丨5，因此 不會影響該晶片1 2 0與該表面黏著元件1 3 〇設置於該基板 II 〇之該上表面1 11。此外，請參閱第4及6圖，該加強件 1 5 0係可為複數個對稱排列之塊體，其可為十字形或其它 適當幾何圖案，每一加強件1 5 〇係具有至少一往該散熱片 140邊緣延伸之延伸支條15ι，以增加對該基板丨丨^之抗翹 曲能力以及增加該散熱片丨4 〇之結構強度。 ▲因此，本發明之高效能散熱型晶片封裝構造丨〇 〇係具 有此在不需要擴大該基板110之尺寸下签合至少一之該表 面黏著元件130於該基板110之該上表面111之角隅或邊 緣。 在本發明之第二具體實施例中，如第7圖所示，其係Page 10, 1253131 V. Description of the Invention (6) The 150 series is integrally formed on the heat sink 140. Referring to FIG. 6 , since the reinforcing member 150 is patterned and protruded from the lower surface 14 of the heat sink 140, a first receiving hole is formed on the lower surface 141 of the heat sink 140. 142 and at least one second receiving hole 143. As shown in FIG. 3, the first receiving pocket 142 corresponds to the wafer bonding region 113 of the substrate 110 to accommodate the wafer 120; and the second receiving cavity 143 corresponds to the substrate. The surface of the ho is adhered to the surface 11 4 to accommodate the surface adhesive member 13 3 . In this embodiment, the second receiving hole 143 is formed in a notch shape to expose the surface adhesive component I 3 0 to enlarge the upper surface 1 丨1 of the substrate 11 可. The surface adhesive component 130 can be disposed. The area. In addition, the second receiving pocket 43 can be connected or not connected to the first valley of the shoal. And the heat sink 160 can be thermally coupled to the back surface 1 2 2 of the wafer 120 by a thermal interface material 160. Since the reinforcing member 150 is attached to the line dense area 丨丨5 of the substrate 1 1 , the wafer 1 2 0 and the surface adhesive element 13 3 〇 are disposed on the substrate II 不会Upper surface 1 11. In addition, referring to Figures 4 and 6, the reinforcing member 150 can be a plurality of symmetrically arranged blocks, which can be a cross or other suitable geometric pattern, and each reinforcing member 15 has at least one The fins 140 extend along the edge of the fins 140 to increase the warpage resistance of the substrate and increase the structural strength of the fins. ▲ Therefore, the high-efficiency heat-dissipating chip package structure of the present invention has the corner of the upper surface 111 of the substrate 110 at least one of the surface-adhesive elements 130 at the size of the substrate 110 without expanding the size of the substrate 110.隅 or edge. In a second embodiment of the present invention, as shown in Figure 7, the system

第11頁 1253131 五、發明說明（7) 揭示一種適用於高效能散熱型晶片封裝構造之散熱機構， 主要包含有一散熱片21 〇以及複數個加強件220，該些加強 件220係圖案化突設於該散熱片21〇之一下表面211，以使 該散熱片210之該下表面211上形成有一第一容置六2 12以 及複數個第二容置穴2 1 3，以分別容納一晶片與至少一表 面黏著元件（圖未繪出）。在本實施例中，該些加強件2 2 〇 係概呈T形並相互對稱，每一加強件220係具有一往該散熱 片2 1 0邊緣延伸之延伸支條2 2 1。 一在本發明之第三具體實施例中，如第8圖所示，其係 揭示另一種適用於高效能散熱型晶片封裝構造之散熱機 構\主要包含有一散熱片310以及一加強件320，該加強件 320係圖案化突設於該散熱片31〇之一下表面，以使該 =熱片310之下表面311上形成有一第一容置穴312以及複 —固=容置穴31 3，以分別容納一晶片與至少一表面黏 =圖未繪出），以使該表面黏著元件可設置於一基板 一面之角隅或邊緣。在本實施例中，該加強件320係 容納晶片之環狀體並具有複數個往該散熱片31〇邊 支條321，以維持該加強件320對-基板之抗 並可谷納複數個表面黏著元件。 為準本^月之保護範圍當視後附之申請專利範圍所界定者 圍内所你可熟知此項技藝者’在不脫離本發明之精神和範 圍内所作之任何變化與修改’均屬於本發明之保護範圍。Page 11 1253131 V. Description of the Invention (7) A heat dissipating mechanism suitable for a high-efficiency heat-dissipating chip package structure is disclosed, which mainly includes a heat sink 21 〇 and a plurality of reinforcing members 220, and the reinforcing members 220 are patterned. a lower surface 211 of the heat sink 21, such that a first receiving portion 612 and a plurality of second receiving holes 2 1 3 are formed on the lower surface 211 of the heat sink 210 to respectively accommodate a wafer and At least one surface adhesive element (not shown). In this embodiment, the reinforcing members 2 2 are generally T-shaped and symmetrical with each other, and each reinforcing member 220 has an extending struts 2 21 extending toward the edge of the heat dissipating fins 210. In a third embodiment of the present invention, as shown in FIG. 8, it is disclosed that another heat dissipating mechanism suitable for a high-efficiency heat-dissipating chip package structure mainly includes a heat sink 310 and a reinforcing member 320. The reinforcing member 320 is patterned and protruded from a lower surface of the heat sink 31 such that a first receiving hole 312 and a complex-receiving hole 31 3 are formed on the lower surface 311 of the hot plate 310. Each of the wafers is affixed to at least one surface (not shown) so that the surface adhesive component can be disposed on a corner or edge of one side of the substrate. In this embodiment, the reinforcing member 320 is configured to receive the annular body of the wafer and has a plurality of ribs 321 toward the heat sink 31 to maintain the resistance of the reinforcing member 320 to the substrate and to form a plurality of surfaces. Adhesive components. The scope of protection of this section is subject to the definition of the scope of the patent application, which is to be understood by those skilled in the art, and any changes and modifications made by those skilled in the art without departing from the spirit and scope of the invention The scope of protection of the invention.

圖：習知高效能散熱型晶片封裝構 =圖··習知高效能散熱型晶片封裝構造° 晶片封裝構造之截面示意、@。實^ —南效能散熱趣 該晶片封裝構造 該晶片封裝構造 該晶片封裝構造 另一高致能散熱 Ο 另一高效能散熱 圖.依據本發明之第一具體實 之頂面透視圖。 明之第—具體實施例 反上表面之局部示意圖。 :6'::依據本發明之第-具體實施例 之政熱片之立體底面示意圖。 第7圖·•依據本發明之箆-型日Κ 44壯说第—具體實施例， 二曰曰片封裳構造之散熱片之下表面』 圖：依據本發明之第三罝二 型晶片封裝構造之散熱片之；； 〜广衣面不意圖 元件符號簡單說明 1 晶片封裝構造 10 基板 2 0 覆晶晶片 23 凸塊 30 散熱片 S1 間隙 1 0 0晶片封裝構造 11 上表面 21主動面 24 底部填充材 40加強環 1222 下表面背面 50 熱導界面物質 1253131 面 圖式簡單說明 110基板 1 1 3 晶片接合區 1 1 6 覆晶塾 119電性導接孔 1 2 0晶片 1 2 3凸塊 14 0散熱片 142第一容置穴 1 5 0 加強件 21 0散熱片 212第一容置穴 220加強件 31〇散熱片 3 1 2第一容置穴 3 20加強件 111上表面 11 4 表面黏著區 11 7 線路 1 2 1 主動面 124底部填充材 141 下表面 1 43第二容置穴 1 5 1延伸支條 211下表面 213第二容置穴 2 2 1延伸支條 311下表面 313第二容置穴 3 2 1延伸支條 112下表 Π 5 線路密集區 11 8 連接塾 1 2 2背面 1 3 0表面黏著元件 160熱導界面物質Figure: A well-known high-efficiency heat-dissipating chip package structure. Fig.···························· The present invention is a chip package structure, the chip package structure, the chip package structure, another high-energy heat dissipation, another high-efficiency heat dissipation, and a first detailed perspective view of the top surface according to the present invention. The first embodiment - a specific embodiment of the reverse upper surface. : 6':: A schematic perspective view of a top surface of a political sheet according to the first embodiment of the present invention. Fig. 7 is a third surface of a heat sink according to the present invention. Fig. 7 is a third type of chip package according to the present invention. The heat sink of the structure is not specifically designed for the symbol of the device. 1 wafer package structure 10 substrate 2 0 flip chip 23 bump 30 heat sink S1 gap 1 0 0 chip package structure 11 upper surface 21 active surface 24 bottom Filler 40 Reinforced Ring 1222 Lower Surface Back Surface 50 Thermal Conductivity Interface Material 1253131 Surface Description Simple Description 110 Substrate 1 1 3 Wafer Bonding Area 1 1 6 Flip Chip 119 Electrical Conduction Hole 1 2 0 Wafer 1 2 3 Bump 14 0 heat sink 142 first receiving hole 1 50 0 reinforcing member 21 0 heat sink 212 first receiving hole 220 reinforcing member 31 heat sink 3 1 2 first receiving hole 3 20 reinforcing member 111 upper surface 11 4 surface adhesion Area 11 7 Line 1 2 1 Active surface 124 Underfill 141 Lower surface 1 43 Second accommodating hole 1 5 1 Extension 211 Lower surface 213 Second accommodating hole 2 2 1 Extension 311 Lower surface 313 Second容 穴 3 2 1 Extension struts 112 Table Π 5 Line-intensive areas 11 8 Sook backside surface 130 122 160 thermal conductivity of the interface element adhesive material

第14頁Page 14

Claims (1)

12531311253131 【申請專利範圍】 1、一種晶片封裝構造，包含： 一基板，其係具有一上表面，該上表面係定義有_晶 片接合區以及至少一位於該上表面角隅之表面黏著區； 一晶片，其係設置於該基板之該晶片接合區； 至少一表面黏著元件（Surface Mount Device， SMD) ’其係設置於該表面黏著區； 一散熱片，其係具有一下表面；及 至少一加強件，其係連接該散熱片之該下表面與該基 板之違上表面，該加強件係圊案化突設於該散熱片之該下 表面’以容納該表面黏著元件。 2 '如申請專利範圍第1項所述之晶片封裝構造，其中該 加強件係為十字形或T形。 3、 如申請專利範圍第1項所述之晶片封裝構造，其中該 加強件係一體形成於該散熱片。 4、 如申請專利範圍第1項所述之晶片封裝構造，其中在 該基板之該上表面係定義有一線路密集區，其係在該晶片 接合區與該表面黏著區之間。 5、 如申請專利範圍第4項所述之晶片封裝構造，其中該 加強件係貼設於該基板之該線路密集區。 6、 如申請專利範圍第1項所述之晶片封裝構造，其中該 散熱片之該下表面形成有一第一容置穴以及至少一第二容 置穴，該第一容置穴係對應於該基板之該晶片接合區以容 納該晶片，該第二容置穴係對應於該基板之該表面黏著區[Patent Application Scope] 1. A wafer package structure comprising: a substrate having an upper surface defining a wafer bonding region and at least one surface adhesion region at the upper surface corner; a wafer Provided in the wafer bonding region of the substrate; at least one surface mount device (SMD) is disposed in the surface adhesion region; a heat sink having a lower surface; and at least one reinforcing member The lower surface of the heat sink is connected to the upper surface of the heat sink, and the reinforcing member is protruded from the lower surface of the heat sink to accommodate the surface adhesive component. 2' The wafer package construction of claim 1, wherein the reinforcement member is in the shape of a cross or a T. 3. The wafer package structure of claim 1, wherein the reinforcement member is integrally formed on the heat sink. 4. The wafer package structure of claim 1, wherein the upper surface of the substrate defines a line dense region between the wafer bond region and the surface adhesion region. 5. The wafer package structure of claim 4, wherein the reinforcement member is attached to the line dense region of the substrate. The wafer package structure of claim 1, wherein the lower surface of the heat sink is formed with a first receiving hole and at least one second receiving hole, wherein the first receiving hole corresponds to the The wafer bonding region of the substrate to accommodate the wafer, the second receiving cavity corresponding to the surface adhesion region of the substrate 12531311253131 申請專利範圍 以容納該表面黏著元件。 其中 中该 %% 7、 如申請專利範圍第i項所述之晶片封 加強件係具有往該散熱片邊緣延伸之延伸^ 8、 如申請專利範圍第丨項所述之晶片封=二 晶片接合區係在該基板之該上表面之中央^了 9、 如申請專利範圍第1項所述之晶片封裝槿造 散熱片係熱耦合至該晶片。 & 造 其 其中 其 其中該 其中該 其中該 10:如申請專利範圍第項所述之晶片封 中違晶片係覆晶接合至該晶片接合區。 、 11、如=請專利範圍第丨項所述之晶片封装構造 表面黏著元件係為一被動元件。 專：範圍第1項所述之晶片封裝構造 弟一合置八係為一缺口，以顯露該表面黏著元件 13、 如申請專利範圍第1項所述之晶片封裝構造 第二谷置穴係連通至該第一容置穴。 14、 一種晶片封裝之散熱機構，包含： 一散熱片，其係具有一下表面；及 至少一加強件，其係圖案化突設於該散熱片之該下表 面’以使該散熱片之該下表面形成有一第一容置穴以及至 少一第二容置穴，以分別容納一晶片與一表面黏著元件。 1 5、如申請專利範圍第1 4項所述之晶片封裝之散熱機 構’其中該加強件係為十字形或T形。 1 6、如申請專利範圍第1 4項所述之晶片封裝之散熱機 構’其中該加強件係一體形成於該散熱片。 IIH 第16頁 1253131 六、申請專利範圍 17、如申請專 構，其中該加 條0 18、一 片接合 黏著區 種晶片 基板， 區、_ 之間之 利範圍第1 4項所述之晶片封裝之散熱機 強件係具有往該散熱片邊緣延伸之延伸支 封装構造’包含： 曰曰 片 SMD) 至少一表 ’其係設 一散熱片 至 該基板 19、如 該表面 2 0、如 該加強 21、如 該加強 2 2、如 該散熱 2 3、如 该晶片 2 4、如 少一加 之該線 申請專 黏著區 申請專 件係為 申請專 件係一 申請專 片係熱 申請專 係覆晶 申請專 其係具 表面黏 線路密 其係設 面黏著 置於該 ’其係 強件， 路密集 利範圍 係位於 利範圍 十字形 利範圍 體彤成 利範圍 耦合至 利範圍 接合至 利範圍 有一上表面，該上表面係定義有_晶 著區以及一在該晶片接合區與該表面 集區； 置於該基板之該晶片接合區；元件（Surface Mount Device， 基板之該表面黏著區； 位於該基板之該上表面之上；及 其係圖案化連接於該散熱片並貼設於 區。 第1 8項所述之晶片封裝構造，其中 該基板之該上表面之邊緣。 第1 8項所述之晶片封裝構造，其中 或丁形。 第18項所述之晶片封裝構造，其中 於該散熱片。 第18項所述之晶片封裝構造，其中 該晶片。 第1 8項所述之晶片封裝構造，其中 該晶片接合區。 第18項所述之晶片封裝構造，其中The patent application scope is to accommodate the surface adhesive component. Wherein the wafer seal reinforcement member as described in claim i has an extension extending toward the edge of the heat sink, and the wafer seal = two wafer bond as described in the scope of the patent application. The wafer is mounted on the center of the upper surface of the substrate. The wafer package thermal pad described in claim 1 is thermally coupled to the wafer. And wherein: wherein: wherein: 10: the wafer-sealing of the wafer according to claim 2 is flip-chip bonding to the wafer bonding region. 11. The wafer package structure as described in the above patent scope is a passive component. The chip package structure described in the first item is a gap in which the surface mount component 13 is exposed, and the chip package structure described in claim 1 is connected to the second valley. To the first receiving hole. A heat dissipation mechanism for a chip package, comprising: a heat sink having a lower surface; and at least one reinforcing member patterned to protrude from the lower surface of the heat sink to make the heat sink The surface is formed with a first receiving hole and at least one second receiving hole for respectively accommodating a wafer and a surface bonding component. The heat-dissipating mechanism of the chip package of claim 14 wherein the reinforcing member is in the shape of a cross or a T. The heat dissipating device of the chip package of claim 14, wherein the reinforcing member is integrally formed on the heat sink. IIH Page 16 1253131 VI. Patent Application Area 17. If the application is self-contained, the application of the package 0 18, a piece of bonding pad substrate, the wafer package of the area, the range between the _ and the _ The heat sink strength member has an extended branch package structure extending toward the edge of the heat sink. The package includes: at least one watch 'which is provided with a heat sink to the substrate 19, such as the surface 20, such as the reinforcement 21. If the reinforcement 2 2, such as the heat dissipation 2 3, such as the wafer 24, if less than one plus the line application for the adhesive area application component is for the application of a special department for a special application for the application of thermal application for the application of the application It is specially designed to have a surface-adhesive line and its surface is adhesively placed on the 'strong part of the system. The road is densely distributed. The range is in the range of the cross. The range is in the range of the profit. The range is coupled to the profit range. The upper surface defines a crystallization region and a wafer junction region and the surface collection region; the wafer bonding region disposed on the substrate; and the component (Surface Mount Device) The surface of the substrate is disposed on the upper surface of the substrate; and is patterned and connected to the heat sink and attached to the region. The chip package structure of claim 18, wherein an edge of the upper surface of the substrate The wafer package structure of any one of the preceding claims, wherein the wafer package structure of the item 18, wherein the wafer is packaged. The wafer package structure of the item, wherein the wafer bonding region, the chip package structure of item 18, wherein 第』7頁 1253131 六、申請專利範圍 該表面黏著元件係為一被動元件。 ι·ιι 第18頁Chapter 7 Page 1253131 VI. Patent Application The surface adhesive component is a passive component. ι·ιι第18页
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