TWI251801B - Image display device, pixel drive method, and scan line drive circuit - Google Patents

Abstract

To supply selection signals to multiplexed pixels efficiently. For a period from time t0 to time t2, first, during a period from time t0 to time t1, a pixel electrode All is driven by selecting scan lines Gn+1 and Gn+2, and next, during a period from time t1 to time t2, a pixel electrode bll is driven by selecting only the scan line Gn+1. Moreover, during the period from time t1 to time t2, scan lines Gn+3 and Gn+4 are also selected, and thus a pixel electrode A12 is driven. After time t2, at least one of the scan lines Gn+3 and Gn+4 is not selected before the pixel electrode A12 is driven by selecting both of the scan lines Gn+3 and Gn+4 during a period from time t4 to time t5. Accordingly, the pixel electrode A12 can be preliminarily charged during the period from time t1 to time t2 and can maintain a potential preliminarily applied thereto until the pixel electrode A12 is driven during the period from time t4 to time t5.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image display device, a pixel driving method, and a scanning line driving circuit, and more particularly to a liquid crystal display panel (1 iquidcrysta 1 disp) 1 ay, LCD) technology. BACKGROUND OF THE INVENTION In general, for a display device driven by an active matrix driving system, when the number of display pixels is increased, the number of driving integrated circuits (ICs) is also increased, resulting in cost. improve. Further, when the definition of the screen is improved, it means that the pixel interval is narrowed, so that it becomes more difficult to connect one pixel to one drive integrated circuit. Therefore, in order to solve these problems at the same time, a display device employing a multiplexed pixel structure has been proposed. Here, the potential between two or more adjacent pixels in different time segments in a data column is utilized, so that the height (p i t c h ) between the connection terminals is increased and the number of driving integrated circuits is reduced. For example, the display device disclosed in Japanese Patent Laid-Open No. 5 (1 9 9 3 ) - 3 0 3 1 1 4 and Japanese Patent Laid-Open No. 8 (1 9 9 6 ) - 2 4 8 3 8 5 . SUMMARY OF THE INVENTION Problems to be Solved by the Invention In the display device having the multiplexed pixel structure as described above, in accordance with the multi-engineering degree of pixels of a horizontal scanning period, a plurality of types of selection signals must be provided for a column of pixels. Therefore, pixels are usually multiplexed according to pixels.

___ Page 6 1251801 V. INSTRUCTIONS (2) The degree is selected from the combination of scan lines of other systems. However, the selection logic that provides the selection signals for these complex patterns has not been established. In order to select a plurality of scan lines, a selection pulse consisting of a plurality of offset timers is successively transferred to a buffer connected to the input of the scan line, which is sufficient. However, since only the selection pulse does not constitute logic, a number of systems with output control lines must be provided to control the on/off of the buffer. However, the relationship between the number of systems having an output control line and the number of offset pulses of the selection pulse is not significant, or it is not clear which output control signal can effectively control the on/off of the buffer. Further, in this display device, since the electric charge has been used for two or more pixels in each time interval in a time before a charge is used for one pixel, the charging time is shortened. That is to say, as long as a selection element is not amplified, the accuracy of the potential used will be lowered, causing a problem. A method for compensating for a shortage of charge, known as precharge, is well known. Here, precharging is indicated before the data is written to a pixel, and data of the same polarity is previously written into the pixel. Therefore, even if the amount of a charge when the data is written to the pixel is small, the desired amount of charge can be obtained. The precharging method as described above can also be applied to a display device including non-multiplexed pixels when one of the high resolution write times is insufficient. In this display device, since the pixels are not multiplexed and normally driven, the time for performing the precharge can be determined in particular by selecting the time close to the precharged pixels and one pixel of the same polarity. However, if the scan lines of other systems are shared with adjacent columns in a display device having a multiplexed pixel structure,

Page 7 ^ {3) It is difficult to drive backwards and between places. , ‘’. The logical time of 5 is specifically determined by the present invention: the pre-charging, providing an image g to the technical subject matter. This is the main screen for you, the pot can be on the right 4 丄 ^ one of the sun and the moon ί pixels and other phases: effectively provide choice 氘 $ a eve, display device, 苴 ^ East this invention another - destination 5 Tiger multi-work method and other; secondly, the time to pre-charge is determined in time, like ♦ providing an image of the same thing. Pixel body waveform and device for solving the problem 'The present invention provides a map of the present invention = "Pixel-Pixel" group complex: the water is known to continuously select the cycle, and to a specific signal line; a second: After the horizontal sweeping period, :::, and the second pixel electrode group is coupled to the line group for providing a scan signal that can be used in the first water, the group; and a second scan: a horizontal scanning period to drive the second In order to achieve the above, the pixel has two features. = two pixel electrode group is connected to a brother-pixel t (four) system group: "two pixel electrode group two: flat scan cycle continuous selection - first scan = cycle drive first pixel wire group" is used to provide a group Scanning signal. Here, the characteristic scan line group displayed by the image is driven in the pixel electrode group, and the scan line is not self-aligned: the second scan line group is selected to be selected. First, ^, from and to a specific scan line; 7 flat to know the specific group of the cycle ^

1251801, invention description (4) I selected to the second horizontal sweep --- selected. During the period of the field, the period between the specific π-image electrodes is driven in this structure, 6 from the first - Huanhua 4, the 夂 scan line group, the selection of the specific group in the drive ii; the broom line f Non-I, therefore, is a special image that is selected when the t-line group is selected. The specific electrode of the horizontal scanning period of the 1st Ά Ά z is not charged. I is pre-charged. The driving of the special pixel electrode can be determined to be in the second insertion period and the second horizontal scanning period; the stator element is at the first level. In addition, specific scan lines are driven at the same polarity. Therefore, the group that is selected at the same time ==; the group can share at least - sweep _ in addition, here at a same level, the number will be reduced. : display signal of polarity, in addition, in the center of the heart =: 'individual signal line provides the adjacent signal between the lines";::: J period, pixels selected continuously in the complex finger period) movable pixels ( The present invention can also be understood as the invention according to the same level sweeping. In particular, the image of the present invention is displayed in a first horizontal scanning period: _ = element electrode connection To a specific signal line; another:; = 'and, after the first-horizontal scanning period, continuously driving in a second image: the electrode's time-point to the m-th time point; Another m pixel electrode system page 9 丄 251801 V. Invention description (5) knot to a specific signal line; and one - ^ ^ period drive another _ = field line, 'selected to the second level = cycle, In the scan line group, since ° = sign t in the second horizontal sweep ', the group is also the natural number of a specific scan m selected at the first level sweep. The field period is selected, and the η value is determined by匕 As described above, the first ρ scan line is also selected at the ηth time point of the 7:::th drawing period; precharge In the second level, the selected result, will prime. / Di spoon is driven between a dot image

The selection time can be different: ί: 2: period ★,. For the specific scan line group, the specific scan line can be used to know the Γ1 time point in the trace period. This, the water is ten percent in the Zhousi, and the line of the poem is used to provide the line. The sub-control _ pixel electrode scan in addition to the 'specific scan line group in the flat scan period, at least one scan line from the 箆, may not be m, from the -H time point to the (n-1) time point Ershui, brother - horizontal scanning week ^ out of the point. Because - the pixel electrode is not driven from the second: the selection of the specific scan line group is driven by the η time point. ^ (η-~ between the points. In addition, in the first caller a horizontal scanning period, the special line can be different from the scanning signal of the sensor electrode to provide the driving _ In addition, the present invention can be similarly understood as a ferrule driving circuit! 2518 〇 ι 5, invention description (6) I invention. In particular, the invention of the invention, the wheel 2 can be connected to a plurality of scanning Line; a plurality of transmission features 匕 corresponding to a plurality of output terminals; a meta-L. seven shouting output unit in a u τ a current 唬 column; its = to a plurality of output terminal groups::: description, mid-term, At the same time, the output letter l:=:r moves out of the terminal, 』confidence:::every|round_m This characteristic line driving circuit is characterized by: V: the terminal is like the wheel out of the terminal group in the temple: on: The first time in the tracing cycle:: The other work in the horizontal scanning cycle: the t-flat is different from the Ή 4 inch 作 作 έ - signal to a specific round-out terminal in the event of an 'output zone-driven image'; to select a connection to a specific round-out terminal...t two times No driving inside. Special two: ? point, and can be set to I until the second electrode * and the pixel electrode "1 can be charged at the first turn point. Temple pre-charge potential, this: Ming: :: The first-level rf pixel driving method also has a - pixel driving method, which includes: - Jth. Special electric; in: ί; cycle, select and start the pair - "Turn in - horizontal scanning"; Step::: r: the horizontal sweep electrode electrode group is filled with lightning, the performance is extracted, the witch contains the specific ^ - the step - the electricity: straight, characterized by the pixel position of the specific pixel electrode electrode until the second After the step selection, it is kept fine on the first page 111251801. 5. Description of the Invention Here, a plurality of pixel electrodes are formed in a matrix and the pixel electrodes A and B of the same group are in the same column, and the driving polarity is In addition, the output registers are respectively connected to the input ends of the scan lines, and the three adjacent output registers are controlled by different control signals, and a signal column is first Pulse and a second pulse, first The pulse has a length of one of two horizontal scanning periods, the second pulse has one of two horizontal scanning periods, and the signal sequence is transmitted to each output register continuously for each horizontal scanning period, the second pulse In another aspect, the present invention may include an image display device as follows. In particular, the image display device includes: a plurality of scan lines, a system for providing a scan signal; a plurality of output control lines; a plurality of output buffers respectively assigned to and connected to the output control line; and a control signal output unit for respectively outputting control signals different from each other The system to the output control line. With such an architecture, the signals provided to the plurality of scan lines can be simultaneously controlled, and the pixel electrodes driven by the combination selected from the plurality of scan lines can be driven in time. Here, the image display device further includes a pulse signal providing unit for continuously transmitting a pulse signal having a specific length of time to the output register, and each pulse signal has a time length, which is long It is m times of a horizontal scanning period (m is a natural number), and the number of the output control lines is η system instead of m (η is a natural number of 2 or more). In addition, the present invention can also have the following filBl_circle of the scanning line driving circuit _

Page 15 1251801 V. Description of invention (11). In particular, the scan line driving circuit of the present invention comprises: a plurality of output terminals respectively connectable to a plurality of scan lines; an output circuit connected to the output terminal; and a control signal generating unit for generating a control output The control signal of the output of the circuit is characterized in that n kinds of output signals are generated (n is a natural number of 2 or more), and the n kinds of output signals are respectively supplied to n output circuits. The scan line driving circuit as described above further includes: a plurality of offset adjusters respectively connected to the output circuit and connected to each other in series; a timing signal generating unit for generating a timing signal for driving the offset adjuster; and a signal A column generation unit for generating a signal train for continuous transfer to the offset adjuster. Here, each signal train has a time length of m times the timing signal (m is a natural number), and the m value can be larger or smaller than the value of η. In particular, when the value of m is greater than the value of η, a plurality of scan lines can be selected and controlled by a relatively small number of control signals. BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, embodiments of the present invention and corresponding drawings will be described in detail. First Embodiment FIG. 2 is a view showing an overall configuration of an embodiment of a liquid crystal display device of the present invention. Figure 3 shows a schematic diagram of the array substrate architecture. Figure 4 shows a block diagram of the main architecture of a gate driver and a control circuit as shown in Figure 2. The liquid crystal display device of this first embodiment has a feature that is a clip

Page 16 1251801 V. INSTRUCTIONS (12) This signal line is shared by two adjacent pixels that squeeze a signal line to reduce the number of signal lines by half. In this method, the liquid crystal display device must include a color filter substrate, a backlight unit, and other components facing the array substrate. However, the above portions may be omitted without the features of the present invention. As shown in Fig. 2, a liquid crystal display device (image display device) 1 of the present embodiment includes a display area S for displaying an image on an array substrate A. In addition, the liquid crystal display device 1 includes a data driver 3 for providing a display signal from the signal line D to the pixel electrode located in the display area S; a gate driver (scanning line driving circuit) 5 for providing control for display The thin film transistor formed in the region S is a scan signal for turning on/off the thin film transistor of the scanning line G; and a control circuit (scanning signal driving circuit) 6 for controlling the gong drive and the gate drive. In the display region S, the pixel electrodes are formed by an MN matrix (Μ and N are any positive integers), and a certain number of scanning lines G and signal lines D are provided. This number corresponds to the number of these pixel electrodes. Hereinafter, in the scanning line G connected to the same gate driver 5, a scanning line G located at the nth position in a scanning direction of a screen will be represented as a scanning line Gn. In the signal line D connected to the same data driver 3, a signal line D at the mth position from an input terminal of the scanning line G will be represented as a scanning line Dm. In addition, as shown in FIG. 3, in the display region S of the array substrate A, for the signal line Dm interposed by the adjacent pixel electrodes A 1 1 and B 1 1 , three thin film transistors (TFTs), such as a first A thin film transistor, a second thin film transistor M2, and a third thin film transistor M3 are disposed as follows.

Page 17 1251801 V. INSTRUCTION DESCRIPTION (13) First, in the first thin film transistor Μ1, one source electrode is connected to the signal line Dm' and one 汲 electrode is connected to the pixel electrode Αn. Further, the gate electrode of the first thin film transistor is connected to a source electrode of the second thin film transistor M2. Here, for a conversion element having three terminals (switching = thin film transistor, for example, in a liquid crystal display device, the connection 2: t 2 Ϊ 2 - the side (terminal) is regarded as a source electrode, and is connected to one, One side of the element (terminal) is treated as a 汲 electrode. Therefore, the above two types of electricity are about to be used as the source electrode / 汲

In the membrane electro-crystal (4), one of the source electrode and the non-electrode is connected to the gate electrode of the 溽臊1 transistor, and the other ρι|, έ & s scan line Gn + 2. Because, the room continues to spray B ^ is connected to a film ... ' L Ϊ : it ί / 1 of the gate through the second M2 of the gate electrode: ΪΓΓ, outside, the second film transistor teeth, connected to I know the 4 field line G n + 1. Therefore, when the film life command ai/, G 2 and the custodian are in a selection potential, the first ", the fast Japanese body M 1 breaks open, and the potential of the signal line Dm is recognized by your main pole A1 1 . This table thousand wrong - ★ ^ J potential break & supply pixel power, Yi Budi thin film transistor M2 control the first private on / off. The thicker transistor Ml is connected to the third thin film transistor 3 and is connected to one of the electrodes and the electrodes.

The main broken line Dm is reversed, and the other is connected to the stupid. Further, one electrode of the third thin film transistor M3 = the electrode B11.

Gn + 1. Therefore, the broadcast pr := is connected to the scan line Tian Tian 4 line Gn + 1 in a choice Lei bamboo n ± - crystal M3 is turned on, and 俨 secret 蠄 nm. Lei you 4 α potential ¥, brother three thin film electricity Bl 1. "The potential of the D line Dm is supplied to the pixel electrode 1251801. 5. Description of the invention (14) ^ -__ The above-described circuit structure from the first thin film transistor M to the third array substrate A, the following will describe the pen crystal M3 The circuit frame of the array substrate A seen by the input electrode B 1 1 "electrode A 1 1 is supplied to the pixel electrode B11 by the single-signal line ^. The display pixel electrode A1 erase line Dm may be connected to the pixel electrode a 1丨 and pixel electrodes, in addition, the line. Therefore, for the pixel located in the matrix MN, the shared signal of 屯° 11 is Μ / 2 . The number of D 5 tiger lines D m will be the first thin film electric arc film transistor M2 for the pixel electrode A1. In addition, the first thin film transistor _ = 乐 乐 : _ two thin film transistor M2. $2 thin film transistor_=信信^The next step of the pixel electrode Al1 is connected to the scanning line Gn+. In addition, the 汲 electrode of the handle thin film transistor 乂2 is connected to the next step of the scanning line Gn+1' The second line is Gn + 2. Here, in order to provide a potential of the signal line such as to A1 to A1 1, the first thin film transistor mi must be turned on. In addition, the first film 卞 ', one of the electric crystal poles. The gate electrode of the second thin film transistor M2 is connected to its 'electricity

The gate electrode of the body M1 is connected to the source electrode of the second thin film transistor M2, =

Scan line Gn + 1. The other of the source/germanium electrodes is below - ' : it is connected to the scanning line Gn + 2. Therefore, the second thin film transistor must be turned on to defeat the first thin film transistor Μ1. In order to turn on the second thin film transistor μ 2, 'scanning line Gn + Ι and scanning line Gn + 2 are simultaneously selected. Therefore, the first thin film M1 and the second thin film transistor M2 form a switching mechanism, so that when the scan Gn+Ι and the scan line Gn+2 are simultaneously selected, the scan signal can pass. In a manner as described, the pixel electrode A 1 1 is driven in accordance with the scanning signal of the scanning line Gn + 1 and the scanning signal of the upper line Gn + 2 to receive the signal line Y, Y

Page 19 1251801 V. Description of the Invention (15) For the pixel electrode B 1 1 , it is connected to the third thin film transistor M3, wherein the gate electrode is connected to the scanning line Gn+. Therefore, the pixel electrode B1 1 is provided when it is scanned. The potential of the signal line Dm when the line Gn + 1 is selected. The above is a description of the pixel electrode A 1 1 and the pixel electrode B 1 1 . In addition, for other pixels (pixel electrodes) shown in FIG. 3, for example, the pixel electrode C 1 1 and the pixel electrode D 1 1 , the pixel electrode A 1 2, B 1 2, C 1 2, and D 1 2, the pixel electrode A 1 3. B 1 3, C 1 3, and D 1 3, as well as other pixels, will adopt a similar architecture. Next, the structure of the gate driver 5 and the control circuit 6 shown in Fig. 4 will be described below. As shown in Fig. 4, the control circuit 6 has an output ON/OFF control unit 8, a pulse generating unit (signal column generating unit) 9, and a timing signal generating unit 10. As will be described later, the output ON/OFF control unit 8 outputs an output control signal to the gate driver 5, and as a whole, the three systems of the output control line OE are composed via the output control lines 0E1, 0E2, and 0E3. The pulse generating unit 9 generates a scanning signal which is output from the gate driver 5 to the scanning line G, that is, an offset pulse. Further, the timing signal generating unit 10 outputs a timer signal to drive the gate driver 5. In the gate driver 5, an offset adjuster unit 12 is provided in which an output control signal, an offset pulse, and a timing signal are input. This offset adjuster unit 12 is composed of a series-connected offset adjuster SR. The number of this offset adjuster SR is equal to its scan line G. Here, the offset adjuster SR corresponds to the opposite scanning line G and is connected to the output terminal OT which is connectable to the scanning line G via the buffer B (output circuit). Therefore, the control buffer B can be controlled

__ Page 20 1251801 V. INSTRUCTIONS (16) Data output from the offset adjuster SR to the scan line G.

For buffer B, it is connected to output control line 0E. When the book control signal is input such that the output control line 0E is π 0 ", this buffer B is activated. Further, when the output control line is "1", the buffer Β is turned off. Therefore, by offset adjustment The output selection of the scan signal of the SR to the scan line G will be controllable. It should be noted that when a plurality of buffers Β correspond to the scan line G, the output control lines 0 Ε 1, 0 Ε 2, and 0 Ε 3 are Continuously distributed and connected to every three buffers adjacent to each other. Therefore, the output start/stop control unit outputs output control lines 0Ε 1, 0Ε2, and 〇Ε3, thereby making it possible to individually control the three adjacent to each other. The buffer Β Next, the operation of the liquid crystal display device 1 will be described below based on the scanning signal schedule shown in Fig. 1 and the circuit diagrams shown in Figs.

In order to solve the shortage of the pixel charge amount, the liquid crystal display device operates as follows. In one horizontal scanning period of one screen, a display signal voltage is written into the pixel before being held by one pixel, and the display signal voltage is firstly displayed. Write. For this purpose, when a specific display signal voltage is applied to a certain pixel, the specific display signal voltage is simultaneously written to one pixel at a time below one pixel. That is, another pixel is charged after this pixel. Therefore, when a display signal voltage is actually applied to the pixel at the next stage, the pixel is set to a state ready to be charged at a specific voltage. A pixel driving method and a preliminary driving method (precharge method) before a real pixel driving will be specifically described below. As shown in FIG. 1, the graph Gn+1 ou t to the graph G η + 5 〇ut represents the waveform of the scan signal output to the scanning lines G η + 1 to G η + 5, which is transmitted by the offset pulse i2518〇 1______ V. Description of the invention (17) Generated by the recursive offset adjuster SR. In particular, in these illustrations, when the portion indicated by each/solid line or broken line rises, the relevant scanning line G is selected, and when not rising by these portions, the associated scanning line G· Will not be elected. It is to be noted that, in the rising portion of these figures, the portion indicated by each solid line indicates the time at which the display signal voltage maintained by the one-pixel electrode is written in a horizontal scanning period. Further, the portion indicated by the dashed line to the time when the display signal voltage is previously written to the pixel electrode is made to compensate for the shortage of the display signal voltage before the signal voltage is written. Specifically, the portion indicated by the broken line indicates the time point of pre-charging. ^ | Further, Dm (1) in Fig. 1 indicates the potential of a data signal supplied from the signal line Dm, which indicates the point in time at which the data signal is charged. Dm (1) shown here indicates a change in polarity. As will be described later, by the potential supplied from the signal line Dm, the pixel electrode A1 is set to be the same as the polarity of the pixel electrode Bi 1 and is moved by the horse to be different from the pixel electrodes C 1 1 and D 1 1 Under the polarity. Hundreds of firsts write a concatenated program into a display signal voltage to a pixel and maintain it. ^ ^ ® - 7F 'When the scanning signals Gn+1 out and Gn + 2 out are generated 'If = is intended to be the portion indicated by the solid line in the scanning lines Gn+1 and Gn + 2, that is, when the signal is # The voltage is written to the time point of the pixel, after which the scanning lines Gn+1 and Gn + 2 (the first scanning line level) are selected from time to time (the first time point, the first week f is selected. Therefore, as shown in FIG. As shown, the first to fourth thin film transistors M1 to M3 are activated. Therefore, from the signal line Dm to

Page 22 1251801

V. DESCRIPTION OF THE INVENTION (18) The pixel electrode A1m - the potential vall is supplied to the pixel electrode Au, and the potential Vall of the pixel electrode A1 is determined. :::: In Figure 5, the selection of Scanning 1st 2 is in bold line, as follows from time t1 to time t2 (second time point, period), scan line Gn + 2 is set to be unselectable Potential, and corpse = two = line Gn + 1 was selected. Therefore, as shown in Figure 6, the mouth of the Putian M3 is activated. Here, from the signal line shout :, film transistor

B11 determines the potential of the pixel electrode B11. It is to be noted that the pixel electrode is clamped to the flat scan period from the time to the time (the first horizontal scan period 7 =:::= is completed in the -water:: period, s this potential of the signal line Dm; ; k = to the pixel electrodes A11 and B11 (the first pixel electrode group): the keeper & between the description line Gn + 1 is set to be unselectable: the power of the prime == = (four) turn to 〇ut, Gn + 2# 〇 The period of UtM Gn + 3 points is selected..., such as the first time D1 and M2, and the silly +\ is supplied to the pixel electrode C11, and the potential Vc" of the electrode (1) is determined. From the day to the day 13 to time 14 (黛_士 a,

Gn + 3 is set to be non-selectable - just at the point), the scanning line is clamped, and the known line Gn + 2 is selected.

1«*®' 1111第23页

1251801 V. INSTRUCTION DESCRIPTION (19) Therefore, as shown in FIG. 8, the potential supplied from the signal line Dm is changed to the potential Vdl1 applied to the pixel electrode D11, and therefore, the potential Vdl1 is supplied to the pixel electrode D11. The potential of the pixel electrode D 1 1 is determined. Here, the polarities of the potentials Val 1 and Vbl 1 supplied to the pixel electrodes A1 and B11 are reversed to the potentials Vcl 1 and V d 1 1 supplied to the pixel electrodes C1 and D11. Therefore, the liquid crystal display device 1 is driven as a display device of one line reverse driving (1 1 n e inversion d r i v e ), in which the polarity of each column is turned. Next, a precharge method of a pixel will be described below. As described above, the precharging of the pixel is performed by supplying a display signal voltage to a pixel electrode when applied to the next stage of the pixel electrode for display signal voltage and charging. Here, the pixel electrode at the next stage is selected by the scanning line G having one of the values larger than η. Thereafter, the application for maintaining the display signal voltage of the pixel electrode by a pixel electrode will be simply expressed as π charge π, and another display signal voltage charged before the application of the display signal voltage maintained by the pixel electrode will be Indicated as π precharge 〇 一 While a particular pixel electrode X is precharged, a pixel electrode Υ will be charged as 像素 and 像素 of the pixel electrode X below. A: the pixel electrode Y is charged from the pre-charge to the charging period, the pixel electrode Y is not charged while the pixel electrode other than the non-pixel electrode X and Y is charged; and B: the charged pixel electrode Y and the X have the same polarity and The selection time points (charging time points) also approximate each other.

Page 24 1251801 V. INSTRUCTION DESCRIPTION (20) -- In the first embodiment, when the pre-charging method encounters the above-mentioned A and b cases, for example, when a mode is used, it is as shown in FIG. When the pixel electrode B11 is charged, the pixel electrode A12 (specific pixel electrode) is selected after the second stage. Here, the reason why the pixel electrode A 1 2 is not precharged will be described, which is similar to the pixel electrode All and has the same polarity when the pixel electrode A1 丨 is charged. Assuming that the pixel electrode A1 2 is precharged, as shown in FIG. 9, it will be necessary to select the scanning lines Gn + 3 and Gn + 4. At this time, the scanning lines Gn + 2 and Gn + 3 are simultaneously selected, and the pixel electrode C1 1 is driven in a reverse polarity manner. In particular, if the above pre-charging method is used, in the case where the pixel electrode located in the adjacent column and the same row is present, when a higher pixel electrode is charged, a lower pixel electrode will also be used. Being charged. Therefore, when the pixel electrode C 1 1 is precharged while the pixel electrode A1 2 is being charged at the pixel electrode A ’, the pixel electrode A 1 2 is again precharged to the potential to be charged with the reverse polarity. This will be related to the above situation _ 牴. Specifically, in order to precharge the pixel electrode A12 when the pixel electrode B1 is charged, as shown in the graph of Fig. 1, the scanning signals Gn + 3 〇ut and Gn + 4 out 上升 rise between B and 11 to time 12. Therefore, the scanning lines Gn + 3 and Gn + 4 that select the pixel electrode A 丨 2 are selected, and the first thin film transistor M1 and the second thin film transistor M 2 that provide the display signal to the pixel electrode A 12 are controlled to be activated. . Therefore, the same display signal as the display signal supplied to the pixel electrode B?1 is supplied from the signal line Dm to the pixel electrode M?, which has the potential Vbu. Therefore, the pixel electrode A12 is precharged with the same polarity as the pixel electrode βΐ2.

1251801 V. INSTRUCTIONS (21) It should be noted that in this case, the scanning line and the wall are out, therefore, the control is made up of the signal line (4) #素电极', 囡, t, batch, it, 知知线G η + 4 is selected as one of the first: the display signal of the second line Dm to the pixel electrode Μ 2 is raised, and the second half of the pancreatic transistor M3 is activated. Therefore, like | + D12 also has a potential nu. When the pixel electrode B12 is not more than 曰, it is also between t2 and time t3 (four), as shown in the figure - the household is *, any I = f G is not selected for pre-charging. Therefore, as shown in FIG. 7, 1 1 is maintained at the pixel electrode A 1 2盥D 1 2 . Bran, and gentleman ',

The φ pendulum of the line Gn + 3, however, as described above, the scanning MQ selectively activates the third thin film electric 连接 3 connected to the pixel electrode B1 2 , and therefore, like the φ φ to n, ... 1 The same as the CH. The prime electrode β1 2 is set to the potential Veil as the pixel voltage, H, as shown by the line of the three-bit period from the time t3 at which the halogen electrode DU is charged to the time t4, and the signal Gn + 4 is scanned. With 6 out of 5 out: ' Therefore, the scanning signal lines Gn + 4 and Gn + 5 are selected. The second and second thin film transistors M1, M2, and Μ3 are activated by the second and second display signals to the display electrodes of the halogen electrodes C12, D12, and B13. Because it匕, the gentry figure 八1 Γ1 9 Π1 0 ’, this display signal is provided by the signal line Dm to the pixel electrode B, UiZ, Th Rio

The pixel electrode 〇11 is gated by the 3' pixel electrodes C12, D12, and Bi3 with the pixel electrode = mdu. 0, the pixel electrode ci2 can be precharged with a potential of ^^u relative to the polarity. >&# = diode is precharged at the next step in which the pixel electrode is repeatedly charged in the same procedure. The page is hearty, the 疋' is so pre-charged, as shown in Figure 1, scanning

1251801

The line Gn + 4 is selected during the period from time t 〇 to time t1. 'Pixel electrode D 1 2 is driven and shown by the potential ^ } a 'scan line Gn + 5 at time t2 to time, as shown in FIG. The pixel electrode B13 is driven electrically. Out. Therefore, as shown in Figure 5, charge. In addition, the period as shown in Fig. t3 is selected. The channel is charged by the potential Veil. In addition, as shown in Fig. 10, the row and packet method represented by codes A and B in the precharged array are represented by a matrix. In Figure 10 and ΒΗ, Β 12, ... are driven separately. In addition, the columns represented by ^ 12, ... g(n + 2), ... represent scans ["η &, the items indicated by the matrix, w % 一々^十 U GU+^ G(n+1), G(n + 2)··· is selected at the time point when the pixel electrodes An, ai2, . . . , and B11, M2, . . . are driven. For example, the shadow of the first row of the first row of the matrix represents the scanning line G (n + 1) is selected at the time point of the pixel electrode A11.

At the time of driving, the letter level B displayed by each item in the matrix indicates that the pixel electrodes All, A12, . . . , and Bl 1, B12, ... are selected by selecting the scanning line G ( η + 1 ), One of G ( η + 2 )··· is driven by the corresponding project. For example, the first row in the first column of the matrix and the letter π A '' shown in the second column of the first row. Therefore, the pixel electrode A 1 1 shown is driven by selecting the scanning lines G(n + 1 ) and G(n + 2) while being driven while the pixel electrodes A 1 1 , A1 2, ... are driven. In addition, the letter "”π" shown in the project indicates whether the driving of the pixel electrode is used.

For pre-charging. In addition, the code shown in each item of the matrix or π - π indicates that each of the scan lines G (η ), G ( η+1 )··· corresponding to an item is associated with the corresponding scan.

Page 27 1251801

Each of the scan lines G(n + 1), G(n + 2V „ prime electrode (1), Μ 2, ..., and -, .., of the first low-order line of the line can be understood according to this matrix. When the pixel electrode selection scan line G(nH) is driven, the scan line 〇(^3) and the scan s = are driven, and the pixel electrode A 1 2 is charged at the second low order. In the precharge method, pay attention to the % scan letter +3 out and Gn + 4 out as shown in Fig. 1. Then, at time t1 to time 12, a time point) 'pixel electrode A丨2 (specific pixel electrode) By choosing

+ Temple fixed scan line) pre-charged. Thereafter, at least the scan line "+ 3 and h" before the scan line = +3 and Gn + 4 (a set of trace lines) is selected from the time t4 to the time t5 (the first time of the second time point) is selected. Any one of the + pixel electrodes is not selected when driving. The period refers to Gn + 3 and Gn + 4 when the pixel electrodes 八 12 and B12 (the second group of pixel electrodes) are driven 2 to charge the pixel electrode A1 2 In particular, different L numbers are output to the scanning lines G η + 3 and G η + 4 at the time of charging. Therefore, the pixel electrode a 1 2 will not be charged again until time t1 to time VII 2 After being precharged, it is charged during the period from time t4 to time t5, wherein the completion of the precharging described above satisfies the above case B. Other pixel electrodes in the same column such as the pixel electrodes C 1 2 and A 1 3 The same is true. Next, the control method of the gate driver 5 will be described below for charging.

The pixel electrode described above is precharged. FIG. 10, an indication of the offset signal (signal line) supplied to the scanning line G η + 1 to G η + 4 by the scanning signal G η + 1 to G η + 4 to the offset adjuster SR SD 1 and output control signals 0E1 to 0E3, and drive offset regulator SR

Page 28 1251801 V. INSTRUCTIONS (24) Timing diagram of the relationship between one of the timing signals DCPV. It should be noted that the position at which the potential rises during pre-charging between the scanning signals G η + 2 〇 u t and G η + 4 〇 u t in Fig. 10 - is also indicated by a solid line. As shown, the rise and fall of the offset pulse SD I is equal to four cycles of the timing signal DCPV. This offset pulse SDI is moved to the next offset adjuster S R while the timing signal DCPV rises in one cycle of the timing signal DCPV. Therefore, as shown, by providing the offset pulse SDI, the four scanning lines G, i.e., the scanning lines Gn + Ι to Gn + 4, can be simultaneously selected. It should be noted that one cycle of the timing signal DCPV is equal to one water.

Flat scan period. Therefore, the time length of the offset pulse SD I is four times the horizontal scanning period. It is conceivable that the four systems of the output control line 0E need to select four scanning lines Gn + 1 to Gn + 4 at the same time. However, in this first embodiment, as shown in Fig. 10, the output control lines 0E1 to 0E3 are utilized, and therefore, by the three systems of the control line 0E, the four scanning lines G can be simultaneously selected. Special Workplace This first embodiment employs a charging & pre-charging method in a matrix as shown in FIG. In the matrix shown in Figure 10, the code g' (η and g(n + 4), the scan lines Gn+1 and Gn + 4 are selected as shown in the column.

A and B are the same. Specifically, the turn-off control signal supplied to the buffer b to the scan line S^ and the output control signal supplied to the buffer b connected to the scan j1 can be regarded as the same signal. Similarly, the Gn + 4 scan lines Gn+2 and Gn + 5, Gn + 3 and Gn + 6··· buffers B, and the transfer-to-round control signals can be supplied separately. Therefore, this loss: two phases: the system is sufficient. Don't blame 0E's three

1251801 V. Inventive Description (25) As described above, in the first embodiment, when the conditions necessary for precharging are satisfied, charging and precharging of the pixel electrode having the multiplexed pixel structure can be completed, and therefore, liquid crystal The display device 1 is accurately driven. Further, in this precharging method, when the pixel electrode B 1 1 is charged, the pixel electrodes A 1 2 in different rows are precharged. As described above, among the pixel electrodes including the rows different from the pixel electrode to be charged, the pixel electrodes A and B satisfying the above conditions are selected. Therefore, the comparison selects that when the pixel electrodes located in the same row satisfy the above conditions A and B, the selection range is expanded. Therefore, the interval between the line in which the pixel electrode is charged and the pixel electrode being precharged at the same time can be narrowed. Therefore, the time interval from pre-charging to charging can be shortened to reduce the influence on the pixels of the non-display pixels by /Jn. Further, in the first embodiment, this has a time length of four cycles of the timing signal DCPV ( The offset pulse SD I of the quadruple horizontal scanning period can be controlled by three systems of the output control line OE. In particular, since the selection control of the four scanning lines can be performed by three systems of the same number of output control lines 0E, the selection control of the scanning lines G can be completed by the control signals with less scanning lines G being controlled at the same time. Therefore, the number of output control lines 0E can be reduced, thereby reducing costs and facilitating circuit design. It should be noted that although the array structure A is arranged as shown in the first embodiment of Fig. 3, the circuit structure of Fig. 12 can also be used instead. Second Embodiment Next, a second embodiment of the present invention will be described below.

Page 30 1251801 V. Inventive Description (26) Since the overall structure of the liquid crystal display device 1 in the second embodiment is similar to that of the first embodiment, the description thereof will be omitted herein, and the main description will be different from the first embodiment. At the office. The second embodiment is different from the first embodiment in the circuit structure of an array substrate and the pixel driving method. Figure 13 is a view showing the structure of the array substrate in the second embodiment of the present invention. As in the first embodiment, two pixels share one signal line Dm, and the second embodiment allows three pixels to share one signal line Dm.

Specifically, as shown in Fig. 13, in the array substrate of the liquid crystal display device 1 in the second embodiment, the signal line Dm is shared by three pixels, for example,

The pixel electrode A31 (pixel electrode D3l···), the pixel electrode B31 (pixel electrode E31···), and the pixel electrode C31 (pixel electrode F3l···). Next, a data of the signal line D m is supplied to the pixel electrode A31 when the scanning lines G η + 1 and G η + 3 are set to the selection potential. Further, a data potential of the signal line Dm is supplied to the pixel electrode Β3 1 when the scanning lines G η + 1 and G η + 2 are set to the selection potential. Further, a data potential of the signal line Dm is supplied to the pixel electrode C 3 1 when the scanning line Gn+1 is set to the selection potential. In order to perform the above-described actions, in the second embodiment, the first thin film transistor Μ 31 to the fifth thin film transistor Μ 35 of the switching element as set forth will be described below. Specifically, as shown in FIG. 13, for the first thin film transistor Μ 3 1, one of the source/germanium electrodes is connected to the pixel electrode A 3 1, and the other is connected to 1251801. 5. Description of the invention (27) To the signal line Dm. Further, the gate electrode of the first thin film transistor Μ 31 is connected to one of the source/germanium electrodes of the second thin film transistor Μ32. One of the source/germanium electrodes of the second thin film transistor Μ 3 2 is connected to the scanning line Gn + 3, and the other is connected to the gate electrode of the first thin film transistor M31. Therefore, the gate electrode of the first thin film transistor Μ 31 is connected to the scanning line G η + 3 via the second thin film transistor Μ 3 2 . Further, the gate electrode of the second thin film transistor μ 3 2 is connected to the scanning line GnH. Therefore, only when the two scan lines Gn+1 and

While Gn + 3 is simultaneously set to the selection potential, the first thin film transistor Μ: π is activated, and the potential of the signal line Dni is supplied to the pixel electrode Α3丨. This table

The second thin film transistor 32 is used to control a switching element of the opening/closing of the first thin film transistor M31. The line D: the other::: source/no electrode of the 连接 is connected to the signal line Dm, and the other is connected to the pixel electrode c3. The gate electrode of the transistor M33 is connected to the scanning line 6n + ι. For the fourth thin film transistor ^ J ^ to the signal line 〇, and the source of the other is connected to the fourth thin film transistor M34, the opening, the pole, the έ 4 to the pixel electrode B3 1 . In addition, one of the /th electrode. a source connected to the fifth thin film transistor M35

For the fifth thin film transistor M to the scanning line Gn + 2, and alternatively, one of the source/germanium electrodes is connected to the gate electrode. Further, the fourth film ray is connected to the film transistor M3 5 of the fourth thin film transistor Μ 3 4 and is connected to the scan line = the gate electrode of the body Μ 34 is connected to the scan line gn + via the gate electrode of the fifth thin M3 5 2. In addition, the fifth thin film transistor

Gn+Ι and Gn + 2 are set to be simultaneously. Therefore, only during the period of the two scanning lines & potential, the fourth thin film electro-crystal

1251801 V. DESCRIPTION OF THE INVENTION (28) The body M3 4 is activated, and the signal line indicates that the fifth thin film transistor M 3 5 is supplied to the pixel electrode B 3b ^β, Ι ^ /Μ η ^ ^ . A switching element for turning on/off the fourth thin film transistor Μ 34. Although the circuit structure of the first to the first array substrate has been described above, the following = crystal river 31 to Μ 35 are seen as Α 015 η 乂 将 will be explained by the pixel The circuit structure of the electrode two-night crystal display device 1. The early D~, the spring Dm provides a display signal, and the signal line Dm is a connection man #冬+pixel book A31 to C31. 4 inch t I Asf , , Λ""Α31" C31^ " ^

The crystal crucibles 32 are connected to each other... Bu, the second and second thin film wires, the second thin film transistor, the second: _2S; - η- a, a special film transistor Μ 3 2 gate electrode ίίί; 2: Γ ... η +1, and the second thin film (4) 汲 electrode is connected to the scanning line Gn+3 at the next stage. Here, the potential of the signal line Dm is supplied to the pixel electrode A31, and it is necessary to activate the first film.

Electric body M3 1. Further, the gate electrode of the first thin film transistor M3 1 is connected to one of the source/germanium electrodes of the second thin film transistor M3 2 . The gate electrode of the second thin film Diqing M32 is connected to the next step of the pixel electrodes A3丨 and B3 1 to the ^^0^ line Gn+1 2 and the other of the source/汲 electrodes is on the scan line Gn+Ι Next _ ^ is connected to the scan line Gn + 3. Therefore, the second thin film transistor must be activated from 3" 2 to activate the first thin film transistor M31. In order to activate the second thin film transistor MU, the scan line Gn+1 and the scan line Gn + 3 must be set to the next step in the next step: "Selection of electricity / 〇 $ - as described above" pixel electrode A31 is based on scanning from The scanning signal of the line Gn+1 and the scanning line Gn+1 is driven to receive the electric power from the signal line Dm.

Page 33 1251801 Five digits Description of the invention (29) For the pixel electrode B 3 1, the μ body Μ 3 5 are connected to each other. The fourth thin film transistor Μ 35 and the fifth thin film transistor Μ 35. Third, the transistor 34 is connected to the signal line Dm and the scanning line Gn+; 1, and the gate electrode of the fifth thin five-pole film transistor M3 5 is connected to the scanning line Gn + 2. In the source/germanium electrode of the crystal M35, the element B31 must be activated to provide a signal, the potential of the line ^ to the inter-electrode of the transistor M34: the membrane M34. Next, the fourth thin electric "-. 帛 five: film connection, to the fifth thin film transistor W source / no ^ 1, and the source / 汲 electrode special medium \ transistor M 3 5 of the question electrode is connected to the scan line Therefore, in order to start the fourth thin abdomen\another/connected to the gynecological line Gn + 2. Because of the crystal Zhao M35. In order to start ^ transistor M34, the fifth thin film electricity Gn + 2 must be activated. The crystal M35 'scan line Gn + m is below the B4 1 - the 4th order of the order. As described above, 'only when the pixel is at the selection potential, this line Gn + 1 and the next-order scan line Gn + 2 B3l 〇 This potential is supplied from the signal line Dm to the pixel electrode, and is connected to the pixel electrode C31 and connected to the third thin film electric crystal nozzle M3 3. The "pole" is connected to the scanning line Gn+Ι. Therefore, when the selection is called the day pixel electric sC3l is powered by the signal line 位

The magazine uses 俅$ to explain the pixel electrodes Α3 1 to C3 1 , such as γ 用 image, electrode D31 to F31, etc. The similar structure can be used, the timing signal of the liquid crystal display device 1 of the second embodiment, the timing chart of the offset pulse tracing signal, the sick pulse shown in FIG. 15 and the timing chart of the output control signal, as shown in FIG.

Face Page 34 1251801 V. INSTRUCTIONS (30) ☆ to m road map, and i ’ as shown in Figure 19 are like the second real:: drive matrix. In a horizontal scanning period of a screen: the pre-charging method, the I signal potential is written into the image, and the other pixel is maintained in a display I. The external display signal potential is initially written to

As shown in Fig. 14, the waveform of the scanning signal of the graph Gn out to the Gn + 5 line Gn to Gn + 5 is shown to be generated by the offset pulse of the scan | SR. In particular, this is +. In this case, when the offset register j or the portion indicated by the broken line is at the time point of the bit H = rising, the solid line is used, and at the time point 2 of the non-rising portion, the line G is selected. Out. It should be noted that the rise in the illustrations is not selected. The portion where the rise is not maintained by the pixel electrode is charged at the time of the line-of-line potential. Further, the display signal of the I f period is when the display signal potential is initially written to the pixel electrode: pre-[:J = and the timing of the selection control of the charging pixel electrode. % pixel private

Next, Dm(2) shown in Fig. 4 indicates a power & provided by the signal line Dm, which indicates that when the f-material signal is charged (4) Dm(2) shown here contains A polarity conversion. As will be described later, the pixel electrode A31 is set to have the same polarity as the pixel electrodes β3ι and c3i with the data signal Dm(2), and is driven with a polarity different from that of the pixel electrode D3 E3 and F31.

In addition, as shown in FIG. 15 is a timing chart, the scan signals Gn+1 out to Gn+1 out which are supplied to the scan lines Gn+i to Gn+5, and an offset pulse SD outputted to the offset register SR are displayed. I, an output signal corresponding to the above-mentioned scan signal, control signals 0E1 to 0E3, and a timing signal YfLK 1251801 of the drive offset register SR

The relationship between. It should be noted that the "precharge + square in out to Gn + 5 out, in Fig. fifteen" is shown in the scanning signal Gn+l. The portion where the potential rises is also set by the solid line. In order to drive the liquid crystal display, the SDI is set by the pulse of the control circuit 6. The pixel in \ is first, as shown in Figure 15 of the offset pulse. The τ unit 9 is output to the gate driver 5 (as shown in FIG. 15 , the three counting pulses s D 1 of the bias timing signal YCLK are caused by having a rising time to a falling timing signal - a long time A pulse Pm consists of a pulse P 2 composed of one letter. ^ One cycle is one long and one second

Equal to a horizontal scanning period of the screen s, one cycle of the timing signal YCLK has a total of four horizontal scanning period work. In particular, the offset pulse ςDI is a signal train having a length of three horizontal sweeps, wherein the first scan period is long, the second period is long, and has a water bucket therein. The interval is continued first; ^ Ρ 2 is between a horizontal scanning period 隋 ^ pulse Ρ 1 〇 The offset of the driver 5 is temporarily stored and the timing 栌祙ΥΓ丨 h must be earlier than 1 This offset pulse SD I, At the same time, in the system of timing signal yclk

Two to the next offset register SR. Therefore, by providing five times of the ear: the period of the trace is longer than the offset pulse SD丨, the offset pulse sd is present in the presence of two adjacent offset registers SR and an interval from a register The one-for-one spokes register SR continuously moves. Here, as shown in FIG. 15, by buffering the output control signals 0E1 to 0E3 to the buffers β adjacent to each other, the buffers connected to the five offset registers SR are simultaneously controlled, thus Five scan lines G can be selected and controlled simultaneously. In addition, here, since the buffer 3 is

Page 36 1251801 V. INSTRUCTIONS (32) The value of the rounded output control signal 0E is activated when 〇, and when it is 1, it turns off 'this scan signal G η + 1 〇ut to G η + 5 〇 Ut will be shown in the lower part of Figure 15. Next, a procedure for charging a pixel electrode will be described below.

As shown in FIG. 14, when the scanning signal Gn+1 oum Gn + 3 out is generated and supplied to the scanning lines Gn+1 to Gn+3 (first scanning line group), if the scanning signal G η + 1 is noted部分ut to G η + 3 〇ut The part of the day π ' indicated by the solid line is the time point when the % member indicates that the potential of k is written to the pixel electrode. Then, the scanning lines Gn + Ι and Gn + 3 are selected in the period from time t0 to time t1 (first time point). Therefore, as shown in Fig. 16, the first to third thin film electromorphs M3 1 to M3 3 are activated. Therefore, the potential Va21 of the signal line Dm having the pixel electrode A31 is supplied to the pixel electrodes A31, C31, and C32. Therefore, the potential Va21 of the pixel electrode A31 is determined. It should be noted that, as shown in Fig. 16, the selected scanning letter G is indicated in bold.

Meanwhile, in the period from the following time t1 to the time t2 (second time point), the potential supplied to the signal line Dm is charged to have the potential Va21 of the pixel electrode β31. Here, as shown in FIG. 14, the scanning lines "+丨 and Gn + 2 are selected, and therefore, as shown in FIG. 17, the second thin film transistor M32 is turned off. Further, the potential of the scanning line Gn + 3 ( The turn-off potential is supplied to the gate electrode of the first thin film transistor = 31, and thus the first thin film transistor M31 is turned off. Further, the third to fifth thin film transistors M33 to M35 are activated. Therefore, the potential Va21 is supplied to The pixel electrodes B31, C31, and F31. Therefore, the potential va21 of the pixel electrode B31 is determined. Therefore, the period from the following time t2 to time 13 (third time point)

Page 37 1251801 5. In the invention description (33), the potential of the signal line D m is charged to the potential V a 2 1 of the pixel electrode C 3 1 . Here, in the period from time 12 to time 13, as shown in Fig. 14, only the scanning line G η + 1 is set to the selection potential. Next, as shown in Fig. 18, the potential Vc21 of the signal line Dm is supplied to the pixel electrode C 3 1 ' via the third thin film transistor Μ 33, so that the potential V c 2 1 of the 5 pixel electrode C 3 1 is determined. It is to be noted that the period from time t 0 to time 13 corresponds to a horizontal scanning period (first horizontal scanning period). The pixel driving as described above is completed in this period, and therefore, the potential of the signal line Dm can be supplied to the pixel electrodes A31, B31, and C31 (first pixel electrode group) in time intervals.

After the scanning line Gn+1 is set to the non-selection potential, the polarity of the potential of the signal line Dm is reversed, and this potential is charged to a potential Vd2 1 to be supplied to the pixel electrode D31. By repeating the above procedure, the potential hunting of the pixel electrodes D31 to F 3 1 is determined by the time interval. In this case, the potentials Va21 to Vc 21 supplied to the pixel electrodes A3 1 to C31 are reversed to the potentials Vd21 to Vf 2 supplied to the pixel electrodes D31 to F 31. Therefore, the liquid crystal display device 1 is driven as A display device driven by a line conversion in which the polarity of each column is reversed. Next, a pre-charging method of one pixel will be described below.

As described above, the pixel electrode Y which is precharged while the pixel electrode X is being charged is desirably associated with A and B of the pixel electrode X below. A: the pixel electrode Y is charged from the precharge to the charging period, the pixel electrode Y is not charged while the pixel electrode other than the non-pixel electrode X and Y is charged; and B: the charged pixel electrode Y and the X have the same polarity and selection period

Page 38 1251801

'Inventive Notes (34) Gas Day Stagnation Point) are also similar to each other. Since the lth is precharged, in the second embodiment, if the electric conditions of the above conditions A and B are satisfied, for example, a mode is used, when the pixel electrode A31 is charged four-"electrode A3 2 After the second order, it is selected. In particular, as shown in the figure: Τ ^ dotted line, the period of time 7 〇 to time 1 (first time point) is selected ^ I t 戒 Gn + 3 (10) Caution Gn + 5 out potential is Therefore, the scan lines Gn + 3 and Gn + 5 (specific scan lines) of the Shiji A32 are selected.

The number of f彳^ ί is not. Further, the display signal to the pixel electrode A32 is controlled to be "2: The first and second thin film transistors M32 are activated. Therefore, the same display signal as the sinusoidal electrode A3 is supplied by the signal line Dm, == A32, which has electricity. Therefore, the pixel electrode A"" pixel electrode A31 is precharged with the same polarity. Thus, ί 5 f*, in this case, the 'scanning line Gn+5 is selected, and because the thin ΐΐΓ ΐΐΓ ΐΐΓ line Dm provides the display signal to the pixel electrode (3); Therefore, the 'pixel electrode (3) also has the potential t3, the period from the time U to the time ΐ2 and the time t2 to the time = ten:=: '::

Chuan. In &, since each pixel of the column has the same polarity at the pixel electrode. The period of the pixel electric time u to the day ^ t8 (the = horizontal sweep n four does not) in A32^

!2518〇1 V. Description of invention (35) During the period from t 5 to time t6 (the first time at the second time point), the scanning line

Gn+3 and Gn+5 are selected at the same time. Therefore, at least one of the & 'scanning signals G η + 3 〇 u t and G η + 5 〇 u t to which the pixel electrode A3 2 is charged is not selected. In particular, unlike charging, the signal is output to the scanning lines G η + 3 and G η + 5. Therefore, the pixel electrode A 3 2 is not precharged again during the precharge to charging period. Therefore, the precharge method of the second embodiment satisfies the above conditions A and B. Further, as described above, when the pixel electrodes D3 1 , A32 ··· are charged, the pixel electrodes D 3 2, A 3 3 are in the lower second The steps are pre-charged, so that the pre-charging that satisfies the above conditions A and B is completed. The method of precharging is shown in a matrix as shown in FIG. In the matrix of Fig. 19, the lines indicated by codes A, B and C respectively indicate the pixel electrode A 3 1 ,

A 3 2, ..., B 3 1, B3 2···, and C 3 1 , C3 2··· The time point when it is driven. Further, the columns G (n+1) and G(n + 2)··· are indicated by the code g ( η + 1 ) and g ( η + 2 ). In addition, the items in the matrix indicate whether or not the scanning lines G(n+1), G(n + 2)··· are on the pixel electrodes A31, A32, ..., B31, B32, ..., and C31 in the illustrated shadow. The time point at which C3 2 is driven is selected. For example, the shadow of the first row of the first column of the matrix indicates that the scanning line G (η + 1 ) is selected at the time point when the pixel electrode A 3 1 is driven. In addition, the letters A, B, and C displayed for each item in the matrix represent the pixel electrode A3, A3 2..... B3, B32, ..., and C3, C32, ... by selecting the scanning line G (n+) 1), one of G(n + 2)··· is driven by the project. For example, the first column in the first row of the matrix and the letter "”π" shown in the first row and the third column. Therefore, the pixel electrodes A31, A32, ... shown are by the same

Page 40 1251801 V. Description of invention (36)

The scanning lines G ( n + 1 ) and G ( η + 3 ) are selected to drive when the pixel electrodes A 1 1 , A 1 2, ... are driven. Further, the letter "pa" shown in the item indicates that the pixel electrodes A 3 1 , A 3 2, ... and others are selected by scanning lines G ( n + 1 ), G ( n + 2 ) corresponding to the item. Precharged. For example, the first row and the third column in the matrix and the letters in the first row and the fifth column "pA" show that the pixel electrodes A3 Y, A 3 2··· are precharged, and at the pixel electrode A3 1 , A3 2... is driven by the same day's drive by selecting the scan lines G ( η + 3 ) and G ( η + 5 ). Here, the "Α/ΡΑ" in the first row and the third column of the = array It is shown that the scanning line G(n + 3) is extracted to charge the pixel electrode A 3 1 and the pixel electrode A 3 2 is precharged at a time point corresponding to the item. As described above, in the second embodiment, the charging and precharging of the pixel electrode having the multiplexed pixel structure can be achieved when the pre-charging condition II, ^' is necessary. Therefore, the liquid crystal display device 1 can be accurately driven. ^ In addition, in the pre-charging method in the second embodiment, for example, during the period from time t 0 to time 11, the scanning lines G ( n + 丨 ) and g ( n + 3 ) are filled with X by the pixel. Electrode A 3 1, and scan lines g ( η + 3 ) and G ( η + 5 ) are exposed to precharge the pixel electrode while pixel electrode A 3 1 is being charged

Specifically, the selection control signal of the pixel electrode to be charged and the remote control line of the pixel electrode to be preamplified are the same. By using such a structure, the interval between the column in which the pixel electrode is charged and the column in which the pixel electrode is simultaneously precharged can be narrowed. Therefore, the time interval from pre-charging to charging can be shortened to reduce the influence of pixels of fresh non-display pixels. It should be noted that in the second embodiment described above, the pixel electrode B 3 1 can be selected from the scanning line g η + 2 by the pixel electrode A 3 1 when driven.

Page 41 1251801 V. Description of invention (37)

Va21 is charged. Therefore, the pixel electrode B31 can be charged before the actual driving. Therefore, the shortage of the writing pixel electrode B 3 1 can be avoided. THIRD EMBODIMENT Next, the configuration of the third embodiment, an array substrate, and the second embodiment and the second embodiment and the third embodiment will be described below. After that, it should be noted that the method, in which an image is used, the signal voltage is written and written. In Fig. 20, the offset pulse of the scanning line SR of the line Gn to Gn + 5 is generated by the dotted line or the portion indicated by the broken line. It is to be noted that the portion indicated is charged by the potential of the potential when the display signal potential is described as the third embodiment of the present invention. In the example, since the overall frame circuit configuration of the liquid crystal display device 1 and the circuit configuration of the gate driver 5 are similar, the description will be omitted here, and the main difference is.

The second embodiment is different in that a liquid crystal display device will describe the operation of the liquid crystal display device 1. Also in the third embodiment, a pre-charging element is used to maintain a pixel in a horizontal scanning period of one screen, and other display signal voltages are also initial.

The graph Gn out to Gn + 5 out represents the waveform output to the scan signal, which is passed to the offset register. In particular, when the rise of these figures is at the time point of each solid line, the relevant scanning line G is selected. At the time point of the division, the relevant scanning line G is not selected in the rising portion of these figures, and the pixel position of the horizontal scanning period is maintained by the solid line pixel electrode. In addition, the portion indicated by a broken line indicates that the pixel electrode is initially written to precharge the pixel electrode

Page 42 1251801 V. Description of the Invention (38) and the timing of the selection control of the charged pixel electrode. Further, Dm ( 2 ) as shown in Fig. 20 indicates the potential of a data signal supplied from the signal line Dm, which indicates the time point at which the data signal is charged. The data signal Dm(2) shown here contains a polarity transition. As will be described later, the pixel electrode A 3 1 is set to have the same polarity as the pixel electrodes E 3 1 and F 3 1 with the data signal Dm ( 2 ), and the pixel electrode B 3 1 is different from C 3 1 and D 3 1 . Polar drive. First, the charging _ ^ 〜 y will be described below, as shown in FIG. 20, when the scanning signals GnH out to Gn +3 out are generated and supplied to the scanning lines Gn+1 to Gn + 3 (first scanning line group) If the portion indicated by the solid line in the scanning signal Gn+1 out to Gn+3out is noted, that is, the time point at which the signal potential is written to the pixel electrode. Then, the HI lines Gn+l and Gn+3 are selected from the time t〇 to the time u (the first time point). For this reason, as shown in Fig. 20 - the first to third thin film electric eclips = 31 to M33 are activated. Therefore, the pixel electrode has a signal edge

/V : HM1 is supplied to be connected to the scanning Gn + 3 pixel electrodes 八31, C31, and via the third thin germanium transistor M33. ^ L potential va3m * fixed. It should be noted that the scanning signal G of the mouth of the pixel package is shown in bold. In addition, ^, the household is set to - positive potential. And in Fig. 21, 'here' potential Va31 is false and some of you fly 7^ pixel electrode A 31 or other potential Va3l is positive potential, after the system, also in Figure 20 - To Figure 1 + 丄: ... horse + table does not. The polarity of this is also α π , , 囷 , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , ,

Then, at time 11 to time 12 (the 12518801, the invention (39), the potential of the supply signal line Dm is charged to have the potential of the pixel electrode B3?

Vb3 1, and its polarity is reversed to a negative potential. Here, as shown in Fig. 20, the "scan lines Gn + l and Gn + 2 are selected" and the scanning line Gn + 3 is not selected. Therefore, as shown in Fig. 22, the second thin film transistor M 3 2 is turned off. Further, the potential of the scanning line Gn + 3 (off potential) is supplied to a gate electrode of the first thin film transistor M3, i, so that the first thin film transistor is turned off. Further, the second to fifth thin film transistors M 3 3 to Μ 3 5 are activated. Since the 1st bit is provided to the pixel electrode Β3, C3b and F3, the potential Vb3l of the pixel electrode B31 is determined.

Further, during the period of time 10 s α 曰曰 η / , the signal line D_potential ^ time point) is charged to the potential Vc31 of the pixel electrode C31. t this is from time t2 to time coffee period, as shown in Fig. 20, only the right deduction line Gn+1 is set to the selection potential. Next, as shown in Fig. 23, the signal line Dm has a potential Vc3, the level of the mountain is sufficient, and the β2 & 丨不' package m vcw,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, The potential Vc31 is determined. It should be noted that the period from time to time t3 corresponds to a horizontal period f, a horizontal scanning period). The pixel driving as described above is completed here and the potential of the itb' signal line Dm can be electrically charged by 1 pixel in time intervals, A31, B3, and C31 (first pixel electrode group). ,,to

Then, during the period from the following time u to the time t4, after the sweep is set to the non-selection potential, the polarity of the potential of the signal line ^ 3 Gn + 1 is changed, and the Jt bit is charged to the _ potential Vd3 丨 to be supplied to the pixel. The electrode has been D3. Next, as shown in Fig. 20, the scanning line Gn + ^ Gn + 4 is set to a potential. Therefore, as shown in Figure 24, connect to the scan line ^^ and select

1251801

G. DESCRIPTION OF THE INVENTION (40) The first and second thin film transistors M31 and M32 of η+4 are activated, and the potential Vd3i is supplied to the pixel electrode! Further, in this case, since the third thin film transistor M33 connected to the scanning lines Gn + 2 and Gn + 4 is activated, the potential V d 3 1 is supplied by the pixel electrodes F 3 丨 and F 3 2 . Further, during the period from the following time t4 to time t5, the scanning line Gn + 4 as shown in FIG. 20 is set to the non-selection potential, and the potential i ? of the signal line (4) is again inverted to positive ' and this potential Changed to be supplied to the pixel ==...e31. (4) As shown in Fig. 25, the scanning line center ί selects the potential, therefore, the connection to the scanning line "+ 2"

=Electricity: 曰: Body M35 is activated. In addition, the potential of the scanning line Gn + 3 is passive I:, the transistor M34, (5), the fourth thin film transistor M34 is turned on. ^ This potential Ve31 is supplied to the pixel electrode. In addition, here, the Thunder connection is activated. The third thin film transistor M33 to ^ + ^ Gn + 4 is supplied to the pixel electrodes F31 and c32 by the bit Ve31. The dry, Hi is during the period from the time t5 to the time t6, as shown in Fig. 20: i + 3f is set to a non-selection potential, and the potential of the signal line is changed to the potential V f 3 1 supplied to the pixel electrode F 3 1 . Next, Fig. 2: 1 is due to the scan line Gn+2 Is set to the selection potential, such as

And, if not, the third thin film transistor M3 3 connected to Gn + 2 is turned on, and the bit V f 3 1 is supplied to the pixel electrode ρ 3 1 . During the period of the second power: vd3: - V water two scan cycle (time t3 to time "supply to f + Λ Dqi ^ Bu Vf 31 can be extracted in one time interval I electrode D31, E31, and F31 The core is repeated by the above procedure, including the pixels of the pixel electrodes A 3 2 to c 3 2

IH

Page 45 1251801 V. INSTRUCTIONS (41) The potential of the electrode is determined by the time interval. 4. Therefore, the potential of each pixel at the potentials Va31 to Vc31 of the potential electrodes V31 to (3) supplied to the pixel electrode A31 is reversed, and is supplied to the potential Vd31 provided to the pixel electrode D31. = Prime, shift... The potential of Ve3 & Vf31 is reversed: (1, and == 乂, the polarity of the pixel electrodes A31 and D31 are opposite to each other. The polarity of the pixel B31 and C31 and the polarity of the pixel electrodes E31 and F31 are also Everything is reversed: this 'one-line conversion drive is completed... every pole of the column

Next, a pre-charging method of one pixel will be described below. In this third embodiment, for example, the pixel electrode D31 (specific pixel electrode) whose pixel electrode β3ι is charged with the first order is selected. In particular, as shown by the dotted line in Fig. 20, in time " to two,, in addition to the scanning signal Gn + 1 〇um Gn + 2 〇, the power of the scanning letter is also increased..., as shown in Fig. 2 Twelve, select the line D1 of the line D1 of the line Gn+2 and Gn+4 (specific scan line, second scan, a flute selection, " control provided to the pixel electricity, although the D1 page The first film of the signal, the thin film transistors M3 1 and M32, is activated. Therefore, the display signal identical to the display signal for providing the coffee is supplied to the signal line =

With =^^ pole 31, which has a potential Vb31. Therefore, the pixel electrode d31 / and the pixel electrode B 3 1 are precharged in the same polarity. It is to be noted that, in this case, the scanning line Gn + 4 is selected because the third film transistor M33 which supplies the display signal to the pixel electrode F32 by the control signal line Dm is activated. Therefore, the potential puff 31 is also provided to like winter

Page 46 1251801 V. INSTRUCTIONS (42) Electrode F 3 2 .

Thereafter, during the period from time 12 to time 13, any of the scanning lines G is not selected for pre-charging. Therefore, as shown in Fig. 23, the potential Vb3 1 is maintained at the pixel electrode D 3 1 . Here, since the driving polarity of the pixels of each column is reversed, the potential which is actually charged to the pixel electrode D 3 1 is turned by the pixel electrode A 3 1 . Further, since the pixel electrode A 3 1 and the pixel electrode B 3 1 are driven while the polarities are turned toward each other, the potential Vb3 1 precharged to the pixel electrode D 3 1 and the potential actually charged to the pixel electrode D31 have the same polarity. Thereafter, during the period from time t3 to time t6 (second horizontal scanning period), when the pixel electrodes A32, B32, and C32 (second pixel electrode group) are simultaneously driven, from time t3 to time t4 (second In the period of the first time of the time point, the scanning lines Gn + 2 and Gn + 4 are simultaneously selected, and the pixel electrode D31 is charged. Therefore, the pixel electrode D 3 1 is not precharged again during the precharge to charging period. Further, the same is true when the pixel electrode A 3 2 is precharged. Therefore, the precharge method of this third embodiment satisfies the following two conditions A and B.

A: the pixel electrode Y is precharged to the charging period, the pixel electrode Y is not precharged while the pixel electrode other than the non-pixel electrode X and Y is charged; and B: the charged pixel electrode Y and the X have the same polarity And the selection time points (charging time points) are also similar to each other. This pre-charging method is shown in the matrix of Figure 27. In the matrix of Fig. 27, the lines indicated by codes A, B, and C indicate the time points at which the pixel electrodes A 3 1 , B 3 1 , and C 3 1 are driven, respectively. In addition, with the code g ( η + 1 ),

ΗΒ P.47 1251801 V OBJECT DESCRIPTION OF THE INVENTION (43) g(n + 2)... indicates that the scanning lines G(n+1), G(n + 2)··· are indicated. The items in the matrix indicate that G(n + 1), G(n + 2)... are selected at the pixel electrodes A3, B31, and C31 to be driven by the shadow shown. For example, the time table of the first row of the first column of the matrix does not scan the line G (n + 丨) at the time when the pixel electrode A 3 丨 is driven to select a shadow shadow. In addition, each item in the matrix The letters a and $ are displayed. = pixel electrodes A31, B31, and (:31 are driven by the item corresponding to one of the selected scan lines G (n+i^C table/n + 2)···. For example, in the matrix, the first column of the row And the letter "A" shown in the third column of the first row. Therefore, the first ~

The pixel electrode A31 is driven by selecting the scanning lines G(n+1) and G(n + 3) while the pixel electrodes A3 1 , A3 2, ... 7K are simultaneously moved. Further, the term "breaking drive" PD" indicates that the pixel electrode D31 is precharged by selecting the corresponding ψ line G(nH), G(n+2) of the corresponding V. For example, the letter " array in the second column of the second row and the fourth column of the second row is pre-charged, and the scanning electrode G(n + 2) is selected by the pixel electrode along with the core of the driving. ) and G(n + 4) to drive it. • ‘ 仇 ΪΪ ΪΪ 矩阵 矩阵 矩阵 矩阵 矩阵 ΪΪ ’ ’ ’ ’ ’ ’ ’ ’ ’ ’ ’ ’ ’ 像素 像素 像素 像素 像素 像素 像素 像素 像素 像素 像素 像素 像素 像素 像素 像素 像素 像素 像素 像素

The line i ? G - the scan line group (Gn + ^ Gn + 3) and the completion of the charge Λ and , and (〇 11 + 1 and Gn + 2) are the same. What is satisfied: in the third embodiment, when the necessary condition of pre-charging is completed, B, charging and pre-charging of the pixel electrode having the multiplexed pixel structure can be performed, and thus the liquid crystal display device 1 can be accurately drive. Further, in this third embodiment, for example, the pixel electrode D31

1251801 V. DESCRIPTION OF THE INVENTION (44) When the pixel electrode B31 is charged, it is precharged when it is charged by the second or second person. On this side: the prime electrode A 3 2 is charged in the pixel & different rows of pixels. In the pixel + less: the pixel electrode is selected. The pixel electrode of conditional level B of 1 foot ^ 又 is selected to be located only in the same row, and its pre-charged 22 is in the interval between the occurrence of the pixel electrode being charged and the range between the pre-charging and the pixel electrode being simultaneously : The time interval can be shortened to :::, from pre-charging to charging. 4, the effect of pixels that are not pixels is subtracted to charge the pixel-electrode β3. In the wide example, the two scanning lines G (Gn + l and Gn + 2) are used to charge the pixel electrode B31 as If, G(Gn + 2 and Gn + 4) is selected 2 i to use this structure, its Μ / pixel electrode im. The pixel electrode that has been charged as above is the same as the tangent line. Therefore, the interval between them can be narrowed down. Therefore, the effect of the above-mentioned pixel electrode is made more conspicuous. Fourth embodiment

ΪΪSecond Si present: The fourth embodiment. The circuit name of the array substrate is: J crystal, and the overall frame of the device 1 is omitted. This is similar to the first embodiment: the embodiment is different. Here, the differences are exemplified. ...and "same statement" and the main description is different from the first embodiment. The fourth embodiment differs from the first embodiment in that - liquid crystal display device

1251801 V. INSTRUCTIONS (45) The action of setting 1. Hereinafter, the operation of the liquid crystal display device 1 will be described.

As shown in Fig. 28, the graphs Gn out to Gn + 7 ou t represent the waveforms of the scanning signals output to the scanning lines Gn to Gn + 7, which are generated by the offset pulses transmitted to the offset register SR. Specifically, the relevant scanning line G is selected at the time point of the portion indicated by each solid line or broken line at the rise of these figures. Further, at the time point of the non-rising portion, the relevant scanning line G is not selected. It is to be noted that, in the rising portion of these figures, the portion indicated by the solid line indicates the time point at which the display signal potential of the horizontal scanning period is maintained by the pixel electrode. Further, the portion indicated by a broken line indicates a point in time at which the display signal potential is initially written to the pixel electrode to compensate for the shortage of the display signal potential before the display signal potential is written. In particular, the portion indicated by the dashed line indicates the time point of pre-charging. Further, Dm (1) shown in Fig. 28 indicates the potential of a data signal supplied from the signal line Dm, which indicates the time point at which the data signal is charged. Here, the displayed data signal Dm(1) contains a polarity transition. As will be explained below, all of the pixel electrodes A 1 1 , B 1 1 , C 1 1 , and D 1 1 are driven with the same polarity as the data signal D m ( 1 ).

Next, the operation of the liquid crystal display device 1 of the fourth embodiment will be described below, with reference to the timing chart of the scanning signal as shown in FIG. 28, the offset pulse and the output signal as shown in FIG. Figure 30 to Figure 34 shows the circuit diagram. It should be noted that, as in the fourth embodiment, a precharge method is used in which other display signal potentials are also initially written before a display signal potential maintained by the pixel in one horizontal scanning period of one screen is written to the pixel.

_ _ Page 50 Ϊ 251801 V. Invention Description (46) In addition, as shown in Figure 29, the scanning signals Gn+1 out and Gn + 4 out are supplied to the scanning lines Gn+1 to Gn + 4, and the output is biased. Timing of the relationship between an offset pulse (signal line) SD I of the shifter 'SR and the output control signals 0E1 to 0E3 corresponding to the above-described scan signal, and the timing signal DCPV of one of the drive offset adjusters SR Figure. It should be noted that in Fig. 29, in the scanning signals Gn+1 out to Gn +4 out, the portion of the potential at the time of precharging is also indicated by a solid line.

In order to drive the pixels of the liquid crystal display device, first, the offset pulse is output from the pulse generating unit 9 of the control circuit 6 to the gate driver 5 (as shown in FIG. 21, the second pulse group is equal to the time when the timing signal falls, In the timing signal period, in particular, the time-long pulse P2 of the long-term signal period is twice as high as P1 ° when the gate drive signal YCLK is up to the next offset, and the offset pulse SDI is first Pulsed disk solution 1 a pulse rises to a long time of falling # & 4 a cycle, the second pulse rises specifically for the timing of the letter to

One of _: cycle. In the offset pulse s two \ right; / screen a horizontal scan of the week number column. ΪΓ Λ a total of six times the horizontal scanning period, and has a -# level ^ ρ 1 with twice the horizontal scanning horizontal scanning of the circumferential period of the second interval of the second interval - the interval of the indirect continuation of the -pulse 5 靳 left One liter at the same time %\7^ in the 'offset pulse %sdi in the register SR. In a cycle of YCLK, moving the port, the fine is provided by six times horizontal scanning.

1251801 V. Inventive Note (47) The time is up to the offset pulse SD I, the offset pulse SD I is in the two adjacent offset registers SR and the two offset registers separated from the two registers by one interval When it exists, it moves continuously. Here, by providing the output control signals OE1 to OE3 shown in FIG. 29 to the buffers b adjacent to each other, the buffer B connected to the six offset registers SR is simultaneously controlled, and thus Six scan lines g can be selected and controlled simultaneously. Further, here, since the value of the output control signal 0E of the buffer 3 at the input is 〇, it can be activated, and when the value is 1, it is turned off. This scanning signal G η + 1 〇 u t to G η + 4 〇 u t will be as shown in the lower part of Fig. 29.

Next, a procedure of charging a pixel electrode will be described.

As shown in Fig. 28, when the scanning signals Gn+i out and Gn + 2 out are generated and supplied to the scanning lines Gn+丨 and Gn + 2 (first scanning line group), if the scanning signal Gn + 1 out is noted The portion indicated by the solid line in Gn + 2 out, that is, the time point at which the signal potential is written to the pixel electrode, and the period of the sweeping line Gn+Ι and Gn + 2 between time t0 and time t1 (first At the time point), ^ is selected. Therefore, as shown in FIG. thirty, the first to third thin film transistors g to M3 are activated. Therefore, the potential Va4 1 supplied from the signal line Dm to the pixel electrode a is supplied to the pixel electrodes a ! i, b 1 1 , and D 1 1 . Therefore, the potential Va41 like the ^ electrode All is determined. It should be noted that, as shown in Fig. 30, the selected scanning lines G η + 1 and G η + 2 are shown in bold. In the case of ^, in the period from the following time t1 to the time t2 (second time point), the scanning line Gn + 2 is set to the non-selection potential, and only the sweep =. Therefore, as shown in Figure 30 - only the third film is electrically active. Here, the potential supplied from the signal line Dm is changed to be supplied to ^

1251801 V. DESCRIPTION OF THE INVENTION (48) The potential Vb41 of the element electrode B11 is such that the potential U4 of the potential U4 determines the potential of the pixel electrode B1?. The period from two / to pixel electrical time t2 corresponds to a horizontal scanning period = 'bearing _, time tO to period). The pixel as described above is driven by this period (= a horizontal selection week)

The potential of Dm can be supplied to the image area by the time interval [hence, the signal line electrode group). The pixel electrodes AU and B11 (the first image is set to the non-selection # potential is changed to the electric power provided by the pixel electrode C11, and the signal line is as shown here, as shown in FIG. ; Λ / . 41. With _ -, the scan line _ and the second two - are selected. Therefore, as shown in Fig. 30:: Dt2 to the daytime m3, the potential Vc41 of the element electrode ci 1 is supplied to the image The 2' line of the butadiene electrode = the supply image B12, and the potential of the pixel electrode cu is determined. Further, in the period from the following time t3 to when the time is not selected + # π Ί t4, the line Gn + 3 is known. As shown in Figure 33::, and only the scan line Gn + 2 is selected. Therefore, the pole follows (four) electricity: 'two =? 峨 supply potential is changed to... pole Dl 1 to determine like f electricity 11, potential Vd41 The potential yd4 provided to the pixel electric 电极 electrode Dl 1 is further, on the day 4 + d

The polarity of Dm (1 ) is reversed. After that, as shown in Figure 28, the scan signal is connected to 'Time Gate +1'

After Vd42 is similar to I = , the potentials Va42, Vb42, Vc42, and the next order are supplied to the pixel electrodes ΑΠ, BU, Cn, and D11 provided to the pixel electrodes j12, B12, C12, and D12. Thereafter, the polarity is reversed for every two columns provided in its 1251801 V, invention description (49). Therefore, the liquid crystal display device inversion drive) is driven by two lines (tw〇_line is reversed, and the device is not driven, wherein the polarity of each of the two columns is followed by a description of the pixel in the fourth embodiment. In the case of a pixel electrode A 〖3 (specific two, when the pixel electrode A is 充电 is charged fourth order is selected to satisfy the above-mentioned 侪 Du ', the package pole) under the pixel electrode A 1 1 in particular, as shown in the figure The pixel electrode of T == and β. The electric power with Gn + 6 out is at time ff, no, the scanning signal Gn + 5 out. As shown in Fig. 30, the period of selection 111 is raised. + 6 (the second scan line group, the scan line Gn + _ of the specific μ electrode M3 is supplied to the pixel electrode A 丨 3 and the group 2 is deciphered and controlled, and the control bodies Μ 1 and Μ 2 are activated. Therefore, the display signals of the first and second thin film electro-crystal numbers are the same as the display signal potential Va41 of the :::: JA i ! is provided. Therefore, the pixel electrodes AU have the same polarity. Precharged, electrode A 1 3 with pixel electrode a 1 1

It should be noted that, in this case, the control is supplied from the signal line Dm to the pixel: the field line Gn + 5 is selected because the three-film transistor M3 is activated. Further, in addition to the display signal of H1 3, the control is supplied from the signal line Dm to the pixel strip line Gn + Y, since the three thin film transistors Μ 3 are activated. The pixel electrodes Β1 3 and D 1 3 of the display signal due to &,: , M 3 . A a 1 1 is also supplied to these - thereafter, during the time U to the time gamma period, as shown in Fig. No, any scanning line G is not selected for precharging. Therefore, as shown in Figure 10

125180!, invention description (50) The indication is that the position V a 4 1 is still maintained at the pixel electrodes a丨3, b 1 3, and D1 3.

For example, the scanning signal Gn + 6 (10) is read by the Gn + 7 control at the time t 2 to the time period 13 when the pixel electrode c 1 1 is charged. "The bit rises, therefore, the scanning signal lines Gn + 6 and Gn + M are selected and the second fish 2, and the display tf of the display signals supplied to the pixel electrodes C 1 3 and D 1 3 is controlled, the thin film transistors ^ and M2 Then, as shown in Fig. 32, the image is supplied from the signal line Dm to the pixel electrode C13, and therefore, the potential Vc41 of the same potential of ^3.^\U3 is supplied to the potential of the pixel electrode. The pixel electrode C1 3 can be selected with the same polarity as the pixel electrode C11, and because: the batch Γ ί ί is 'in this case, the scanning line Gn + 6 is the signal of the first - I ^ φ s ^ line Dm The display provided to the pixel electrode D1 3 is supplied to the pixel electrode D1 3. The potential Vc41 is also referred to as a period of time •, and any scan is not selected to be ^, As shown in Figure 28: The pixel electrodes A13 and B13 maintain the charge: bit. v Therefore, as shown in Figure 3, η C13!^D13 maintains this potential Vc4i. Hold this potential va4l, and the pixel is charged.

Similar to the above procedure, the pre-charging of the pixel electrode is completed. "The next-order pair of electrodes is charged" as described above, it is desirable to: - the pre-charged one pixel electrode γ is electrically connected to the pixel, and the pole A is charged in two. The human has the following A and B A: pixel electrode Y is precharged to charge J, pixel electrode

1251801 一---^五非以,发明说明(51) The pixel electrode X and the pixel electrode other than Y are charged without being pre-charged; and, point B ··the charged pixel electrode floor has the same polarity and The selection time (charging time point) also approximates each other. t For example, the pre-charging method of the fourth embodiment, for example, pay attention to the scanning signals Gn+5 〇1^ and Gn+6 〇ut as shown in Fig. 28. In the period of time 辛0i m and one time point), the pixel electrode A13 (specific image tt is pre-charged at line Gn+6 (specific scan line), t6(, /^; VnT-G:T:: : ; ^ ^ ^ ^ A12 and B12 (second pixel electricity: between): During the period, the prime electrode M3 is charged at time t5 to time t^2 to charge other d·! lines with at least +5 and Gn + 6 The cup is not selected when it is driven by its prime electrode. In particular, the signal of the electrodes A and 13 is turned to the scanning lines Gn + 5 and Gn + 6. Because: Shoude does not break again. Pre-charging until the time pixel is 匕: during the period from time t5 to time (10), the pre-electrical charge of the susceptor electrode 7 is completed by: the above condition A. In particular, the sputum is electrically charged to the charged During the period, the pixel electrode is not in/or the other pixel electrodes of γ are charged while being precharged. θ ί is not like the "pixel electrode Cl 3 and the Α1 3 are in the same row of silly 4 + 4 甩. For its construction. The pixel electrode of 4 D is also the same as the picture of the figure of the thirty-fourth. Chen Xian 1251801 V. Description of the invention (52) The time point when BU' and C11 are driven. In addition, the code g(n+1), g(n + 2) The column shown represents the scanning lines G(n+1), G(n + 2). In addition, the items in the matrix indicate whether or not the scanning lines G(n + 1), G(n) are indicated by the dark shadows shown. + 2) ... is selected at the time point when the pixel electrodes AU, Bn are driven. For example, the shadow of the first row of the first column of the matrix represents the sweeping line G ( η + 1 ) at the pixel electrode a 3 1 is selected when the time is driven.

Further, the letter level B displayed by each item in the matrix indicates that the prime electrodes AH, B11, ... are driven by a corresponding one of ^, G(n + 2) ... by selecting a scanning line. For example, the first column in the first row of the matrix is the letter "A" shown in the third column of the first row. Therefore, the pixel electrode shown = is driven by selecting the scanning line G ( n + 1 ) G(n + 2) while being driven while the pixel electrode A is being driven. In addition, the letter "pA" shown in the project indicates that the hair electrodes A 1 1 , A 1 2... are selected by the scanning line corresponding to this item, G ( η + 1 ) ^ ( η + 2 ) By pre-charging. For example, the first five columns in the matrix and the letters in the first predetermined sixth column, ρ Α , show that any pixel electrode Α 1 Α 12 ... (here, pixel electrode Α 13) is pre-charged And while the pixel electrode AU is being driven, 'by driving the scanning line G (n + 5mG(n + 6)).

According to this matrix, it can be seen that the pre-charging of a pixel electrode (ai3) is completed when the pixel electrode (A1 1 ) is charged at the ^ row t, and is supplied for completion. The known line group (Gn + _ 6η+6) is different from the scan line group (Gn+Ι and Gn + 2) for charging. flowing of water? ^上=Ϊ々 In this fourth embodiment, when the pre-charging necessary condition, the charging and pre-charging of the pixel electrode of the pixel structure can be

1251801 V. INSTRUCTIONS (53) Done. Therefore, the liquid crystal display device 1 can be accurately driven. Fifth Embodiment Next, a fifth embodiment of the present invention will be described below. In the fifth embodiment, since the overall structure of the liquid crystal display device 1 and the circuit structure of an array substrate are similar to those of the first embodiment, the same description as the first embodiment will be omitted herein, and the main description will be omitted. The difference from the first embodiment.

The fifth embodiment differs from the first embodiment in the configuration of a control circuit 6' and a gate driver 5' and the operation of a liquid crystal display device 1. First, the control circuit 6' and the gate driver 5' in the fifth embodiment will be described below with reference to Fig. 35.

The control circuit 6' of the fifth embodiment is different from the control circuit 6 of the first embodiment in that an output start/stop control unit 8' provided by the control circuit 6' outputs an output control signal 0E to the output control lines 0E1 and 0E2. The two systems. The two systems of the output control lines 〇E1 and OE2 are distributed and connected to each of the two buffers B adjacent to each other in the gate driver 5'. Therefore, the output start/stop control unit 8' outputs output control signals different from each other to these output control lines OE1 and OE2. Therefore, it is enabled to independently control two buffers B adjacent to each other. Next, the following will be described with reference to the timing diagrams of FIGS. 36 and 37 and the circuit diagrams of FIG. 38 to FIG. The operation of the liquid crystal display device 1 of the embodiment. It should be noted that in this fifth embodiment, the pre-charging of the pixels is not

η Page 58 1251801 V. INSTRUCTIONS (54) Completion. In Fig. 26, the graphs Gn out to Gn + 3 out represent the waveforms of the scanning signals output to the scanning lines Gn to Gn + 3, which are generated by the offset pulses transmitted to the offset register SR. In particular, when the rise of these figures is at the time point of the portion indicated by each solid line or broken line, the relevant scan line is selected. Moreover, at the time point of the non-rising portion, the relevant scanning line G is not represented by t, and Dm(2) shown in FIG. 36 indicates a potential of a poor signal supplied from the signal line D? Indicates the point in time at which the data signal is being charged. The Dm shown here contains a change in polarity. As will be described later, with respect to the data signal Dm(2), the pixel electrode All is driven with the same polarity as the pixel electrode B11 and having a polarity different from that of the pixel electrodes C1 and D1. The sequence diagram is displayed to the scan line. In addition, as shown in Figure 37.

Gn + 1 to Gn + 3 scan signal Gn + 1 0 to Gn + 3 〇ut, an offset pulse SDI of the input and value register SR, corresponding to the above-mentioned sweep control signals 〇E1 and 0E2 The relationship between the YCLK and the drive offset offset register. j leaf k k the early element 9 output to the gate driver In order to drive the liquid crystal display device, S D I is generated by the pulse of the control circuit 6 ' (as shown in Fig. 37). As shown in Figure 37, the offset pulse SDI is the two cycles of the falling timing signal YCLK, and there is a cycle from rising to the next YCLK equal to the screen's water =:. Here, the timing signal shift pulse SDI has two horizontal sweeps "钿 cycles. In particular, the duration of the cycle is long. In the offset temporary storage unit 12 of the driver 5', the offset pulse SD!, while rising with the timing signal YCLK, is tmt in the timing signal γακ Offset register sr. Therefore, by providing two sections of the road. The time of the day 乜唬 γ c L K is long until the offset pulse s D 丨 , and the offset pulse SM continuously moves when it exists in the two adjacent offset registers SR. Therefore, as shown in Fig. 17, by providing the output control signal 盥〇1盥〇E2 °° ^ 5 -r ^ ' Therefore, the two scanning lines G can be selected and controlled at the same time.

The specific action of the gate driver 5 will be described. It should be noted that the output control signal 〇E1 shown in Fig. 37 is supplied to Gn+1, Gn + 3··· every _ 蛉λ # p 1 Na, and the spring signal _ is supplied to the connecting wheel end; ^Γ冲,β. At the same time, the buffer of the control terminal is output. Connect to each line of the field line _, Gn + 4... (10) at the time point of the time ^, offset pulse SR. Here, each offset register at time t; ^ line ^ and 甘(4) 2 is in the middle of the scan lines Gn + 1 and Gn + 2 $ ‘ ^ &

With , , 〇 " value, and the connection output control signals 〇E1 and B2 B are activated. Because ί =, the buffered data at the input of Gn + 2 is used as the sweep +, and the offset pulses SDI and Gn + 2 are stored. Therefore: m = ^Gn + 2 〇Ut output to scan line _ and Gn+2 can be selected:::〇 to time ^ period, scan line; the following %· between 11 and time 12 period, output control letter 11111

Page 60 1251801

The value of the number (10) 1 is set to " ο", but the value of the output control signal 〇 E2 is set to 1 port /, and the buffer connected to the wheel end of the scanning line Gn + 1 is activated. Therefore, only the data of the offset pulse SDI appearing in the offset temporary boundary SR corresponding to the scanning line Gn+Ι is output to the scanning line Gn+b, thus sweeping. The trace signals Gn + 1 out and Gn + 2 out become as shown in Fig. 37, and only the scan line G η + 1 is selected.

Further, in the following time interval between the day and the second day, the offset register SR and the timing signal YCLK are simultaneously activated, and therefore, the offset pulse SDI is moved to be connected to the scanning lines Gn + 2 and Gn + 3 Each offset register SR. Here, in the period from day to day t 2 to time 13, since the output control signals 〇E2 and 〇E1 supplied to the buffers B corresponding to the sweep lines Gn + 2 and Gn + 3 have,

The value, the buffer β connected to the output of the scanning line Gn + _ Gn + 3 is activated. Therefore, the data of the offset pulse SM appearing in the offset register SR is output as the scanning signal Gn + 2 (10) with Gn + 3 out to the scanning lines Gn + 2 and Gn + 3. Therefore, in the period from time t2 to time ΐ3, the scanning lines ^^ and Gn + 3 can be selected and controlled. Further, during the period from the time t3 to the time, the value of the output control signal OE2 is set to "〇", but the value of the output control signal 0E1 is set to "丨". Therefore, only the buffer 连接 connected to the output terminal of the scanning line Gn + 2 is activated. Therefore, only the data of the offset pulse SDI appearing in the offset register SR corresponding to the scanning line Gn + 2 is output to the scanning line Gn + 2. Therefore, the scanning signal Gn + 2(10) is carefully changed to Gn + 3 out as shown in Fig. 37, and therefore only the scanning line Gn + 2 is selected. - Next, a driving method of one pixel corresponding to the operation of the gate driver 5 will be described below. μ

Page 61 1251801 V. Description of invention (57) As shown in Figures 36 and 37, when the scanning signal Gn+i 〇117

When Gn + 2 out is generated, attention is paid to the scanning signals GnH 〇ut and Gn + 2 o u t 'the scanning lines G η + 1 and G η + 2 are selected from time t 0 to time 11. Therefore, as shown in Fig. 38, the first thin film transistor M丨 to the third thin film transistor M3 are activated. Therefore, a potential Val 1 applied from the signal line Dm to the pixel electrode A1 被 is supplied to the pixel electrodes A1 }, B1 1 , and D11. Therefore, the potential Vail of the pixel electrode All is determined. It should be noted that the selection of the scanning lines Gn+Ι and Gn + 2 in Fig. 38 is indicated by a bold line. Meanwhile, the scanning line Gn + 2 is set from time t1 to time seven 2 as follows

It is not possible to select a potential, and only the scanning line Gn+1 is selected. Therefore, as shown in Fig. 29, only the third thin film transistor is activated. Here, the potential supplied from the part number line Dm is changed to the potential vbii/== applied to the pixel electrode Bu, and the potential vbii is supplied to the pixel electrode β11 to determine the pixel electrode Bu a , which is described above, the 仏 line Dm The potential is supplied to the pixel electrodes A 1 1 and B 1 1 in time intervals. When the known line Gn + 1 is set to the non-selection potential, as shown in Fig. 36, the polarity of the potential of ΪΜ is reversed, and this potential is changed to the potential VcU supplied to the pixel electrode C11. Right in ltb, 士α[5Ι二 4-二-rK 1

Γη , q — 十/, 中 'If you notice the scanning signal Gn + 2 out盥^ because 0Γ' line 6n + 2 and Gn + 3 are selected from time t3 to time ΐ4 ^ ci 1 potential is 1; V The signal electrodes are supplied to the pixel electrodes, such as the f-electrode electrodes C11, D11, and Β12. The potential Veil of the CU electrode is determined. In the period between 14 and 15 during the following day, the scanning line Gn +3

Page 62 1251801 V. Description of the invention (58) is set to a non-selection potential, and only the scanning line G η + 2 is selected. Therefore, as shown in FIG. 41, the potential supplied from the signal line Dm is changed to the potential V d 1 1 supplied to the pixel electrode D 1 1 , and therefore, the potential V d 1 1 is supplied to the pixel electrode D 1 1 to The potential of the pixel electrode D 1 1 is determined. In this case, the potentials Va 1 1 and Vbl 1 supplied to the pixel electrodes A 1 1 and B 1 1 are reversed to the potentials Vcl 1 and V d 1 1 supplied to the pixel electrodes Cl 1 and D11. Therefore, the liquid crystal display device 1 is driven by a display device such as a one-line conversion drive in which the polarity of each column is reversed. As described above, in the fifth embodiment, the offset pulse SD I having the time length of the double timing signal YCLK can be smoothly driven by the two systems of the output control line OE. It should be noted that, instead of the fifth embodiment, other embodiments may also adopt an offset pulse SD I having a time length of m times (m is a natural number greater than 2) of the timing signal YCLK by outputting the control line 0E. m system controls. Sixth Embodiment Next, a sixth embodiment of the present invention will be described. In this sixth embodiment, due to the overall structure of the liquid crystal display device 1 and

And the circuit structure of an array substrate, the pixel driving method similar to the first embodiment is similar to the fifth embodiment, and the same description as the first embodiment and the fifth embodiment will be omitted herein, and the main description and the An embodiment differs from the fifth embodiment. The sixth embodiment is different from the first and fifth embodiments in that the control circuits 6 and 6' and the gate driver 5 are used when a liquid crystal display device 1 is driven.

Page 63 1251801 V. INSTRUCTIONS (59) 5 ′'s action. It should be noted that in the sixth embodiment, the precharging of the pixels is also not completed. First, the control circuit 6 and the driver 5' in the sixth embodiment will be explained below.

Figure 42 is a timing diagram 'displaying an offset pulse SD I supplied to the scan line with the scan signal Gn+1 out to Gn +3 out of +丨 to Gn + 3, output to the offset register (10), Corresponding to the above-mentioned scan signal rotation 9 control; number 0E1 to 0E3, and a timing signal y^lk of the drive offset register SR. It should be noted that in Fig. 42, the potential rising portion of the precharge in the scanning signals Gn+i 〇ut to Gn +4 out is also indicated by a solid line. In order to drive the pixel ' in the sixth embodiment', first, the offset pulse sdi is output from the pulse generating unit 9 of the control circuit 6' to the gate driver 12). As shown in Fig. 42, the offset pulse SDI is made up of one of two cycles with the up-down timing signal YCLK, 矣M den τΓ. Here, one cycle of the timing signal YCLK is equal to the -J J water tenth cycle of the screen. In particular, the offset pulse SD I has a time length of two horizontal broadcasts. Here, in the gate driver 5, the % tooth temporary storage unit π 1 2, the offset pulse SDI, and the timing signal YCLK on the well 々η # ^

Add π β Shi Meng Shi Ding Sheng Zhitong, in the timing signal YCLK IU hard register SR. Therefore, by providing two cycles of the timing signal YCLK 彳 环 沾 # 叫 叫 巨 巨 巨 巨 巨 SD SD SD SD SD SD SD SD SD SD SD SD SD SD SD SD SD SD SD SD SD SD SD SD SD SD SD SD SD SD SD When LU is fixed, it moves continuously when it is offset from the scratchpad SR. Therefore, as shown in Fig. 27, the μ τ is not provided by the output control signals 〇Ε 1 and 0 Ε 2 or 0 Ε 2 and 0 Ε 3 to each other γ ^ adjacent to the buffer Β, connected to the two biases

1251801 V. INSTRUCTIONS (60) ----- The buffer B of the shift register SR is simultaneously controlled, so that two scans are selected and controlled at the same time. The specific operation of the gate driver 5 will be described. It should be noted that the output control signal OE1 shown in 37 is supplied to the buffer 连接 connected to each input of the scanning line back to a Gn+1, Gn + 4.... At the same time, the output signal ΟΕ2 is supplied to the buffer B connected to each of the scanning lines Gn + 2, Gn + 5·.·, and the output control signal 〇E3 is supplied to the connection to the Sweep 1 Gn + 3, Gn + Buffer B for each input of 6···. At the time t0 to the time of the temple Fb1 t2, the point 'offset pulse SDI appears on each offset connected to the scan lines 611+1 and Gn + 2 to temporarily cry. Here, first, in the time t〇 to the time period, since the output control signals 〇Ei^ 〇Ef corresponding to the buffers B of the scanning lines 11+1 and Gn + 2 have a "〇" value, and are connected to Both the scan lines Q+丨 and the buffer B at the input of Gn+2 are activated. Therefore, the data of the offset pulse 讣I appearing in the offset register is output to the scanning lines Gn + Ι and Gn + 2 as the scanning signal Gn + 1 (10) Caution Gn + 2 〇ut. Therefore, in the period from time to time ^, the scanning lines Gn + Ι and Gn + 2 can be selected and controlled. 〇 In addition, during the period from the following time to time t2, the value of the output control signal E1 is set to "〇", but the value of the output control signal 〇E2 is set to 1. Therefore, only the buffer connected to the wheel end of the scanning line Gn+丨 is activated. Therefore, only the data of the offset pulse SD I appearing in the offset register SR corresponding to the scanning line Gn+1 is output to the scanning line GnH. Therefore, the scanning signals Gn+1 out and Gn +2 out become as shown in Fig. 42, and therefore only the scanning line Gn+Ι is selected.

1251801 V. INSTRUCTION DESCRIPTION (61) Further, in the time point of the following time 12 to time 14, the offset register SR and the timing signal YCLK are simultaneously activated, and therefore, the offset pulse SDI is moved to be connected to the scanning line G η + 2 and G η + 3 for each offset register SR. Here, in the period from time t 2 to time t 3 , since the output control signals 0E2 and 0E3 supplied to the buffers B corresponding to the scanning lines Gn + 2 and Gn + 3 have π 〇" values, they are connected to the scanning lines. The buffer Β at the output of Gn +2 and Gn + 3 is activated. Therefore, the data of the offset pulse SD I appearing in the offset register SR is

The scanning signals G η + 2 〇 u t and G η + 3 〇 u t are output to the scanning lines G η + 2 and Gn + 3 . Therefore, in the period from time t2 to time t3, the scanning lines Gn + 2 and Gn + 3 can be selected and controlled. Further, in the period from the following time t3 to time ΐ4, the value of the output control signal ΟΕ2 is set to π 〇, but the value of the output control signal ΟΕ1 is set to "1". Therefore, only the output connected to the scanning line Gn + 2 The buffer B of the terminal is activated. Therefore, only the data of the offset pulse SD of the offset register SR corresponding to the scanning line Gn + 2 is output to the scanning line Gn + 2: therefore, the scanning signal Gn + 2 Begging and Gn + 3 〇ut become as shown in Fig. 42, and therefore only the scanning line Gn + 2 is selected. As described above, the scanning signals Gn+1 〇ut, Gn + 2 〇ut,

Gn + 3 out... can be generated. Therefore, in this sixth embodiment, the pixels can be driven as in the fifth embodiment. Specifically, since the scanning line Gn + squid Gn + 2 can be selected in the period from time to to time t1, the potential Val 1 supplied from the signal line Dm is supplied to the pixel electrode A1 丨 as shown in Fig. 38. Further, only the scanning line (^ + 丨 is selected during the period from time t1 to time t2, and therefore, the potential Vbl 提供 provided by the signal line Dm is supplied to the image B11' as shown in Fig. 39.

1251801 V. INSTRUCTION DESCRIPTION (62) Further, in the period from time t2 to time t3, the scanning lines Gn + 2 and Gn + 3 are selected, and therefore, the polarity is reversed to the potential Vcl 1 of the potential Vbl 1 by the signal line Dni is supplied to the pixel electrode C 1 1 . Further, in the period from time t 3 to time 14, only the scanning line G η + 2 is selected, and therefore, the potential V d 1 1 is supplied from the signal line Dm to the pixel electrode D 1 1 . Therefore, the liquid crystal display device 1 is driven by a display device such as a one-line conversion drive in which the polarity of each column is reversed.

As described above, in this sixth embodiment, the time-long offset pulse SD I having twice the timing signal YCLK can be smoothly driven by the three systems of the control line OE. It should be noted that, instead of the sixth embodiment, other embodiments may also adopt an offset pulse SD I having a time length of ΐΏ times (m is a natural number greater than 2) timing signal YCLK by outputting the control line 0E. η system control, this number η is greater than m 〇 characteristics of the present invention

As described above, according to the present invention, the selection signal can be efficiently supplied to the multiplexed pixel, and the time point of pre-charging and the driving waveform and method of the pixel can be efficiently determined.

Page 67 1251801 Schematic description of the figure and the intention of the scan. A schematic diagram showing a timing diagram of a display signal in a first embodiment of the present invention. A system showing a whole structure of a liquid crystal display device to which the present invention is applied shows a structure of a first array substrate of the present invention. One of the diagrams of the diagrams of the diagrams of the diagrams of the diagrams of the circuit diagrams of the diagrams of the diagrams of the circuit diagrams of the diagrams of the diagrams of the circuit diagrams of the four diagrams of the movements of the six series of movements The explicit display selects the ten-line display of the present invention, and shows the present invention, showing the present invention, showing the present invention, showing the first embodiment of the present logic. The first lower one, the first one, the first one, the first action, the first diagram of the driving matrix, the bright figure of the device. The figure of the figure is shown in Figure 5. The figure of the figure is shown in Figure 7. The circuit of the circuit is shown in the embodiment of the liquid crystal display. A liquid crystal display device of a first embodiment of a main portion of the embodiment

A schematic diagram of a liquid crystal display device of one embodiment. A schematic diagram of a liquid crystal display device of one embodiment. A schematic diagram of a liquid crystal display device of one embodiment. A liquid crystal display device of one embodiment is intended. Liquid crystal display device of a first embodiment

Figure 11 is a view showing a first offset pulse and a scan signal of the present invention showing a timing signal and a timing chart of a first embodiment of the present invention. A further circuit configuration of the array substrate of an embodiment is not intended.

Page 68 1251801 Brief description of the diagram Figure 13 is a circuit diagram of the base diagram of a fourteenth time series of fifteen pulses, and a sixteenth circuit diagram of the sixteenth circuit diagram of the circuit of the seventeenth circuit A schematic diagram of a drive matrix system is shown in this figure. The present invention shows an action of displaying an action, and a display action, showing an array of a second embodiment of the present invention. A timing of one of the display signal and the scanning signal of the second embodiment of the present invention is a schematic diagram of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 10 is a timing signal of an embodiment of the present invention. A liquid crystal display in a second embodiment is a schematic diagram of a liquid crystal display. A liquid crystal display of a second embodiment shows a schematic diagram of a step below the seventeenth embodiment. DETAILED DESCRIPTION OF THE INVENTION A liquid crystal display device according to a third embodiment of the third embodiment of the invention is a schematic diagram showing a timing chart of a signal and a scanning signal. Figure 21 is a view showing one of the actions of a circuit of a liquid crystal device in a third embodiment of the present invention. FIG. 20 is a circuit diagram of a device. FIG. 20 is a circuit diagram of a device. The second circuit of the device is shown in the following figure. The present invention is not shown in the drawings. One of the third embodiments, one of the liquid crystals, one of the steps below, one of the steps of the third embodiment, one of the liquid crystals, twenty-two, one step, one of the steps, one of the third embodiments, the liquid crystal twenty-three The schematic shift of the next step shows the display display display of the display device. Show the graph. Show the graph.

Page 69 1251801 Brief description of the diagram Figure 20 Circuit diagram of the device 20 Circuit diagram of the device 20 A device of the device 20 shows the signal and the scan of the twenty offset pulse, the five-line display action six series of action seven The system is shown in the following figure, which is a schematic diagram of the liquid crystal display of the third embodiment of the present invention. A liquid crystal display of one of the third embodiments is a schematic diagram of the next step. One of the liquid crystal displays of the third embodiment is shown in Fig. 20, which is a timing chart showing the present invention. Figure 30 of the signal of the present invention shows a timing signal diagram of the fourth embodiment of the fourth embodiment of the present invention. One of the first timings, a liquid crystal display device in the fourth embodiment

Schematic diagram of one of the actions of a circuit. The circuit diagram of the device is shown in Figure 30. The circuit diagram of the device is shown in Figure 30. The circuit diagram of the device 30. The device is a three-figure circuit and a picture of the 30th and the scanning letter. The second line of the action of the three-line display action four-line display matrix five-series simple brake drive display this hair, indicating the present hair, indicating the present hair, indicating that the fourth embodiment of the present hair ^ night crystal display Figure 30 is a schematic diagram of the next step. A liquid crystal display of one of the fourth embodiments is shown in FIG. A liquid crystal display of one of the fourth embodiments is a schematic diagram of the next step of FIG. One of the fourth embodiments of the liquid crystal display

A schematic diagram of a display of a fifth embodiment of the present invention shows a timing chart of a display signal in a fifth embodiment of the present invention. Figure.

Page 70 1251801 Brief description of the drawing Figure 37 shows a circuit of offset pulse and a circuit of the scanning device of the thirty-eighth display device. Circuit diagram of the device. Figure of the circuit of the fortieth device. Circuit diagram of the device for forty. The signal and offset nine-display operation display operation, a series of action two-system simple pulse, a timing signal of a fifth embodiment of the present invention, and a timing chart of the signal. A schematic diagram of a liquid crystal display operation in a fifth embodiment of the present invention. A liquid crystal display showing one of the fifth embodiments of the present invention, showing a schematic diagram of a step below the thirty-eighth embodiment. A liquid crystal display device according to a fifth embodiment of the present invention is a schematic view showing a step below the figure 39. A liquid crystal display showing one of the fifth embodiments of the present invention is a schematic view showing a step below the fourth step of the drawing. A timing chart of a timing and scan signal of a sixth embodiment of the present invention is shown.

Symbols of the illustrated components A, B, All A13, B13, C32, C33 Bu 1, 3 5 ^ 5, 6 ^ 6, 8^ 8, 9 10 D12, B32, C31

Bn, Cn, DU, A12, B12, C12 C13, D13, A3, A32, A33, B3, pixel electrode liquid crystal display device (image display device), tributary drive gate driver (scanning line drive circuit), control circuit (scanning line) Drive circuit) output start/stop control unit pulse generation unit (signal column generation unit timing signal generation unit

Page 1251801 Schematic description 12 offset temporary storage unit B buffer (output circuit) D, Dm signal line DCPV, YCLK timing signal G, Gn, Gn + Bu Gn+2, Gn+3, Gn+4, Gn +5, Gn+6, Gn+7 signal lines

Gn+1 out, Gn+2 out, Gn+3 out, Gn+4 out, Gn+5 out Scan signal 0E, 0E1, 0E2, 0E3 Output control line, output control signal 0t PI P2 SDI SR SM Bu M2, M3 , M34 M35 Vail Ve31 M31 M32 M33

Vbl 1 Va41 output terminal first pulse second pulse offset pulse (signal column offset register display area first thin film transistor brother - a thin film transistor third thin film transistor fourth thin film transistor young five thin film electric Crystal Vcl 1> Vdl1^ Va31 Vb4 Bu Vc4 Bu Vd41

Vb31, potential

Vc3 Bu Vd31

Page 72

Claims (1)

1251801 VI. The scope of the patent application includes · for providing a display signal. 1. An image display device, a plurality of signal lines, being a first pixel electrode group, connected to a first horizontal scanning pixel electrode group The first horizontal sweep is continuously selected, the second continuous scan is selected, the first second pixel second horizontal scan week is connected to the specific signal, and the first scan period drives the first image period to drive the first The water is specific to the scanning circumference to drive the middle portion, and the specific scanning image in the special period is in the pixel electrode group period of the scanning electrode, the line group, the line group, the element electrode group, and the element electrode a second sweep period is selected; and a set of electrodes of the trace group is used to provide a scan signal available for the first set; and a scan signal for providing the scan signal of the first set is used to provide a specific sweep in the set of traces to In the second image sketching cycle, the signal line is connected; one pixel electrode group after the drawing period is a horizontal scanning Tuesday horizontal scanning circumference, and the group of the scanning line is driven in the electrode group. Any one of the scan lines is not selected from the selection of the first level to the middle of the second horizontal scan period. 2. The image display device of claim 1, wherein the specific pixel electrode is driven under the same polarity in the first horizontal scanning period and the second horizontal scanning period. 3. The image display device of claim 1, wherein the specific scan line group shares at least one scan line with the first scan line group. Page 73 1251801 VI. Application scope of the patent 4: If the same horizontal scanning period is included in the scope of the patent application, the individual two image head display devices, in the _ number; and the same water two k for the same polarity The adjacent letter/line of the display letter provides a different:::, between the plurality of positive lines, I and Zhuangzhi do not signal. An image display device comprising: I m pixel electrodes, continuously driving water from a first time point to an mth time point: in the scanning period, from the _1 number, and the m pixel electrode systems蛀 蛀 ς ς 值 值 值 值 值 值 自然 自然 自然 自然 自然 自然 自然 自然 自然 自然 自然 自然 自然 自然 自然 自然 自然 : : : : : : : : : : : : : : : : : : : : : : : : : : The time point is to the 筮0 丨 丨 line; ^ and ... a pixel electrode is connected to the: 弟定:: point scan line group, selects IV | another m image of the element f 1 second horizontal scan period drives the ι(四)έ ^ I The natural number up to m. God 6 · Such as Shen Qing patent model: in the horizontal scanning cycle, the household; one of the image display devices, which is at the time point of ▲ 7 brothers η. The image display device of claim 5, wherein the specific scan line group includes a scan line for providing the first image. The m pixel electrodes are driven and controlled in a horizontal scanning period. 8. The image display device of claim 5, wherein at least one scan line in the specific scan line group is not in the second horizontal scan period from the first time point to the first (n- 1) Select from the time points. 9. The image display device of claim 5, wherein in the first horizontal scanning period, a selection time of the specific scanning line group is the ηth time point; and the specific scanning line group Different from the ηth time point in the first horizontal scanning period, the scan line for driving the scan signal for driving the πι pixel electrode. 1 0. A scanning line driving circuit, comprising: a plurality of output terminals, which are connectable to a plurality of scanning lines; a signal output unit is configured to output a signal sequence including a plurality of signals respectively corresponding to the output terminal; wherein the signal output unit simultaneously outputs the signal column to the plurality of output terminal groups in a horizontal scanning period, one by one Each horizontal scanning period is offset from the output terminal to output the signal column to other output terminal groups; and output a signal group 'the signal group in a particular horizontal scanning period Page 75 1251801 6. The patent application scope outputs a specific output terminal in the output terminal group at a first time point, and a specific output terminal at a second time point in another horizontal scanning period after the specific horizontal scanning period; And outputting a signal different from the signal group to the specific output terminal during the period from the first time point to the second time point. 11. A pixel driving method comprising the steps of: a first step of selecting and starting to charge a particular pixel electrode in a first horizontal scanning period; a second step of continuously selecting and charging a pixel electrode group including the specific pixel electrode in the second horizontal scanning period after the first horizontal scanning period; wherein the specific pixel electrode remains operating in the first A potential of the step until after the second step is selected. The pixel driving method of claim 11, wherein the pixel electrodes are formed in a matrix, and the pixel electrodes having the same pixel structure are elements of the same row. Other pixel electrode groups different from the specific pixel electrode are continuously selected and charged in the first horizontal scanning period, and a pixel electrode is selected in the first step in the other pixel electrode group. For a particular pixel electrode, the pixel electrode in one row is different from the pixel electrode driven at the same point in time, which is when the particular pixel electrode begins to charge. Page 76 1251801 VI. Patent Application Range 2 5. The scan line driver circuit as described in claim 24, further comprising: a plurality of offset registers respectively connected to the output circuit and connected in series with each other a timing signal generating unit for generating a timing signal for driving the offset register; and a signal column generating unit for generating a signal column for continuous transmission to the offset register, wherein each signal column There is a time length m (m is a natural number) of the timing signal, and the m value is larger than the η value. The scanning line driving circuit of claim 24, further comprising: a plurality of offset registers respectively connected to the output circuit and connected in series with each other; a timing signal generating unit, Providing a timing signal for driving the offset register; a signal column generating unit for generating a signal sequence for continuous transmission to the offset register, wherein each signal column has m times the time length of the timing signal (m is a natural number), and the m value is a ratio The value of η is small. Page 82