JP2008242144A - Liquid crystal display device, and driving circuit and driving method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a liquid crystal display device capable of displaying an image of an interlaced signal itself without generating an afterimage or without causing burning. <P>SOLUTION: A digital image signal having black data inserted between data of odd-numbered rows in an odd field and between data of even rows in an even field is sent from a display control circuit to a source driver. The source driver applies driving video signals to respective source bus lines so that when respective gate bus lines are selected, the driving video signals applied to the respective source bus lines are inverted in polarity in every two fields. Each pixel formation part is AC-driven in unit periods each comprising four successive field periods. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a liquid crystal display device, and more particularly to a technique for displaying an image based on a video signal given by an interlace method in an active matrix liquid crystal display device.

  Conventionally, in the broadcasting industry and the like, confirmation of a display image is performed by a device called a master monitor. As a master monitor, a CRT (Cathode Ray Tube) has been conventionally used in many cases, but a liquid crystal display device is also being used in recent years. By the way, with respect to image display, in general television broadcasting, an interlace method (a method of displaying one screen by two scans is performed, odd-numbered rows are scanned first, and even-numbered rows are scanned second. In the liquid crystal display device, a progressive method (a method in which one screen is displayed by one scan) is adopted. For this reason, when an image is displayed on the liquid crystal display device based on the interlace signal, data between those rows is generated based on the data every other row indicated by the interlace signal (for example, one row). The data of the second row is generated based on the data of the eye and the data of the third row), and the scanning signal lines are scanned one row at a time.

  However, it is strongly desired to display “an image in which data is not generated” (ie, an image based on an interlace signal itself). Therefore, it is considered to display an image of the interlace signal itself with a liquid crystal display device. In general, a liquid crystal display device employs a driving method called “dot inversion driving” in order to prevent occurrence of flicker. FIG. 18 is a diagram illustrating a change in polarity during a period of four consecutive fields (for convenience, the “first to fourth fields”, respectively) in a liquid crystal display device that employs dot inversion driving. In any field, the polarity of the voltage applied to the liquid crystal layer in each pixel formation portion (hereinafter simply referred to as “polarity of the pixel formation portion”) in both the horizontal direction and the vertical direction is the adjacent pixel formation portion. They are opposite to each other. Further, when attention is paid to individual pixel formation portions, the polarity is reversed every time the field changes. Here, in order to display the image of the interlace signal itself, consider “inserting a black image” instead of “generating data between rows” as described above. Then, the change in the polarity of each pixel forming portion during the period of four consecutive fields is as shown in FIG. In FIG. 19, the hatched portion indicates a portion where a black image is displayed. As described above, the liquid crystal display device can perform pseudo-interlaced image display.

Japanese Patent Laid-Open No. 7-75045 discloses an invention of a driving method of a liquid crystal display device that prevents the occurrence of flicker by inverting the polarity of an interlaced video signal every two fields.
JP-A-7-75045

  However, when the image display by the pseudo interlace method is performed as described above, a direct current component remains in the liquid crystal in each pixel forming unit. For example, the polarities of the four field periods of the pixel formation portion indicated by reference numeral 8 in FIG. 19 are “positive, 0 (black), positive, 0 (black)”. Further, the polarities in the four field periods of the pixel formation portion indicated by reference numeral 9 in FIG. 19 are “negative, 0 (black), negative, 0 (black)”. As described above, as a result of applying a voltage in one direction (applying a DC voltage) in each pixel forming portion, an afterimage or image sticking occurs in the display portion.

  Accordingly, an object of the present invention is to provide a liquid crystal display device capable of displaying an image of an interlace signal itself without causing an afterimage or image sticking.

According to a first aspect of the present invention, a plurality of video signal lines for respectively transmitting a plurality of video signals representing images to be displayed, a plurality of scanning signal lines intersecting with the plurality of video signal lines, and the plurality of video signals When a scanning signal line arranged in a matrix corresponding to each of the intersections of the line and the plurality of scanning signal lines and passing through the corresponding intersection is selected, the video signal line passing through the corresponding intersection is selected. An active matrix liquid crystal display device including a display unit including a plurality of pixel formation units that capture a transmitted video signal as a pixel value,
A scanning signal line driving circuit for selectively driving the plurality of scanning signal lines sequentially one by one;
The plurality of video signals are applied to the plurality of video signal lines so that the polarity of the video signal applied to each video signal line is inverted every two vertical scanning periods when each scanning signal line is selected. A video signal line driving circuit;
The voltage of the video signal applied to the plurality of video signal lines when the odd-numbered scanning signal lines are selected and the plurality of video signal lines when the even-numbered scanning signal lines are selected. And black insertion means for alternately changing the voltage of the applied video signal for each vertical scanning period to a voltage corresponding to black display.

According to a second invention, in the first invention,
The video signal line driving circuit applies the plurality of video signals to the plurality of video signal lines so that polarities of video signals applied to the plurality of video signal lines are different from each other between adjacent video signal lines. It is characterized by that.

According to a third invention, in the first or second invention,
The video signal line driving circuit applies the plurality of video signals to the plurality of video signal lines so that the polarity of the voltage of the video signal applied to each video signal line is inverted every two horizontal scanning periods. It is characterized by.

According to a fourth invention, in any one of the first to third inventions,
The black insertion means displays the voltage of the video signal applied to the plurality of video signal lines in black by short-circuiting the video signal lines to which video signals having different polarities are applied among the plurality of video signal lines. The voltage is equivalent to

A fifth invention is the fourth invention,
The black insertion means short-circuits video signal lines adjacent to each other among the plurality of video signal lines, thereby setting the voltage of the video signal applied to the plurality of video signal lines to a voltage corresponding to black display. It is characterized by that.

According to a sixth invention, in any one of the first to fifth inventions,
A signal type determination means for determining whether the type of an image signal sent from the outside to generate the image to be displayed is an interlace signal or a progressive signal;
A backlight for irradiating the display unit with light from the back side;
Further comprising backlight control means for controlling the brightness of light emitted by the backlight,
When the signal type determining unit determines that the type of the image signal is an interlace signal, the backlight control unit determines that the type of the image signal is a progressive signal when the signal type determining unit determines that the type of the image signal is an interlaced signal. Rather, the brightness of the light is increased.

A seventh invention is the sixth invention, wherein
When the signal type determining unit determines that the type of the image signal is an interlace signal, the backlight control unit determines that the type of the image signal is a progressive signal when the signal type determining unit determines that the type of the image signal is an interlaced signal. The brightness of the light is doubled.

According to an eighth aspect of the present invention, a plurality of video signal lines for respectively transmitting a plurality of video signals representing images to be displayed, a plurality of scanning signal lines intersecting with the plurality of video signal lines, and the plurality of video signals When a scanning signal line arranged in a matrix corresponding to each of the intersections of the line and the plurality of scanning signal lines and passing through the corresponding intersection is selected, the video signal line passing through the corresponding intersection is selected. A drive circuit for an active matrix liquid crystal display device including a display unit including a plurality of pixel forming units that capture a transmitted video signal as a pixel value,
A scanning signal line driving circuit for selectively driving the plurality of scanning signal lines sequentially one by one;
The plurality of video signals are applied to the plurality of video signal lines so that the polarity of the video signal applied to each video signal line is inverted every two vertical scanning periods when each scanning signal line is selected. A video signal line driving circuit;
The voltage of the video signal applied to the plurality of video signal lines when the odd-numbered scanning signal lines are selected and the plurality of video signal lines when the even-numbered scanning signal lines are selected. And black insertion means for alternately changing the voltage of the applied video signal for each vertical scanning period to a voltage corresponding to black display.

  Moreover, the modification grasped | ascertained by referring embodiment and drawing in 8th invention is considered as a means for solving a subject.

According to a thirteenth aspect of the present invention, a plurality of video signal lines for respectively transmitting a plurality of video signals representing images to be displayed, a plurality of scanning signal lines intersecting with the plurality of video signal lines, and the plurality of video signals When a scanning signal line arranged in a matrix corresponding to each of the intersections of the line and the plurality of scanning signal lines and passing through the corresponding intersection is selected, the video signal line passing through the corresponding intersection is selected. A driving method of an active matrix type liquid crystal display device including a display unit including a plurality of pixel forming units that capture a transmitted video signal as a pixel value,
A scanning signal line driving step for sequentially and selectively driving the plurality of scanning signal lines one by one;
The plurality of video signals are applied to the plurality of video signal lines so that the polarity of the video signal applied to each video signal line is inverted every two vertical scanning periods when each scanning signal line is selected. Video signal line driving step;
The voltage of the video signal applied to the plurality of video signal lines when the odd-numbered scanning signal lines are selected and the plurality of video signal lines when the even-numbered scanning signal lines are selected. And a black insertion step of changing the voltage of the applied video signal alternately to a voltage corresponding to black display every vertical scanning period.

  Further, in the thirteenth invention, a modification grasped by referring to the embodiment and the drawings is considered as a means for solving the problem.

  According to the first aspect, the voltage of the video signal when the odd-numbered scanning signal line is selected and the voltage of the video signal when the even-numbered scanning signal line is selected are 1 The voltage is alternately equivalent to black display every vertical scanning period. Thereby, an image based on the interlace signal itself is displayed on the display unit. Here, the polarity of the video signal applied to each video signal line when each scanning signal line is selected is inverted every two vertical scanning periods. For this reason, regarding the voltage applied to the liquid crystal layer of each pixel formation portion in the continuous four vertical scanning periods, the positive polarity is once, the negative polarity is once, and the voltage corresponding to black display is twice. Therefore, no direct current voltage is applied to the liquid crystal layer of each pixel formation portion. Thereby, a liquid crystal display device capable of displaying an image of the interlace signal itself without causing image sticking or afterimage on the display unit due to application of the DC voltage is realized.

  According to the second aspect, the polarities of the voltages applied to the liquid crystal layer are opposite to each other between the pixel forming portions adjacent in the horizontal direction. For this reason, the image of the interlace signal itself can be displayed on the display unit while suppressing the occurrence of flicker.

  According to the third aspect of the present invention, when attention is paid only to the pixel forming portion in which a positive or negative voltage is applied to the liquid crystal layer in each vertical scanning period, the liquid crystal is generated between the pixel forming portions adjacent in the vertical direction. The polarities of the voltages applied to the layers are opposite to each other. For this reason, it is possible to display the image of the interlace signal itself on the display unit while more effectively suppressing the occurrence of flicker.

  According to the fourth aspect of the invention, the voltage corresponding to the black display is applied to the video signal lines by short-circuiting the video signal lines to which voltages having different polarities are applied. For this reason, the charge stored in the wiring capacitance of each video signal line is used to apply a voltage corresponding to the black display. Thereby, black display can be inserted in order to display the image of the interlace signal itself without increasing the power consumption.

  According to the fifth aspect, the voltage corresponding to black display is applied to the video signal lines by short-circuiting the video signal lines adjacent to each other for the video signal lines for each color. For this reason, it is possible to insert a black display with a simple configuration in order to display an image of the interlace signal itself without increasing power consumption.

  According to the sixth aspect of the invention, when the image of the interlace signal itself is displayed based on the interlace signal, the light emitted from the backlight is more effective than when the image is displayed based on the progressive signal. Brightness increases. For this reason, the brightness | luminance fall resulting from inserting black display is suppressed.

  According to the seventh aspect, when the image of the interlace signal itself is displayed based on the interlace signal, the light emitted from the backlight is more effective than when the image is displayed based on the progressive signal. The brightness is doubled. Since a voltage corresponding to black display is applied to the liquid crystal layer of each pixel formation portion in almost half of the entire period, black display is inserted by doubling the luminance of light. The decrease in luminance due to the is effectively suppressed.

  Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.

<1. First Embodiment>
<1.1 Overall configuration and operation>
FIG. 2 is a block diagram showing the overall configuration of the liquid crystal display device according to the first embodiment of the present invention. The liquid crystal display device includes a display unit 100, a display control circuit 200, a source driver (video signal line driving circuit) 300, a gate driver (scanning signal line driving circuit) 400, a selector 500, a microcomputer 600, and a backlight control circuit (backlight). Control means) 700 and a backlight 800. This liquid crystal display device is a normally black type.

  The display unit 100 includes a plurality (n) of source bus lines (video signal lines) SL1 to SLn, a plurality (m) of gate bus lines (scanning signal lines) GL1 to GLm, and source buses thereof. A plurality of (n × m) pixel forming portions provided corresponding to the intersections of the lines SL1 to SLn and the gate bus lines GL1 to GLm are included. These pixel formation portions are arranged in a matrix to form a pixel array, and each pixel formation portion has a gate terminal connected to a gate bus line passing through a corresponding intersection and a source bus line passing through the intersection. TFT 10 that is a switching element to which a source terminal is connected, a pixel electrode that is connected to a drain terminal of the TFT 10, a common electrode Ec that is a common electrode provided in the plurality of pixel forming portions, and The liquid crystal layer is provided in common to the plurality of pixel formation portions and is sandwiched between the pixel electrode and the common electrode Ec. A pixel capacitor Cp is constituted by a liquid crystal capacitor formed by the pixel electrode and the common electrode Ec. Normally, an auxiliary capacitor is provided in parallel with the liquid crystal capacitor in order to reliably hold the voltage in the pixel capacitor Cp. However, since the auxiliary capacitor is not directly related to the present invention, its description and illustration are omitted.

  The selector 500 receives a video signal DV indicating image information and a timing signal group TG composed of a plurality of timing signals from a signal source external to the liquid crystal display device, and receives these signals DV and TG. And a type signal ST indicating whether the video signal DV is an interlace signal or a progressive signal. Thus, in this embodiment, the signal type determination means is realized by the selector 500.

  The display control circuit 200 receives the video signal DV and the timing signal group TG output from the selector 500, receives the digital image signal DA, and a source start pulse signal SSP for controlling the timing for displaying an image on the display unit 100, A source clock signal SCK, a latch strobe signal LS, a polarity inversion signal POL, a gate start pulse signal GSP, and a gate clock signal GCK are output.

  The source driver 300 receives the digital image signal DA, the source start pulse signal SSP, the source clock signal SCK, the latch strobe signal LS, and the polarity inversion signal POL output from the display control circuit 200, and forms each pixel in the display unit 100. A driving video signal is applied to each source bus line SL1 to SLn in order to charge the pixel capacitance Cp of the portion. The detailed configuration of the source driver 300 will be described later.

  The gate driver 400 applies an active scanning signal to the gate bus lines GL1 to GLm based on the gate start pulse signal GSP and the gate clock signal GCK output from the display control circuit 200.

  The microcomputer 600 outputs a switching instruction signal SW for controlling the luminance of the backlight 800 based on the type signal ST output from the selector 500. The backlight control circuit 700 controls (adjusts) the luminance of the backlight 800 based on the switching instruction signal SW output from the microcomputer 600. For example, if the type signal ST indicates that “the video signal DV is an interlace signal”, the microcomputer 600 sets the logic level of the switching instruction signal SW to the high level and sets the type signal ST to “the video signal DV is a progressive signal. If it indicates that the logic level of the switching instruction signal SW is low, The backlight control circuit 700 doubles the luminance of the backlight 800 when the logical level of the switching instruction signal SW is high, and the backlight control circuit 700 when the logical level of the switching instruction signal SW is low. The brightness of the light 800 is set to a normal brightness. In this way, when the type of the video signal DV sent from the outside is an interlace signal, the luminance of the backlight 800 becomes twice the normal brightness.

  As described above, the driving video signals are applied to the source bus lines SL1 to SLn, the scanning signals are applied to the gate bus lines GL1 to GLm, and the backlight is turned on according to the type of the video signal DV. As a result, an image is displayed on the display unit 100.

<1.2 Source Driver Configuration and Operation>
FIG. 3 is a block diagram showing a configuration of the source driver 300 in the present embodiment. The source driver 300 includes an n-stage shift register 31 equal to the number of source bus lines SL1 to SLn, a sampling and latch circuit 32 that outputs internal image signals d1 to dn corresponding to the source bus lines SL1 to SLn, A selection circuit 33 for selecting a voltage to be applied to each source bus line SL1 to SLn, and an output circuit 34 for applying the voltage selected by the selection circuit 33 to the source bus lines SL1 to SLn as a drive video signal. Are applied to the grayscale voltage generation circuit 35 for outputting voltages (grayscale voltage groups) VH0 to VHk and VL0 to VLk respectively corresponding to the grayscale levels in the positive polarity and the negative polarity, and the source bus lines adjacent to each other. And an inverter 36 for changing the polarity of the driving video signal. The inverter 36 is provided so as to correspond only to the source bus lines SL2, SL4,.

  A source start pulse signal SSP and a source clock signal SCK are input to the shift register 31. Based on these signals SSP and SCK, the shift register 31 sequentially transfers pulses included in the source start pulse signal SSP from the input end to the output end. In response to the transfer of the pulses, sampling pulses corresponding to the source bus lines SL1 to SLn are sequentially output from the shift register 31, and the sampling pulses are sequentially input to the sampling and latch circuit 32.

  The sampling / latch circuit 32 samples and holds the digital image signal DA output from the display control circuit 200 at the timing of the sampling pulse output from the shift register 31. Further, the sampling / latch circuit 32 outputs the held digital image signal DA as internal image signals d1 to dn at the same time as the pulse of the latch strobe signal LS. The inverter 36 inverts the polarity of the polarity inversion signal POL (inverts the logic level).

  The gradation voltage generation circuit 35 is based on a plurality of reference voltages supplied from a predetermined power supply circuit (not shown), and voltages VH0 to VHk and VL0 corresponding to the gradation level of “k + 1” for each of plus and minus polarities. ... VLk are generated and output as gradation voltage groups.

  The selection circuit 33 is one of the gradation voltage groups VH0 to VHk and VL0 to VLk output from the gradation voltage generation circuit 35 based on the internal image signals d1 to dn output from the sampling and latch circuit 32. Select voltage and output. At this time, the polarity of the voltage is determined based on the logic level of the polarity inversion signal POL output from the display control circuit 200. In the present embodiment, if the logic level of the polarity inversion signal POL is high, the selection circuit 33 selects a positive gradation voltage, and if the logic level of the polarity inversion signal POL is low, the selection circuit 33 is negative. A gradation voltage is selected. The voltage output from the selection circuit 33 is input to the output circuit 34.

  The output circuit 34 performs impedance conversion of the voltage output from the selection circuit 33 by, for example, a voltage follower, and outputs the converted voltage to the source bus lines SL1 to SLn as drive video signals.

<1.3 Driving method>
Next, a driving method when an interlace signal is sent from the outside as the video signal DV will be described. 4A schematically shows the content of data of the video signal DV sent from the outside, and FIG. 4B shows the content of data of the digital image signal DA sent from the display control circuit 200 to the source driver 300. FIG. When the type of the video signal DV is an interlace signal, as shown in FIG. 4A, first, the odd-numbered row data is sequentially sent from the outside, and then the even-numbered row data is sequentially sent from the outside. come. When data for one screen is sent in this way, the data for the next screen is also sent in the same manner. FIG. 4A is a schematic view. For example, “first row data” is provided corresponding to each column of the first row (first to nth columns). Data indicating the pixel value of the pixel forming portion is included.

  The display control circuit 200 receives the video signal DV sent as shown in FIG. 4 (a), and the data (every other row) of the video signal DV is displayed in black as shown in FIG. 4 (b). Is inserted for displaying the data (hereinafter referred to as “black data”). Thus, in the present embodiment, the black insertion means is realized by the display control circuit 200. Note that the black data inserted between the two odd-numbered data is the even-numbered data in the progressive driving, and the black data inserted between the two even-numbered data is the odd-numbered in the progressive driving. It becomes the data of the line. In this way, the digital image signal DA in which black data is inserted into every other row of data is sent from the display control circuit 200 to the source driver 300.

  FIG. 5 is a signal waveform diagram for explaining the driving method in the present embodiment. In the present embodiment, as shown in FIG. 5, a driving method is adopted in which four consecutive fields are set as a single unit period. Since one vertical scanning is performed in one field period, one field period corresponds to one vertical scanning period.

  As shown in FIG. 5A, for the polarity inversion signal POL, in the first and second fields, the logic level of the first two horizontal scanning periods is set to the high level and inverted every two horizontal scanning periods. In the fourth field, the logic level of the first two horizontal scanning periods is set to a low level and inverted every two horizontal scanning periods. Here, the polarity of the drive video signal is determined based on the logic level of the polarity inversion signal POL. As shown in FIG. 3, an inverter 36 for reversing the logic level of the polarity inversion signal POL is provided. It is provided so as to correspond only to the source bus lines SL2, SL4,. Thus, the change in the polarity of the driving video signal for each horizontal scanning period in the first and second fields is “positive, positive, negative, negative, positive, positive, negative, negative,. “,” And even columns should be “negative, negative, positive, positive, negative, negative, positive, positive,...”. On the other hand, the change in the polarity of the driving video signal for each horizontal scanning period in the third and fourth fields is “negative, negative, positive, positive, negative, negative, positive, positive,. ", And the even-numbered columns should be" positive, positive, negative, negative, positive, positive, negative, negative, ... ". In addition, as shown in FIGS. 5E to 5H, the scanning signal applied to each gate bus line is sequentially activated every horizontal scanning period.

  As described above, the change in the polarity of each pixel formation portion during the period of four consecutive fields should be as shown in FIG. According to this driving method, the polarity is reversed every two rows in the vertical direction. When attention is paid to individual pixel formation portions, the polarity is inverted every two fields. Therefore, the driving method that causes the change in polarity as shown in FIG. 6 is called “2H2F (field) inversion”.

  However, in the digital image signal DA sent from the display control circuit 200 to the source driver 300, black data is inserted every other row as described above. Specifically, in the odd field, black data as even-numbered data is inserted between two data in odd-numbered rows, and in the even-numbered field, odd-numbered rows are inserted between two data in even-numbered rows. Black data is inserted as data. Therefore, the waveform of the digital image signal DA is as shown in FIG. As a result, the waveform of the driving video signal S (a) applied to the odd-numbered source bus lines is as shown in FIG. 5C, and the driving video signal S (a) applied to the even-numbered source bus lines is as shown in FIG. The waveform of the video signal S (b) is as shown in FIG.

  FIG. 7 is a signal waveform diagram showing the change in polarity in each field for the drive video signal S (a) applied to the odd-numbered source bus lines. As shown in FIGS. 7A to 7D, in the first field, “positive, 0 (black), negative, 0 (black), positive, 0 (black), negative, 0 (black),... ”In the second field,“ 0 (black), positive, 0 (black), negative, 0 (black), positive, 0 (black), negative,... ”. In the third field,“ negative, 0 (Black), positive, 0 (black), negative, 0 (black), positive, 0 (black),..., And in the fourth field, “0 (black), negative, 0 (black), positive, 0 (black), negative, 0 (black), positive,... The polarity of the driving video signal S (b) applied to the even-numbered source bus lines is opposite to that of the driving video signal S (a) applied to the odd-numbered source bus lines.

<1.4 Effect>
According to the present embodiment, the change in the polarity of each pixel formation portion during the period of four consecutive fields is as shown in FIG. In FIG. 1, the hatched portion indicates a portion where a black image is displayed. As shown in FIG. 1, in the odd field, the (valid) image is displayed only for the odd rows, and the black image is displayed for the even rows. On the other hand, in the even field, the (valid) image is displayed only for the even-numbered rows, and the black image is displayed for the odd-numbered rows. Thus, in the liquid crystal display device according to the present embodiment, an image of the interlace signal itself is displayed.

  Here, the polarities in the four field periods of the pixel formation portion indicated by reference numeral 4 in FIG. 1 are “positive, 0 (black), negative, 0 (black)”. The polarities in the four field periods of the pixel formation portion indicated by reference numeral 5 in FIG. 1 are “negative, 0 (black), positive, 0 (black)”. The polarities in the four field periods of the pixel formation portion indicated by reference numeral 6 in FIG. 1 are “0 (black), positive, 0 (black), negative”. The polarities in the four field periods of the pixel formation portion indicated by reference numeral 7 in FIG. 1 are “0 (black), negative, 0 (black), positive”. Thus, in all the pixel forming portions, “one-way voltage application (DC voltage application) is not performed”. That is, an alternating voltage is applied to the liquid crystal layer in all pixel formation portions. For this reason, image sticking or afterimage does not occur on the display unit 100.

  Further, in each field of FIG. 1, when attention is paid only to a pixel formation portion to which a positive or negative voltage is applied (a pixel formation portion other than a pixel formation portion to which a black voltage is applied), the horizontal direction In both the vertical direction and the vertical direction, positive polarity and negative polarity appear alternately. For this reason, in this liquid crystal display device, occurrence of flicker is prevented.

  As described above, according to the present embodiment, a liquid crystal display device capable of displaying an image of the interlace signal itself while preventing occurrence of flicker, image sticking to the display unit 100, and afterimage is realized.

  Further, in the present embodiment, when the type of the video signal DV sent from the outside is an interlace signal, the luminance of the backlight 800 is set to the normal level (from the outside by the selector 500, the microcomputer 600, and the backlight control circuit 700). The type of the video signal DV to be a progressive signal). Thereby, a decrease in luminance due to the insertion of black data is suppressed.

<2. Second Embodiment>
<2.1 Overall configuration and operation>
FIG. 8 is a block diagram showing the overall configuration of a liquid crystal display device according to the second embodiment of the present invention. This liquid crystal display device includes a display unit 100, a display control circuit 200, a source driver 300, a first gate driver 401, a second gate driver 402, a selector 500, a microcomputer 600, a backlight control circuit 700, and a backlight 800. I have. In the present embodiment, unlike the first embodiment, the gate driver includes a first gate driver 401 for driving the odd-numbered gate bus lines GL1, GL3,. The second gate driver 402 for driving the even-numbered gate bus lines GL2, GL4,. Note that the liquid crystal display device according to the present embodiment is also of a normally black type as in the first embodiment.

  The display control circuit 200 receives the video signal DV and the timing signal group TG output from the selector 500, receives the digital image signal DA, and a source start pulse signal SSP for controlling the timing for displaying an image on the display unit 100, Source clock signal SCK, latch strobe signal LS, polarity inversion signal POL, short circuit control signal Csh, first gate start pulse signal GSP1, first gate clock signal GCK1, first gate driver output control signal GOE1, second The gate start pulse signal GSP2, the second gate clock signal GCK2, and the second gate driver output control signal GOE2 are output.

  The source driver 300 receives the digital image signal DA, the source start pulse signal SSP, the source clock signal SCK, the latch strobe signal LS, the polarity inversion signal POL, and the short circuit control signal Csh output from the display control circuit 200, and the display unit 100 A driving video signal is applied to each source bus line SL1 to SLn in order to charge the pixel capacitance Cp of each pixel forming portion.

  In the present embodiment, in order to reduce power consumption, a charge sharing method is employed in which adjacent source bus lines are short-circuited every horizontal scanning period. For this reason, the output unit, which is a part that outputs the driving video signals S (1) to S (n) in the source driver 300, is configured as shown in FIG. That is, the output unit receives analog voltage signals v (1) to v (n) generated based on the digital image signal DA, and impedance-converts these analog voltage signals v (1) to v (n). To generate driving video signals S (1) to S (n) to be transmitted through the source bus lines SL1 to SLn, and has n buffers 37 as voltage followers for impedance conversion. Yes.

  A first MOS transistor SWa as a switching element is connected to the output terminal of each buffer 37, and the driving video signal S (i) from each buffer 37 is output from the source driver 300 via the first MOS transistor SWa. Output from the terminal (i = 1, 2,..., N). Further, adjacent output terminals of the source driver 300 are connected by a second MOS transistor SWb as a switching element. A short-circuit control signal Csh is given to the gate terminal of the second MOS transistor SWb between these output terminals, and the gate terminal of the first MOS transistor SWa connected to the output terminal of each buffer 37 is An output signal of the inverter 38, that is, a logical inversion signal of the short circuit control signal Csh is given. Accordingly, when the logic level of the short-circuit control signal Csh is low, the first MOS transistor SWa is turned on and the second MOS transistor SWb is turned off, so that the driving video signal from each buffer 37 is the first video signal. The signal is output from the source driver 300 via the MOS transistor SWa. On the other hand, when the logic level of the short circuit control signal Csh is high, the first MOS transistor SWa is turned off and the second MOS transistor SWb is turned on, so that the driving video signal from each buffer 37 is not output, The adjacent source bus lines in the display unit 100 are short-circuited via the second MOS transistor SWb. Note that the configuration in which the voltage of each source bus line is brought close to the black voltage by short-circuiting adjacent source bus lines has been proposed as a means for reducing power consumption, and the configuration shown in FIG. It is not limited. In the present embodiment, the black insertion means is realized by the configuration shown in FIG.

  The first gate driver 401 generates an odd-numbered row based on the first gate start pulse signal GSP1, the first gate clock signal GCK1, and the first gate driver output control signal GOE1 output from the display control circuit 200. Scan signals G (1), G (3),..., G (m−1) are applied to the gate bus lines GL1, GL3,. Based on the second gate start pulse signal GSP2, the second gate clock signal GCK2, and the second gate driver output control signal GOE2 output from the display control circuit 200, the second gate driver 402 Scan signals G (2), G (4),..., G (m) are applied to the gate bus lines GL2, GL4,.

  Here, the configuration of the first gate driver 401 will be described with reference to FIG. As shown in FIG. 10, the first gate driver 401 includes a shift register 40, first and second AND gates 41 and 43 provided corresponding to each stage of the shift register 40, And an output unit 45 that outputs scanning signals G (1), G (3),..., G (m−1) based on an output signal from the AND gate 43. The first gate start pulse signal GSP1 and the first gate clock signal GCK1 are input to the shift register 40, and output signals Q (1), Q (3),. (M-1) is output. Each of the first AND gates 41 receives a logical inversion signal of the first gate clock signal GCK1 and an output signal from the shift register 40. Each of the second AND gates 43 receives a logic inversion signal of the first gate driver output control signal GOE1 and an output signal from the first AND gate 41. Then, the output signals of the second AND gate 43 are level-converted by the output unit 45, and the scanning signals G (1), G (3),..., G (m−m−) to be applied to the gate bus lines. 1) is output. Note that the configuration of the second gate driver 402 is the same as the configuration of the first gate driver 401, and thus description thereof is omitted.

  Since operations of the selector 500, the microcomputer 600, the backlight control circuit 700, and the backlight 800 are the same as those in the first embodiment, description thereof is omitted.

<2.2 Driving method>
Next, a driving method in the present embodiment will be described with reference to FIGS. 11 and 12. FIG. 11 is a signal waveform diagram in the first and second fields, and FIG. 12 is a signal waveform diagram in the third and fourth fields. In the present embodiment, unlike the first embodiment, a digital image signal DA is sent from the display control circuit 200 to the source driver 300 as shown in FIG. That is, no black data is inserted between the data (for example, between the first row data and the third row data). For the polarity inversion signal POL, as in the first embodiment, the logic level is inverted every two horizontal scanning periods (2H) as shown in FIG. As a result, the waveform of the analog voltage signal v (a) for the source bus line in the odd-numbered column generated inside the source driver 300 becomes as shown in FIG. Regarding the analog voltage signal v (a), the value in the period from the time point t1 to the time point t2 corresponds to the data value in the first row in FIG. 4A, and the value in the period from the time point t2 to the time point t3 is 3 Corresponds to the data value on the line. Further, the value in the period from the time point t4 to the time point t5 corresponds to the value of the data in the second row, and the value in the period from the time point t5 to the time t6 corresponds to the value of the data in the fourth row. Note that the waveform of the analog voltage signal for the even-numbered source bus lines is opposite in polarity to the waveform of the analog voltage signal v (a) for the odd-numbered source bus lines.

  The output section of the source driver 300 is configured as shown in FIG. 9, and the short-circuit control signal Csh sent from the display control circuit 200 is a predetermined value every two horizontal scanning periods as shown in FIG. It becomes high level only for the period Tsh. As described above, when the short circuit control signal Csh is at the low level, the analog voltage signals v (1) to v (n) are output as the drive video signals S (1) to S (n), and the short circuit control signal Csh is high. When at level, adjacent source bus lines are shorted together. In the present embodiment, the voltages of adjacent source bus lines have opposite polarities, and their absolute values are substantially equal. Therefore, the voltages of the driving video signals S (1) to S (n) are voltages corresponding to black display (hereinafter also simply referred to as “black voltage”) in the short circuit period Tsh. As a result, the waveform of the driving video signal S (a) applied to the odd-numbered source bus lines is as shown in FIG. Note that the waveform of the drive video signal applied to the even-numbered source bus lines has the opposite polarity to the waveform of the drive video signal S (a) applied to the odd-numbered source bus lines. .

  As described above, when the driving video signals S (1) to S (n) are applied to the source bus lines SL1 to SLn, the gate bus lines are shown in FIGS. 11 (d) to 11 (g). Such scanning signals G (1) to G (4) are applied (FIG. 11 shows the first to fourth rows). As shown in FIGS. 11 and 12, in the odd field, the drive video signal S (a) effective as the image data is applied to the odd-numbered gate bus lines during the application period. The scanning signal is active. The application of the active scanning signal to the odd-numbered gate bus lines is performed every two horizontal scanning periods (2H). Further, during the period in which the drive video signal S (a) is at the black voltage, the scanning signal applied to the even-numbered gate bus lines is active. The application of the active scanning signal to the even-numbered gate bus lines is performed four times for each gate bus line.

  On the other hand, in the even field, the scanning signal applied to the even-numbered gate bus lines is active during the period in which the driving video signal S (a) effective as the image data is being applied. . The application of the active scanning signal to the even-numbered gate bus lines is performed every two horizontal scanning periods (2H). Further, during the period in which the driving video signal S (a) is at the black voltage, the scanning signal applied to the odd-numbered gate bus lines is active. The application of the active scanning signal to the odd-numbered gate bus lines is performed four times for each gate bus line.

  Here, a method of generating the scanning signals G (1) to G (4) as shown in FIGS. 11 (d) to 11 (g) will be described. FIG. 13 is a signal waveform diagram for explaining generation of a scanning signal. As shown in FIG. 13A, the first gate start pulse signal GSP1 is at a high level for approximately 2 horizontal scanning periods in the odd field and is at a high level for approximately 8 horizontal scanning periods in the even field. As for the first gate clock signal GCK1, as shown in FIG. 13B, a short-term pulse is generated every two horizontal scanning periods (2H) in both the odd field and the even field. As shown in FIG. 13 (c), the first gate driver output control signal GOE1 is set to the high level only for the period T1 every two horizontal scanning periods in the odd field, and the period every two horizontal scanning periods in the even field. Only T2 is high. Note that the period T2 is set to be longer than the period T1. The signals GSP1, GCK1, and COE1 as described above are input to the first gate driver 401 having the configuration shown in FIG.

  With the configuration shown in FIG. 10, from each stage of the shift register 40 based on the first gate start pulse signal GSP1 and the first gate clock signal GCK1, as shown in FIGS. 13 (d) and 13 (e). Output signals Q (1) and Q (3) are output. Here, as described above, the logical AND signal of the first gate clock signal GCK 1 and the output signal from the shift register 40 are input to the first AND gate 41, and the first AND gate 43 receives the first AND gate 43. The logic inversion signal of the gate driver output control signal GOE1 and the output signal from the first AND gate 41 are input. Therefore, the scanning signal applied to each gate bus line becomes active because “the output signal from the shift register 40 is at a high level”, “the first gate clock signal GCK1 is at a low level”, and “the first gate. This is when the driver output control signal GOE1 is “low level”. Thereby, in the odd field, each of the scanning signals G (1) and G (3) becomes active only once, and the length of the active period becomes “a period shorter than the two horizontal scanning periods by the period T1”. . On the other hand, in the even field, each of the scanning signals G (1) and G (3) becomes active four times, and the length of the period in which the scanning signals G (1) and G (3) become active is A short period ".

  As described above, the scanning signals G (1) and G (3) as shown in FIGS. 11D and 11F are generated. Note that for the scanning signals G (2) and G (4), the second gate start pulse signal GSP2, the second gate clock signal GCK2, and the second signal sent from the display control circuit 200 to the second gate driver 402 are used. By shifting the timing of the gate driver output control signal GOE2 from the first gate start pulse signal GSP1, the first gate clock signal GCK1, and the first gate driver output control signal GOE1, the scanning signals G (1), G It is generated in the same manner as (3).

<2.3 Effects>
The effects of this embodiment will be described with reference to FIGS. 11 and 12 again. Here, attention is focused on the pixel formation portion provided corresponding to the intersection of the gate bus line GL1 in the first row and the source bus line SL1 in the first column. In the first field, as shown in FIGS. 11C and 11D, the scanning signal G (1) becomes active during the period in which the polarity of the driving video signal S (a) is positive. As a result, the polarity of the pixel forming portion is positive in the first field. In the second field, the scanning signal G (1) becomes active during the period when the driving video signal S (a) is at the black potential. Here, during the period in which the driving video signal S (a) is in the black potential, the period Tsh appears every two horizontal scanning periods. During these periods, the scanning signal G (1) is as shown in FIG. 11 (d). Becomes active 4 times. Thereby, in the second field, the pixel forming portion approaches the black potential every time the scanning signal G (1) becomes active. In the third field, as shown in FIGS. 12C and 12D, the scanning signal G (1) becomes active during the period in which the polarity of the driving video signal S (a) is negative. As a result, the polarity of the pixel forming portion is negative in the third field. In the fourth field, as in the second field, the scanning signal G (1) becomes active four times during the period in which the driving video signal S (a) is at the black potential. As a result, in the fourth field, the pixel forming portion approaches the black potential every time the scanning signal G (1) becomes active.

  As described above, the change in the polarity of the pixel formation portion during the period of four consecutive fields is “positive, 0 (black), negative, 0 (black)”. In this way, in the pixel forming portion, voltage application (DC voltage application) in one direction is not performed. Similarly, no voltage is applied in one direction to the other pixel formation portions. For this reason, no DC voltage is applied to the liquid crystal layer, and no burn-in or afterimage occurs on the display unit 100.

  In the present embodiment, the black voltage is applied to the source bus lines by short-circuiting adjacent source bus lines. For this reason, the charge accumulated in the wiring capacitance of each source bus line is used to apply the black voltage. Therefore, power consumption does not increase due to the writing of a voltage corresponding to the black voltage to the pixel capacitor Cp. Thereby, a liquid crystal display device capable of displaying an image of the interlace signal itself while suppressing an increase in power consumption is realized.

<3. Modification>
In each of the above embodiments, “2H2F inversion” is described as an example of the driving method. However, the present invention is not limited to this, and the present invention is not limited to this as long as the polarity of each pixel forming portion is inverted every two fields. The invention can be applied. For example, the present invention can be applied to a driving method called “1H2F inversion” as shown in FIG. 14 and a driving method called “3H2F inversion” as shown in FIG. In the case of “1H2F inversion”, the change in polarity of each pixel formation portion during the period of four consecutive fields is as shown in FIG. In the case of “3H2F inversion”, the change in the polarity of each pixel formation portion during the period of four consecutive fields is as shown in FIG. As shown in FIGS. 16 and 17, no voltage is applied in one direction (DC voltage is applied) in any pixel formation portion, and AC driving is performed in continuous four field periods. Yes. For this reason, even if an image of the interlace signal itself is displayed, no burn-in or afterimage occurs on the display unit 100.

  Further, in the second embodiment, it is assumed that a digital image signal DA as shown in FIG. 4B is sent from the display control circuit 200 to the source driver 300, and the adjacent source bus lines are short-circuited ( Black data may be written after charge sharing). This effectively inserts a black image between every other (valid) image data.

In the liquid crystal display device which concerns on the 1st Embodiment of this invention, it is a figure which shows the change of the polarity of each pixel formation part during the period of 4 continuous fields. In the said 1st Embodiment, it is a block diagram which shows the whole structure of a liquid crystal display device. FIG. 3 is a block diagram illustrating a configuration of a source driver in the first embodiment. In the said 1st Embodiment, it is the figure which showed typically the content of the data of the digital image signal. It is a signal waveform diagram for demonstrating the drive method in the said 1st Embodiment. It is a figure which shows the change of the polarity of each pixel formation part in 2H2F inversion. In the said 1st Embodiment, it is a signal waveform diagram which shows the change of the polarity in each field about the drive video signal applied to the source bus line of the odd-numbered column. In the 2nd Embodiment of this invention, it is a block diagram which shows the whole structure of a liquid crystal display device. FIG. 6 is a circuit diagram illustrating a configuration of an output unit of a source driver in the second embodiment. FIG. 6 is a block diagram showing a configuration of a first gate driver in the second embodiment. In the said 2nd Embodiment, it is a signal waveform diagram in the 1st and 2nd field. In the said 2nd Embodiment, it is a signal waveform diagram in the 3rd and 4th field. In the said 2nd Embodiment, it is a signal waveform diagram for demonstrating the production | generation of a scanning signal. It is a figure which shows the change of the polarity of each pixel formation part in 1H2F inversion. It is a figure which shows the change of the polarity of each pixel formation part in 3H2F inversion. It is a figure which shows the change of the polarity of each pixel formation part at the time of applying 1H2F inversion to this invention. It is a figure which shows the change of the polarity of each pixel formation part at the time of applying 3H2F inversion to this invention. It is a figure which shows the change of the polarity in the period of 4 continuous fields in the liquid crystal display device which employ | adopts dot inversion drive. In the conventional example, it is a figure which shows the change of the polarity in the period of 4 continuous fields when the image display by a pseudo interlace system is performed.

Explanation of symbols

DESCRIPTION OF SYMBOLS 100 ... Display part 200 ... Display control circuit 300 ... Source driver (video signal line drive circuit)
400: Gate driver (scanning signal line driving circuit)
500 ... Selector 600 ... Microcomputer 700 ... Backlight control circuit 800 ... Backlight Csh ... Short-circuit control signal DA ... Digital image signal GLj ... Gate bus line (scanning signal line) (j = 1, 2, ..., m)
POL: Polarity inversion signal SLi: Source bus line (video signal line) (i = 1, 2,..., N)

Claims (17)

A plurality of video signal lines for respectively transmitting a plurality of video signals representing an image to be displayed, a plurality of scanning signal lines intersecting with the plurality of video signal lines, the plurality of video signal lines and the plurality of scannings When a scanning signal line that is arranged in a matrix corresponding to each intersection with a signal line and passes through the corresponding intersection is selected, a video signal transmitted by the video signal line that passes through the corresponding intersection is selected. An active matrix type liquid crystal display device having a display unit including a plurality of pixel formation units to be captured as pixel values,
A scanning signal line driving circuit for selectively driving the plurality of scanning signal lines sequentially one by one;
The plurality of video signals are applied to the plurality of video signal lines so that the polarity of the video signal applied to each video signal line is inverted every two vertical scanning periods when each scanning signal line is selected. A video signal line driving circuit;
The voltage of the video signal applied to the plurality of video signal lines when the odd-numbered scanning signal lines are selected and the plurality of video signal lines when the even-numbered scanning signal lines are selected. A liquid crystal display device, comprising: black insertion means for alternately changing a voltage of an applied video signal for each vertical scanning period to a voltage corresponding to black display.   The video signal line driving circuit applies the plurality of video signals to the plurality of video signal lines so that polarities of video signals applied to the plurality of video signal lines are different from each other between adjacent video signal lines. The liquid crystal display device according to claim 1, wherein:   The video signal line driving circuit applies the plurality of video signals to the plurality of video signal lines so that the polarity of the voltage of the video signal applied to each video signal line is inverted every two horizontal scanning periods. The liquid crystal display device according to claim 1, wherein:   The black insertion means displays the voltage of the video signal applied to the plurality of video signal lines in black by short-circuiting the video signal lines to which video signals having different polarities are applied among the plurality of video signal lines. The liquid crystal display device according to any one of claims 1 to 3, wherein a voltage corresponding to the voltage is set.   The black insertion means short-circuits video signal lines adjacent to each other among the plurality of video signal lines, thereby setting the voltage of the video signal applied to the plurality of video signal lines to a voltage corresponding to black display. The liquid crystal display device according to claim 4, wherein the liquid crystal display device is a liquid crystal display device. A signal type determination means for determining whether the type of an image signal sent from the outside to generate the image to be displayed is an interlace signal or a progressive signal;
A backlight for irradiating the display unit with light from the back side;
Further comprising backlight control means for controlling the brightness of light emitted by the backlight,
When the signal type determining unit determines that the type of the image signal is an interlace signal, the backlight control unit determines that the type of the image signal is a progressive signal when the signal type determining unit determines that the type of the image signal is an interlaced signal. The liquid crystal display device according to claim 1, wherein the brightness of the light is made larger than that of the liquid crystal display device.   When the signal type determining unit determines that the type of the image signal is an interlace signal, the backlight control unit determines that the type of the image signal is a progressive signal when the signal type determining unit determines that the type of the image signal is an interlaced signal. The liquid crystal display device according to claim 6, wherein the brightness of the light is doubled. A plurality of video signal lines for respectively transmitting a plurality of video signals representing an image to be displayed, a plurality of scanning signal lines intersecting with the plurality of video signal lines, the plurality of video signal lines and the plurality of scannings When a scanning signal line that is arranged in a matrix corresponding to each intersection with a signal line and passes through the corresponding intersection is selected, a video signal transmitted by the video signal line that passes through the corresponding intersection is selected. A drive circuit of an active matrix type liquid crystal display device including a display unit including a plurality of pixel formation units to be captured as pixel values,
A scanning signal line driving circuit for selectively driving the plurality of scanning signal lines sequentially one by one;
The plurality of video signals are applied to the plurality of video signal lines so that the polarity of the video signal applied to each video signal line is inverted every two vertical scanning periods when each scanning signal line is selected. A video signal line driving circuit;
The voltage of the video signal applied to the plurality of video signal lines when the odd-numbered scanning signal lines are selected and the plurality of video signal lines when the even-numbered scanning signal lines are selected. A drive circuit, comprising: black insertion means for alternately changing the voltage of an applied video signal to a voltage corresponding to black display every vertical scanning period.   The video signal line driving circuit applies the plurality of video signals to the plurality of video signal lines so that polarities of video signals applied to the plurality of video signal lines are different from each other between adjacent video signal lines. The drive circuit according to claim 8, wherein:   The video signal line driving circuit applies the plurality of video signals to the plurality of video signal lines so that the polarity of the voltage of the video signal applied to each video signal line is inverted every two horizontal scanning periods. The drive circuit according to claim 8, wherein:   The black insertion means displays the voltage of the video signal applied to the plurality of video signal lines in black by short-circuiting the video signal lines to which video signals having different polarities are applied among the plurality of video signal lines. The drive circuit according to claim 8, wherein the drive circuit has a voltage corresponding to.   The black insertion means short-circuits video signal lines adjacent to each other among the plurality of video signal lines, thereby setting the voltage of the video signal applied to the plurality of video signal lines to a voltage corresponding to black display. The drive circuit according to claim 11, wherein: A plurality of video signal lines for respectively transmitting a plurality of video signals representing an image to be displayed, a plurality of scanning signal lines intersecting with the plurality of video signal lines, the plurality of video signal lines and the plurality of scannings When a scanning signal line that is arranged in a matrix corresponding to each intersection with a signal line and passes through the corresponding intersection is selected, a video signal transmitted by the video signal line that passes through the corresponding intersection is selected. A driving method of an active matrix type liquid crystal display device including a display unit including a plurality of pixel formation units to be captured as pixel values,
A scanning signal line driving step for sequentially and selectively driving the plurality of scanning signal lines one by one;
The plurality of video signals are applied to the plurality of video signal lines so that the polarity of the video signal applied to each video signal line is inverted every two vertical scanning periods when each scanning signal line is selected. Video signal line driving step;
The voltage of the video signal applied to the plurality of video signal lines when the odd-numbered scanning signal lines are selected and the plurality of video signal lines when the even-numbered scanning signal lines are selected. And a black insertion step of alternately changing the voltage of the video signal to be applied to a voltage corresponding to black display every vertical scanning period.   In the video signal line driving step, the video signals are applied to the video signal lines such that polarities of video signals applied to the video signal lines are different between adjacent video signal lines. The driving method according to claim 13, wherein:   In the video signal line driving step, the plurality of video signals are applied to the plurality of video signal lines so that the polarity of the voltage of the video signal applied to each video signal line is inverted every two horizontal scanning periods. 15. The driving method according to claim 13, wherein the driving method is characterized in that:   In the black insertion step, the video signal voltage applied to the plurality of video signal lines is displayed in black by short-circuiting the video signal lines to which video signals having different polarities are applied among the plurality of video signal lines. The driving method according to any one of claims 13 to 15, wherein the voltage corresponds to   In the black insertion step, adjacent video signal lines among the plurality of video signal lines are short-circuited, whereby the voltage of the video signal applied to the plurality of video signal lines is set to a voltage corresponding to black display. The driving method according to claim 16, wherein:

Images