TWI250602B - Method for testing a substrate and a common clamp used for the method - Google Patents

Method for testing a substrate and a common clamp used for the method Download PDF

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Publication number
TWI250602B
TWI250602B TW93138764A TW93138764A TWI250602B TW I250602 B TWI250602 B TW I250602B TW 93138764 A TW93138764 A TW 93138764A TW 93138764 A TW93138764 A TW 93138764A TW I250602 B TWI250602 B TW I250602B
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Taiwan
Prior art keywords
substrate
test
pressure plate
opening
component
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TW93138764A
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Chinese (zh)
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TW200620517A (en
Inventor
Yen-Kun Chi
Chun-Hao Huang
Tzung-Lin Chuang
Chi-Feng Hung
Chiu-Ping Huang
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Advanced Semiconductor Eng
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Publication of TW200620517A publication Critical patent/TW200620517A/en

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Abstract

According to a method for testing a substrate, a substrate and a common clamp are provided. On an upper surface of the substrate, at least a chip had been disposed. The common clamp has a opening and an elastic protection ring around the opening. When testing, the common clamp and its elastic protection ring are pressed against the upper surface of the substrate, the opening is aligned with the chip to avoid damage of the chip by pressing the common clamp. When the other component is disposed on the upper surface of the substrate, the elastic protection ring can protect the component without damage caused by pressing, and ensure that the plurality of contacts on a bottom surface of the substrate are connected by probes.

Description

12506021250602

【發明所屬之技術領域】 本發明係有關於一種基板測試方法以及其使用之萬用 也I丄特別係有關於一種在半導體封裝製程中封膠之前基 板上攻置複數個元件之基板開/短路測試方法。 【先前技術】 習知半導體產品在封裝過程中需要進行特定之檢測試 驗,例如開/短路測試(open/short test),以確認在個別 封^工作台之良率,並可避免不合袼之物料被誤用後仍被 2績進行封裝作業。習知基板在黏晶之後且在封膠之前係 會,行一開/短路測試,以測試晶片與基板之電^連接狀 况疋否良好,並防止電連接錯誤的晶片被封膠體密封。此 外,在基板上會額外設置有被動元件或其它較小突起狀之 凡件,可增加電性保護、電性功能或特殊應用,以符合不 同需求之半導體封裝產品。 請參閱第1圖,習知之一基板10係具有一上表面η以 及下表面,在遠上表面11上係至少設置有一晶片2〇以 及一被動元件40,在該基板10之該下表面12係形成有複數 個連接端1 3。該晶片2 0之主動面係形成有複數個銲塾2 ^, 該晶片20係以一黏晶材料22黏設於該基板1〇之上表面丨j, 並以複數個銲線30電性連接該些銲墊21至該基板1〇。通常 在封膠之前,會執行一開/短路測試。如第1及3圖所示, 該基板10會放置於一測試機之測試板5〇上,且在該基板1〇 上方係以一壓板100觸壓該基板1〇,為避免該壓板丨〇〇壓傷 該晶片20及該被動元件4〇,該壓板1 〇〇係形成有至少一開BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a substrate testing method and its use. In particular, it relates to a substrate open/short circuit for tapping a plurality of components on a substrate before sealing in a semiconductor packaging process. testing method. [Prior Art] Conventional semiconductor products require specific test tests during the packaging process, such as open/short test, to confirm the yield of individual seals and avoid unsuitable materials. After being misused, it is still packaged by 2 performances. The conventional substrate is subjected to an open/short test after the die bonding and before the sealing, to test whether the connection state of the wafer and the substrate is good, and to prevent the electrically connected wafer from being sealed by the sealant. In addition, passive components or other small protrusions are additionally provided on the substrate to increase electrical protection, electrical functions or special applications to meet different needs of semiconductor package products. Referring to FIG. 1, a substrate 10 has an upper surface η and a lower surface. At least a wafer 2A and a passive component 40 are disposed on the distal surface 11, and the lower surface 12 of the substrate 10 is provided. A plurality of connecting ends 13 are formed. The active surface of the wafer 20 is formed with a plurality of solder pads 2 ^. The wafer 20 is adhered to the upper surface 丨j of the substrate 1 by a die bonding material 22, and is electrically connected by a plurality of bonding wires 30. The pads 21 are to the substrate 1 . An open/short test is usually performed before the seal is applied. As shown in FIGS. 1 and 3, the substrate 10 is placed on a test board 5 of a test machine, and a platen 100 is pressed against the substrate 1A above the substrate 1 to avoid the platen. The wafer 20 and the passive component 4 are crushed, and the pressure plate 1 is formed with at least one opening.

1250602 五、發明說明(2) 口110,其尺寸係大於該晶片20與該被動元件40之尺寸總 合,以在該壓板1 〇 〇觸壓該基板1 0時不會壓傷該i晶片2 〇、 。玄些銲線30與該被動元件4〇,另,該被動元件4〇依產品不 同會變更位置,因此,該壓板1 〇 〇係需設置較大尺寸之該 開口 1 1 0,以配合該被動元件4 〇之可能的位置變動。請參 閱第2及3圖,由於該壓板1〇〇之該開口11〇尺寸較大,因此 在進行測試時,該壓板1 〇 〇並不能均勻地觸壓該基板1 〇之 ,上表面11,導致在該基板1〇之該下表面12無法被平整地 壓迫在該測試板5 〇上之複數個探測件5丨上,導致部分之該 些連接端1 3,特別是在該開口 11 〇區域内之該些連接端 13 ’無法被該測試板50之該些探測件51探觸,而呈電性斷 路使付開/斷路測試之結果不破實。目前的改善作法為 針對不同種類的半導體封裝產品,依被動元件之位置變化 设計出個別之壓板,另不同的壓板具有對應被動元件位置 的小凹穴’可使得上述用以對準晶片之開口尺寸能有效縮 小,這樣雖然可以防止探測失誤的發生,在多樣化產品的 ,農過程中,用以特定產品之壓板要經常更換,會降低測 试效率。甚者,一旦壓板裝錯或忘了作對應的更換,常使 整批產品之損壞,造成生產良率降低,此乃為現行遭遇到 的問題。 【發明内容】 為了解決上述或其它之問題,本發明之主要目的在於 提供一種基板測試方法以及在該方法中使用之萬用壓板, 其係提供一基板,該基板之一上表面係設置有一至少晶1250602 V. DESCRIPTION OF THE INVENTION (2) Port 110 having a size greater than the size of the wafer 20 and the passive component 40 to prevent the i-chip 2 from being crushed when the platen 1 is pressed against the substrate 10 Hey, . The conductive wire 30 is connected to the passive component 4, and the passive component 4 is changed according to the product. Therefore, the pressure plate 1 needs to be provided with a larger size of the opening 110 to match the passive The possible positional change of component 4. Referring to Figures 2 and 3, since the opening 11 of the platen 1 is large in size, the platen 1 does not uniformly touch the substrate 1 and the upper surface 11 during the test. Resulting that the lower surface 12 of the substrate 1 cannot be flatly pressed onto the plurality of detecting members 5 on the test board 5, resulting in a portion of the connecting ends 13, particularly in the opening 11 The connecting ends 13' are not able to be detected by the detecting members 51 of the test board 50, and the electrical disconnection makes the result of the pay-open/open-circuit test unbreakable. The current improvement is to design individual platens for different types of semiconductor package products according to the positional changes of the passive components, and different platens have small recesses corresponding to the position of the passive components to enable the above-mentioned openings for aligning the wafers. The size can be effectively reduced, so that although the detection error can be prevented, in the diversified product, the agricultural process, the pressure plate for the specific product should be replaced frequently, which will reduce the test efficiency. In addition, once the platen is incorrectly installed or forgotten for replacement, the entire batch of products is often damaged, resulting in a decrease in production yield. This is a problem currently encountered. SUMMARY OF THE INVENTION In order to solve the above problems, the main object of the present invention is to provide a substrate testing method and a universal pressure plate used in the method, which provides a substrate, and one of the upper surfaces of the substrate is provided with at least one surface. crystal

1250602_____ 五、發明說明(3) """"" " " ----— 片,该萬用壓板係具有一可對準該晶片之開口以及一 =護環^該開口之周邊係形成有—缺口,該彈性保護環係 认置於該缺口,因此,該萬用壓板及其彈性保護 試時壓迫該基板之上表面,使得在該基板之下表面之連接 墊能被一測試板之複數個探測件探觸,以進行正確的開/ 斷路測試。另外,利用在該缺口之彈性保護環可防止在該 基板上之被動元件或其它元件被該壓板直接壓迫而損傷。 本發明之次一目的在於提供一種基板測試方法,、提供 之一基板係設置有一第一元件與一第二元件,其中該第一 凡件以高於該第二元件為較佳,並在該基板上提供一萬用 壓板,其中該萬用壓板係具有至少一開口以及一彈性保護 膠,該開口之周邊係形成有一凹陷區,該彈性详護膠係設 置於該凹陷區,在測試時,該萬用壓板係觸壓該基板,該 第一元件係被對準在該萬用壓板之該開口内,該第二元件 係被該彈性保護膠彈性觸壓,故可以在較小開口尺寸的條 件下均勻壓迫該基板,不需要在測試過程經常更換該壓 板。 、 呈依據本發明之基板測試方法,提供一基板,該基板係 具有一上表面以及一下表面,至少一晶片係設置於該基板 之$上表面,該基板之該下表面係形成有複數個連接端; 運送該基板至一測試板上;並且,提供一萬用壓板在該基 f上,其中該萬用壓板係具有至少一開口以及一彈性保護 % ’該開口之周邊係形成有一缺口,該彈性保護環係設置 於遠缺口;以該萬用壓板及其彈性保護環觸壓焱基板之上1250602_____ V. Invention Description (3) """"""" ----- The sheet has an opening that can be aligned with the wafer and a = guard ring ^ The periphery of the opening is formed with a notch, and the elastic protection ring is disposed on the notch. Therefore, the universal pressure plate and the elastic protection test press the upper surface of the substrate, so that the connection pad on the lower surface of the substrate can It is probed by a plurality of detectors of a test board for proper open/break test. In addition, the use of the resilient guard ring in the recess prevents passive components or other components on the substrate from being directly damaged by the pressure plate. A second object of the present invention is to provide a substrate testing method, wherein a substrate is provided with a first component and a second component, wherein the first component is preferably higher than the second component, and A 10,000-type pressure plate is provided on the substrate, wherein the universal pressure plate has at least one opening and an elastic protective glue, and a periphery of the opening is formed with a recessed portion, and the elastic adhesive is disposed in the recessed area. The universal pressure plate touches the substrate, the first component is aligned in the opening of the universal pressure plate, and the second component is elastically pressed by the elastic protective rubber, so that the opening can be small The substrate is uniformly pressed under the conditions, and the platen does not need to be frequently replaced during the test. According to the substrate testing method of the present invention, a substrate is provided, the substrate having an upper surface and a lower surface, at least one wafer is disposed on the upper surface of the substrate, and the lower surface of the substrate is formed with a plurality of connections Carrying the substrate to a test board; and providing a 10,000-type pressure plate on the base f, wherein the universal pressure plate has at least one opening and a spring protection %' The elastic protection ring is disposed on the far-notch; the universal pressure plate and the elastic protection ring thereof are pressed onto the substrate

第10頁 1250602Page 10 1250602

表面以使忒基板之該些連接端導接至該測試板,且該晶 片係被對準在該萬用壓板之該開口内。 【實施方式】 明參閱所附圖式,本發明將列舉以下之實施例說明: 第4至6圖係有關於本發明在第一具體實施例中所揭示 =一種基板測試方法,其係可運用在半導體封裝製程中並 可具體實施在黏晶步驟之後與封膠步驟之前。首先,請參 閱第4圖,提供一基板10,該基板1〇係具有一上表面u以 及一下表面1 2。在本實施例中,該基板丨〇係具有雙面導通 之$路結構並可為複數個單元之集合體(圖未繪出),對應 於每一單元,至少一晶片2〇係以一黏晶材料22設置於該基 板10之該上表面11,在本實施例中,其係為在該基板1〇上 之第一元件,並且複數個銲線30或其它電導接元件係可電 性連接該晶片20之複數個銲墊21至該基板1〇。此外,至少 一被動元件4 0或其它較小突起元件亦設置於該基板丨〇之該 上表面11,其係為在該基板1 〇上之第二元件,其中該被動 元件4 0應低於該晶片2 0或是低於該些銲線3 〇之弧高。另, 該基板10之一下表面12係形成有複數個連接端13,例如 接墊。 之後’請參閱第5圖,運送該基板10至一測試機台之 測試板5 0上’該測試板5 0係具有複數個探測件5丨,例如探 針,用以探觸該基板10之該些連接端13 ;並且,提供_ ^ 用壓板200在該基板1〇上,請參閱第5及7圖,其中該萬用 壓板20 0係具有至少一開口2 10以及一彈性保護環22〇,The surface is such that the terminals of the germanium substrate are routed to the test board and the wafer is aligned within the opening of the universal press plate. [Embodiment] Referring to the drawings, the present invention will be described by way of the following embodiments: Figures 4 to 6 are related to the present invention disclosed in the first embodiment = a substrate testing method, which can be applied In the semiconductor packaging process, and after the bonding step and before the sealing step. First, referring to Fig. 4, a substrate 10 having an upper surface u and a lower surface 12 is provided. In this embodiment, the substrate has a two-way conductive structure and can be a collection of a plurality of cells (not shown). For each cell, at least one of the wafers is bonded. The crystal material 22 is disposed on the upper surface 11 of the substrate 10. In the embodiment, it is a first component on the substrate 1 , and a plurality of bonding wires 30 or other electrically conductive components are electrically connected. A plurality of pads 21 of the wafer 20 are bonded to the substrate. In addition, at least one passive component 40 or other smaller protruding component is also disposed on the upper surface 11 of the substrate, which is a second component on the substrate 1 , wherein the passive component 40 should be lower than The wafer 20 is either lower than the arc height of the bonding wires 3 . Further, a lower surface 12 of the substrate 10 is formed with a plurality of connecting ends 13, such as pads. Then, please refer to FIG. 5, the substrate 10 is transported to the test board 50 of a test machine. The test board 50 has a plurality of detecting members 5, for example, probes for detecting the substrate 10. The connecting end 13 is provided with a pressing plate 200 on the substrate 1 , see FIGS. 5 and 7 , wherein the universal pressing plate 20 0 has at least one opening 2 10 and an elastic protection ring 22〇. ,

第11頁 1250602 五、發明說明(5) 彈性保護環2 20係可為矽膠材質。該彈性保護環22〇並具有 一在其下表面之凹陷區’在本實施例中,該凹陷區係為形 成在該開口 2 1 0之周邊之一缺口 2 3 0,該彈性保護環2 2 〇係 設置於該缺口 230。 請參閱第6圖,在一測試過程中,其係為開/短路測 減’以或萬用壓板2 0 0及其彈性保護環2 2 〇觸壓該基板1 〇之 β亥上表面11,以使該基板1 〇之該些連接端1 3能蜂實被壓迫 導接至4測试板5 0之遠些棟測件5 1以執行該開/斷路測 。式’其中’或晶片2 0與該些銲線3 〇係被對準在該萬用壓板 200之該開口 210内,而該彈性保護環220係彈性壓迫該被 動元件40,以避免該萬用壓板200壓傷該被動元件4〇。 因此,利用該萬用壓板20〇具有在該開口 21 〇周邊且在 該缺口 230内之彈性保護環220,當該萬用壓板2〇〇與該彈 性保護環220觸壓該基板10之該上表面u,該味動元件4〇 與该些銲線3 0係不被該萬用壓板2 〇 〇之硬質本體直接壓 迫,以減少損傷。此外,請比對如第3圖之習知屋板丨〇 〇與 本發明第一具體實施例之萬用壓板2〇〇,該萬用壓板2〇〇^ 開口 210尺寸可更接近該晶片3〇之尺寸,使其些許大於該 晶片30之尺寸,故能小於習知壓板丨〇〇之開口丨丨〇尺寸,以 增加壓合面積。同時,加上其彈性保護環22〇之輔助彈性 壓迫,達到均勻之壓迫力量,可使該基板1〇之該些連接端 13被該測試板50之探測件51確實探測,以進行正"讀的開/ 斷路測忒。§本發明之基板測試方法具體實施運用在半導 體封裝製程時,可執行在一晶片設置步驟之後且在一封膠Page 11 1250602 V. INSTRUCTIONS (5) Elastic protection ring 2 The 20 series can be made of silicone. The elastic protection ring 22 has a recessed portion on the lower surface thereof. In the embodiment, the recessed portion is formed by a notch 2 3 0 around the opening 210, and the elastic protection ring 2 2 The tether is disposed in the gap 230. Please refer to FIG. 6 , in the course of a test, it is an open/short measurement minus or a universal pressure plate 200 and its elastic protection ring 2 2 〇 to touch the upper surface 11 of the substrate 1 , The connection terminals 13 of the substrate 1 can be pressed and guided to the remote test pieces 51 of the 4 test boards 50 to perform the on/off test. The 'where' or wafer 20 and the bonding wires 3 are aligned in the opening 210 of the universal platen 200, and the elastic protection ring 220 elastically presses the passive component 40 to avoid the universal use. The pressure plate 200 crushes the passive component 4〇. Therefore, the universal pressure plate 20 has an elastic protection ring 220 around the opening 21 且 and in the notch 230, when the universal pressure plate 2 〇〇 and the elastic protection ring 220 touch the substrate 10 The surface u, the agitating element 4〇 and the bonding wires 30 are not directly pressed by the hard body of the universal platen 2 to reduce damage. In addition, please compare the conventional housing plate as shown in FIG. 3 with the universal pressure plate 2 of the first embodiment of the present invention, and the universal pressure plate 2 〇〇 ^ opening 210 can be closer to the wafer 3 The size of the crucible is somewhat larger than the size of the wafer 30, so that it can be smaller than the opening crucible size of the conventional platen to increase the lamination area. At the same time, with the auxiliary elastic compression of the elastic protection ring 22〇, a uniform pressing force is achieved, so that the connecting ends 13 of the substrate 1 are reliably detected by the detecting member 51 of the test board 50 to perform positive " Read open/open circuit test. § The substrate test method of the present invention is embodied in a semiconductor package process, and can be performed after a wafer setting step and in a glue

第12頁 五、發明說明(6) 10 Ξ ί4以一開/斷路測試進行測試該晶片20與該基板 各式藉_ 接狀況,本發明所提供之萬用壓板200在測試 置,仂π ί基板10時’即使被動元件40被設置於不同位 的方便性?要在製程中更換該萬用壓板200,具有製造上 躐夕ΐ 2,本發明之基板測試方法除了可以解決習知在封 侔懕1沾開/斷路測試過程中發生的探觸不確實與被動元 1=1問題,尚可運用在不同封裝類型之基板測試。請 ^ ,,依據本發明之第二具體實施例,提供一基板 ,1基板310係具有一上表面311以及一下表面312,該 土板31 0係為一軟性電路板、一陶瓷電路板或一印刷電路 板。該基板3 10之該上表面3 11上係至少設置有一第一元件 320與一第二元件330,其中該第一元件32〇係較高於該第 二το件330。在本實施例中,該第一元件32〇係為一覆晶晶 片’其係以凸塊321接合至該基板31〇 ;而該第二元件“ο 係可為鮮球、凸塊或其它突出元件。另,在該基板31〇之 下表面312可形成有複數個連接端313。在測試過程中,先 提供一萬用壓板40 0在該基板310上,其中該萬用壓板4〇〇 係具有至少一對應於該第一元件320之開口 41 〇以及一彈性 保護膠420,該開口410之周邊係形成有一凹陷區43〇,今 彈性保護膠420係設置於該凹陷區430。在測試時,該萬Λ用 壓板4 0 0及其該彈性保護膠4 2 0係觸壓該基板3丨〇之該/上表 面3 11,此時,該第一元件3 2 0係被對準在該萬用壓板4 〇 〇 之該開口 41 0内,而該第二元件3 3 0係被該彈性保護膠4 2 〇Page 12 V. Invention Description (6) 10 Ξ ί 4 ί ί ί ί ί ί ί ί ί ί ί ί 以 ί ί ί ί ί ί ί ί ί ί ί ί ί ί ί ί ί ί ί ί ί ί ί ί ί ί ί ί ί ί ί ί ί ί ί ί In the case of the substrate 10, 'even if the passive component 40 is disposed in a different position. To replace the universal pressure plate 200 in the process, the substrate test method of the present invention can be solved in addition to the conventional method. The detection of the 懕1 open/open circuit test is not true and the passive element 1=1 problem can be used in the substrate test of different package types. According to a second embodiment of the present invention, a substrate is provided. The substrate 310 has an upper surface 311 and a lower surface 312. The earth plate 31 0 is a flexible circuit board, a ceramic circuit board or a A printed circuit board. The upper surface 3 11 of the substrate 3 10 is provided with at least a first component 320 and a second component 330, wherein the first component 32 is higher than the second component 330. In this embodiment, the first component 32 is a flip chip, which is bonded to the substrate 31 by bumps 321; and the second component can be a fresh ball, a bump, or other protrusion. In addition, a plurality of connecting ends 313 may be formed on the lower surface 312 of the substrate 31. During the test, a ten thousand pressing plate 40 is first provided on the substrate 310, wherein the universal pressing plate 4 is There is at least one opening 41 对应 corresponding to the first component 320 and an elastic protective adhesive 420. The periphery of the opening 410 is formed with a recessed area 43. The elastic protective adhesive 420 is disposed in the recessed area 430. The enamel platen 400 and the elastic protective adhesive 420 are pressed against the/upper surface 311 of the substrate 3, at which time the first component 320 is aligned The universal platen 4 is in the opening 41 0, and the second element 3 3 0 is the elastic protective adhesive 4 2 〇

12506021250602

五、發明說明(7) 彈性壓觸,;♦ z, 笛一—杜建到測試時均勻壓迫該基板31〇與避免損傷該 ^ ^ 之功效’該萬用屢板40 0可適用該第二元件 不置於不同位置之該基板3 1 0,在該基板測試過程以 及包s 4基板測試操作之半導體封裝製程中,不需要更換 壓板。 、本發明之保護範圍當視後附之申請專利範圍所界定者 為準’任何熟知此項技藝者,在不脫離本發明之精神和範 圍内所作之任何變化與修改,均屬於本發明之保護範圍。V. Description of invention (7) Elastic pressure contact; ♦ z, flute-Du Jian to evenly press the substrate 31〇 during testing and avoid the damage of the ^ ^ The universal board 40 0 can be applied to the second The substrate 310 is not placed in a different position, and in the semiconductor packaging process of the substrate testing process and the substrate testing operation, there is no need to replace the pressure plate. The scope of the present invention is defined by the scope of the appended claims. Any changes and modifications made without departing from the spirit and scope of the present invention are protected by the present invention. range.

1250602 r —-— 圖式簡單說明 【圖式簡單說明】 第1圖:在習知基板測試方法+ 截面示意圖; ,一 第圖·在習知基板測試方法中 J進2開/短路測試時之截面’該 第3圖:在習知基板測試方法 圖 意圖; T ’所 第4圖·依據本發明之基板測錢 中所提供之基板之截面示意圖;〆 第5圖:依據本發明之基板測試 測試設備内之截面示意圖; ' 第6圖·依據本發明之基板測試方法 時之截面示意圖; 第7圖:依據本發明之基板測試方法 之底面示意圖;及 第8圖:依據本發明之基板測試方法 中一基板在測試狀態被一萬用壓板壓 基板在一測試機内之 基板在被一壓板壓迫 ► 提供之壓板之底面示 ,在第一具體實施例 ,該基板在運送至一 ’該基板在測試狀態 ’所提供之萬用壓板 j ,在第二真體實施例 迫時之截面示意圖。 元件符號簡單說明: 10 13 基板 連接端 11 上表面 20 晶片 21 銲墊 30 銲線 40 被動元件 50 測試板 51 探測件 12 下表面 22 黏晶松1250602 r —-— Brief description of the drawing [Simplified description of the drawing] Fig. 1: In the conventional substrate test method + sectional view; , a picture · In the conventional substrate test method, J input 2 open / short circuit test Section 3: FIG. 3 is a schematic view of a conventional substrate test method; FIG. 4 is a cross-sectional view of a substrate provided in the substrate measurement according to the present invention; FIG. 5: substrate test according to the present invention A schematic cross-sectional view of the test apparatus; 'Fig. 6 is a schematic cross-sectional view of the substrate test method according to the present invention; Fig. 7 is a schematic view of the bottom surface of the substrate test method according to the present invention; and Fig. 8: Substrate test according to the present invention In the method, a substrate is pressed by a 10,000-plate substrate in a test state, and a substrate in a test machine is pressed on a bottom surface of a press plate provided by a press plate. In the first embodiment, the substrate is transported to a substrate. The test plate of the test state is provided as a schematic cross-sectional view of the second body embodiment when forced. Brief description of component symbols: 10 13 Substrate Connection end 11 Upper surface 20 Wafer 21 Solder pad 30 Bond wire 40 Passive component 50 Test board 51 Probe 12 Lower surface 22 Adhesive

第15頁 1250602 圖式簡單說明 1 0 0 壓板 110 開口 200 230 萬用壓板 缺口 210 開口 220 彈性保護環 310 基板 311 上表面 312 下表面 313 330 連接端 第二元件 320 第一元件 321 凸塊 400 430 萬用壓板 凹陷區 410 開口 420 彈性保護膠 ΦPage 15 1250602 Schematic description 1 0 0 Platen 110 Opening 200 230 million Platen notch 210 Opening 220 Elastic protection ring 310 Substrate 311 Upper surface 312 Lower surface 313 330 Connection end Second element 320 First element 321 Bump 400 430 Universal pressure plate recessed area 410 opening 420 elastic protective rubber Φ

Hi·· 第16頁Hi·· Page 16

Claims (1)

1250602 六、申請專利範圍 【申請專利範圍】 1、 一種基板測試方法,包含: 提供一基板,該基板係具有一上表面以及一下表面, 至少一晶片係設置於該基板之該上表面,該基板之一下表 面係形成有複數個連接端; 運送該基板至一測試板上; 提供一萬用壓板在該基板上,其中該萬用壓板係具有 至少一開口以及一彈性保護環,該開口之周邊係形成有一 缺口 ’該彈性保護環係設置於該缺口;及 以該萬用壓板及其彈性保護環壓迫該基板之該上表 面’以使該基板之該些連接端導接至該測試板,且該^ 係被對準容置於該萬用壓板之該開口内。 曰 2、 如申凊專利範圍第1項所述之基板測試方法,其另包 含有·藉由該測試板之導接,對該基板與該晶片執行一 開/短路測試(open/short test )。 >3、如申請專利範圍第2項所述之基板測試方法,其中 該開/短路測試之後,另包含有一封膠步驟。 、 4、 如申請專利範圍第1項所述之基板測試方法,i 彈性保護環係為矽膠材質。 八 ^ 5、 如申請專利範圍第1項所述之基板測試方法,盆中 基板之上表面係設置有至少一被動元件。 ’、μ 6、 、如申請專利範圍第5項所述之基板測試方法,其中 上述之壓迫步驟中,該彈性保護環係壓觸至該被動元件。 7、 如申請專利範圍第1項所述之基板測試方法,其中該 1250602 六、申請專利範圍 基板之上表面係設置有複數個銲線,其係電性連接該曰 與該基板。 ' ^ θθ 8、 如申請專利範圍第7項所述之基板測試方法,其中該 萬用壓板之該開口係大於該晶片,使得該晶片與該些銲線 可被容納於該萬用壓板之該開口内。 9、 一種適用於基板測試之萬用壓板,其係用以壓迫一設 置有至少一晶片之基板,該萬用壓板係具有至少一開口以 及彈性保護環’該開口之周邊係形成有一缺口,該彈性 保護環係設置於該缺口。 1 〇、如申請專利範圍第9項所述之萬用壓板,其中該彈性 保護環係為矽膠材質。 11、一種基板測試方法,包含: 提供一基板,該基板係至少設置有一第一元件與一第 二元件;及 提供一萬用壓板在該基板上,其中該萬用壓板係具有 至少一開口以及一彈性保護膠,該開口之周邊係形成有一 凹陷區’該彈性保護膠係設置於該凹陷區;1250602 VI. Patent Application Range [Application Patent Scope] 1. A substrate testing method comprising: providing a substrate having an upper surface and a lower surface, at least one wafer being disposed on the upper surface of the substrate, the substrate One of the lower surface is formed with a plurality of connecting ends; the substrate is transported to a test board; and a 10,000 pressure plate is provided on the substrate, wherein the universal pressure plate has at least one opening and an elastic protection ring, the periphery of the opening Forming a notch 'the elastic protection ring is disposed on the notch; and pressing the upper surface of the substrate with the universal pressure plate and the elastic protection ring thereof to guide the connection ends of the substrate to the test board, And the system is placed in the opening of the universal pressure plate. The substrate testing method of claim 1, further comprising: performing an open/short test on the substrate and the wafer by the guiding of the test board. . > 3. The substrate test method of claim 2, wherein after the open/short test, a gel step is additionally included. 4. For the substrate test method described in claim 1, the elastic protection ring is made of silicone. The substrate test method of claim 1, wherein the upper surface of the substrate in the basin is provided with at least one passive component. The substrate test method of claim 5, wherein in the pressing step, the elastic protection ring is pressed against the passive component. 7. The substrate testing method according to claim 1, wherein the surface of the substrate is provided with a plurality of bonding wires electrically connected to the substrate and the substrate. The substrate test method of claim 7, wherein the opening of the universal pressure plate is larger than the wafer, so that the wafer and the bonding wires can be accommodated in the universal pressure plate. Inside the opening. 9. A universal pressure plate suitable for substrate testing, for pressing a substrate provided with at least one wafer, the universal pressure plate having at least one opening and an elastic protection ring, wherein a periphery of the opening is formed with a notch, An elastic protection ring is disposed in the gap. 1 . The universal pressure plate according to claim 9 , wherein the elastic protection ring is made of silicone rubber. 11. A substrate testing method comprising: providing a substrate, the substrate being provided with at least a first component and a second component; and providing a universal pressure plate on the substrate, wherein the universal pressure plate has at least one opening and An elastic protective adhesive, the periphery of the opening is formed with a recessed area, wherein the elastic protective adhesive is disposed in the recessed area; 、 在測試時,該萬用壓板係壓迫該基板,該第一元件係 ^對準容置於該萬用壓板之該開口内,該第二元件係被該 彈性保護膠彈性壓觸。 1 2、如申請專利範圍第丨丨項所述之基板測試方法,其另 包含有:對該基板執行一開/短路測試(〇pen/sh〇rt test)。 1 3 '如申請專利範圍第丨丨項所述之基板測試方法,其中In the test, the universal pressing plate presses the substrate, and the first component is aligned and received in the opening of the universal pressure plate, and the second component is elastically pressed by the elastic protective adhesive. 1 . The substrate testing method according to claim 2, further comprising: performing an open/short test on the substrate (〇pen/sh〇rt test). 1 3 'A substrate test method as described in the scope of the patent application, wherein 第18頁 1250602 _________ 六、申請專利範圍 在該開/短路測試之後,另包含有一封膠步驟。 1 4、如申請專利範圍第丨丨項所述之基板測試方法,其中 $亥彈性保護膠係為石夕膠材質。 1 5、如申請專利範圍第i丨項所述之基板測試方法,其中 該第一元件係為一晶片。 1 6、如申請專利範圍第1 1或1 5項所述之基板測試方法, 其中該第二元件係選自於被動元件、銲球、凸塊之其中之 — 〇 、如申請專利範圍第丨丨項所述之基板測試方法,其中 該第一元件係較高於該第二元件。Page 18 1250602 _________ VI. Scope of Application After the open/short test, another step is included. 1 . The substrate testing method as claimed in claim 3, wherein the protective elastic adhesive is made of Shishijiao. The substrate testing method of claim 1, wherein the first component is a wafer. The substrate testing method according to claim 1 or claim 5, wherein the second component is selected from the group consisting of passive components, solder balls, and bumps - 〇, as in the scope of the patent application The substrate testing method of item, wherein the first component is higher than the second component. 第19頁Page 19
TW93138764A 2004-12-14 2004-12-14 Method for testing a substrate and a common clamp used for the method TWI250602B (en)

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