TWI246156B - Method for preventing dishing effect on top of dual damascene structure - Google Patents

Abstract

The present invention provides a method for preventing dishing effect on top of dual damascene structure, in which the semiconductor chip comprises a substrate; a first dielectric configured on the wordline conductive substrate; a dual damascene hole configured in the dielectric and through the substrate surface; a barrier layer covering the surface of the first dielectric, the sidewall surface in the dual damascene hole, and the bottom surface in the dual damascene hole; and, forming a copper metal layer on the barrier layer, and filling up the dual damascene hole to form the dual damascene structure. The present invention is first to conduct a first chemical mechanical polishing (CMP) process to remove part of the copper metal layer, and stop the CMP process at the surface of the barrier layer; next, forming a photoresist layer on the top surface of the dual damascene structure; after removing the barrier layer not covered by the photoresist layer, stripping the photoresist layer; finally, conducting a second CMP process to remove part of the copper metal layer, so the surface of the copper metal layer on top of the dual damascene structure is approximately leveled with the surface of the dielectric.

Description

1246156 V. Description of the Invention (1) Field of the Invention The present invention provides a method for avoiding the occurrence of a depression at the top of a dual damascene structure 'to avoid early breakdown of a capacitor element formed on the dual damascene structure. Background description The dual damascene process (dual damascene pr occess) is a method capable of forming a metal wire and a plug (P 1 U g) stacked structure at the same time. The 'dual damascene structure is used to connect the various layers in a semiconductor wafer. The different components and wires are separated from other components by using inter_layer dielectrics around them. Because in the preparation of the dual mosaic structure, a chemical machine = chemical mechanical polish (CMP)

The surface of the conductor wafer becomes very flat, which is very conducive to the subsequent processes such as deposition and photo-1 ithography to prepare well-structured = heavy metal interconnects (multiievei interc0nnects). Therefore, the double inlay structure is It is widely used in the manufacturing process of integrated circuits. With the development of integrated circuits becoming increasingly sophisticated and complex, how to improve the yield of the dual-mosaic structure is an important issue in the integrated circuit manufacturing process. Figure 4 to Figure 4 of Figure 4's Figure 1 to Figure 4 for the conventional production of metal capacitors

1246156 V. Description of the invention (2) Schematic diagram of 28. As shown in FIG. 1, a semiconductor wafer includes a substrate 12, a first dielectric layer composed of silicon dioxide, and 4 is disposed on the substrate u, and is formed by a plug hole and a wire groove. The stacked dual damascene holes i6 are disposed in the first dielectric layer 14 and reach the surface of the substrate 12. As shown in Figure 2, the conventional method for making a metal capacitor 28 is to form a barrier layer 18 on the surface of the semiconductor wafer 10, and cover the surface of the first dielectric layer 4 and the double inlay 16 holes. A sidewall and bottom surface is then subjected to a physical seed deposition (PVS) process (physicai vapor depositio ^) to form a copper seed layer on the surface of the barrier layer 18 (not shown) ). Subsequently, a wet copper plating (Ecp) process is used to form a copper metal layer 20 on the surface of the barrier layer 18 copperΐ ί and fill the double damascene holes 16 to form another inlay. Structure 2 2. The barrier layer 18 is composed of a button (τ) metal, titanium (τ 1 N), titanium (T 1), or refractory metal material, and a first-chemical mechanical polishing (CMP) system is used. The process stops = the first and the first-chemical mechanical research. "Copper is all acoustic 20 # & 2 electrical layer 14 table to make the double mosaic structure 22 on the top ^ As shown in Figure 4, in Fengdao /, Λ ΛI shield 1 4 surface Tangent. Finally; silicon nitride, silicon, silicon, silicon, silicon, silicon, silicon, silicon, silicon, silicon, silicon, silicon, silicon, silicon, silicon, silicon, silicon, silicon, silicon, silicon, silicon, silicon, silicon, silicon, silicon, silicon, silicon, etc. A taste surface forms a second dielectric d composed of ONO structure material, disordered silicon or other dielectric constant material

1246156 V. Description of the invention (3) A metal layer 26 is formed in a predetermined area on the second dielectric layer 24, so that the copper metal layer 20, the second dielectric layer 24, and the metal layer 26 form a metal. Capacitance 28 ° However, in the conventional method for manufacturing a metal capacitor 28, the polishing rate of the copper metal layer 20 is higher than that of the barrier layer 18, so after the first chemical mechanical polishing process is completed, the dual mosaic structure The surface of the copper metal layer 20 in the center of the 2 2 will be lower than the surface of the first dielectric layer 14, resulting in the occurrence of dishing effects. At the same time, this uneven surface will cause bumps of the barrier layer 18 to be generated at the junction of the first dielectric layer 14 and the copper metal layer 20, which will cause tip discharge and electric field concentration, etc., and degrade the second dielectric. Layer 24, which caused the early collapse of the metal capacitor 28 component. SUMMARY OF THE INVENTION Therefore, the main object of the present invention is to provide a method for preventing a depression phenomenon from occurring on the top of a dual damascene structure when manufacturing a metal capacitor, so as to avoid the problems of the conventional manufacturing method mentioned above.

In a preferred embodiment of the present invention, the semiconductor wafer includes a substrate, a first dielectric layer is disposed on the substrate, and a dual damascene hole is disposed in the first dielectric layer and accessible to the substrate. On the surface of the substrate, a barrier layer covers the surface of the first dielectric layer, the sidewall surface in the double damascene hole and the bottom surface in the double damascene hole, and a copper metal layer.

Page 7 1246156 V. Description of the invention The invention is partially due to the second CMP on the double photoresistor layer, the copper on the semiconductor layer and the metal dielectric (4) barrier layer. The double mosaic hole is filled and filled to form the double mosaic structure. A first chemical mechanical polishing (CMP) process is performed to remove the copper metal layer and stop the CMP on the surface of the barrier layer. A photoresist layer is formed on the top surface of the damascene structure, and the photoresist layer is stripped after removing the uncovered barrier layer. Then, a part of the copper metal layer is removed, so that the surface of the top metal layer of the dual damascene structure is approximately aligned with the surface of the first dielectric layer. Finally, a second dielectric layer composed of a 100N structure material, silicon nitride, or other materials is formed on the surface of the wafer, and a metal layer is formed in a region above the second dielectric layer to make the copper metal layer and the second dielectric The electrical layer forms a metal capacitor. Since the manufacturing method of the present invention can avoid the dishing effect caused by the different polishing rates of the copper metal layer and the barrier layer, the surface of the copper metal layer on the top of the dual damascene structure can be approximately the same as the first dielectric. Under the premise that the surface of the layer is cut, no bumps will be generated at the interface between the first dielectric layer and the copper metal layer, so that the phenomenon of component collapse caused by electric field concentration can be effectively avoided, and the service life and reliability of the product can be relatively extended. Detailed description of the invention Please refer to FIG. 5 to FIG. 10, which are schematic diagrams of a method for avoiding the occurrence of a depression at the top of the dual damascene structure 52 when the metal capacitor 62 is manufactured according to the present invention. As shown in Figure 5, the semiconductor wafer 40 contains a substrate

Page 8 1246156 V. Description of the invention (5) Bottom 42, a first dielectric layer 44 composed of silicon dioxide is disposed on the substrate 42, and a stack of a plug hole and a wire groove is formed. A dual damascene hoi e 46 is disposed in the first dielectric layer 44 and reaches the surface of the substrate 42. As shown in FIG. 6, in the method of the present invention, a barrier layer 48 is first formed to cover the surface of the first dielectric layer 4 4, the side wall and the bottom surface in the double damascene hole 46, and then a copper seed layer (seed layer) physical vapor deposition (PVD) process to form a copper seed layer (not shown) on the surface of the barrier layer 48 'followed by a wet copper electrical deposit (ECP) In the process, a copper metal layer 50 is formed on the surface of the barrier layer 48 and the copper seed layer, and the double damascene holes 46 are filled to form a double damascene structure 52. The barrier layer 48 is composed of a button (Ta) metal, a tantalum nitride (TaN), titanium nitride (ΠN), titanium (Ti), or a refractory metal material. Then, as shown in FIG. The first chemical wind she went to the soil w Department of the Eight-days production of Lili ® to chemical mechanical polishing (CMP) r.,, ~ ~ Using the barrier layer 48 as a stop layer, so that A chemical machine He Yan MM 4 «矣 品 夕 你 '闰 \ said-the grinding process stops on the surface of the barrier layer 48. Then, as shown in FIG. 8, a photoresist layer 58 is formed on the dual damascene, and an etching process is used: f 52 top and the surface is covered with a y barrier layer 48. As shown in Figure 9 = the second photoresist layer 58 is not removed in the second soil, and then a second chemical mechanical polishing process is performed. After the photoresist layer 58 is used, M r0 * you furnace Rishi R 9 primary I f M Remove part of the copper metal shield 5 0 ′ and make the double surface 肷 ,,, and mouth structure 5 2 on the top of the copper vow 1 ^ The metal layer 50 surface is approximately aligned

1246156 V. Description of the invention (6) On the surface of the first dielectric layer 4 4. Finally, as shown in FIG. 10, a second dielectric layer 54 composed of an ONO structure material, silicon nitride, or other high dielectric constant material is formed on the surface of the semiconductor wafer 40, and the second dielectric layer 54 is formed on the second dielectric layer 54. A metal layer 60 is formed in a predetermined area, so that the copper metal layer 50, the second dielectric layer 54 and the metal layer 60 form a metal capacitor 62. Compared with the conventional process of manufacturing a barrier layer outside the range of the first chemical-mechanical polishing of the metal-embedded hole, removing part of the copper and gold to avoid the copper metal layer and damping effects on the surface of the copper metal layer The first dielectric layer and copper of the present invention can be roughly approximated so as to effectively avoid the electric field concentration to increase the service life and the capacity of the product. Since the present invention first advances to the surface of the barrier layer and only removes the double, it is used again. The second chemical mechanical research layer is from the surface of the first dielectric layer to the surface of the first dielectric layer. Therefore, the polishing rate can be different, and the resulting shallow dish is formed on the premise that the surface of the first dielectric layer on the top of the dual damascene structure is aligned. There will be no bumps at the junction of the layers, and the phenomenon of component collapse caused by them is relatively reliable. The above are only the preferred embodiments of the present invention, and any equivalent changes and modifications made in accordance with the scope of the patent application for the present invention shall fall within the scope of the patent of the present invention. ’

Page 10 1246156 Brief description of the diagrams Brief description of the diagrams Figures 1-4 are schematic diagrams of conventional methods for making metal capacitors. 5 to 10 are schematic diagrams of a method for manufacturing a metal capacitor provided by the present invention. Symbol description

Page 11 10 Semiconductor wafer 12 Substrate 14 First dielectric layer 16 Double damascene 18 Barrier layer 20 Copper metal layer 22 Double damascene structure 24 Second dielectric 26 Metal layer 28 Metal capacitor 40 Semiconductor wafer 42 Substrate 44 No. _ A dielectric layer 46 double inlay holes 48 barrier layer 50 copper metal layer 52 double damascene structure 54 second dielectric 56 metal layer 58 photoresist layer 60 metal layer 62 metal capacitor

Claims (1)

1246156 Amendment No. 90101308 6. Scope of Patent Application 1. A method for avoiding the occurrence of dishing on the top of a dual damascene structure on a semiconductor wafer, the semiconductor wafer includes a substrate, a first dielectric layer On the substrate, a dual damascene hole is provided in the first dielectric layer and reaches the surface of the substrate. A barrier layer covers the surface of the first dielectric layer and the sidewalls in the dual damascene hole. The surface and the bottom surface in the double damascene hole and a copper metal layer are formed on the barrier layer and fill the double damascene hole to form the double damascene structure. The method includes the following steps: Performing a first chemical mechanical polishing (CMP) process to remove part of the copper metal layer and stopping the first chemical mechanical polishing process on the surface of the barrier layer; forming a photoresist layer on the top surface of the dual damascene structure Removing the barrier layer not covered by the photoresist layer; stripping the photoresist layer; and performing a second chemical mechanical polishing process to remove a portion of the copper metal layer so that the copper on top of the dual damascene structure The surface of the metal layer is aligned with the surface of the first dielectric layer. 2. The method according to item 1 of the patent application scope, wherein the double inlay hole is formed by stacking a plug hole and a wire groove. 3. The method according to item 1 of the patent application, wherein the material of the barrier layer includes tantalum (Ta), nitride button (TaN), titanium nitride (TiN), and titanium (Ti). Page 12 1246156 / ——_______________ Case No. 90101308 __ ^ f 7 July _______ Amendment ______________________________________________ VI. Application for Patent Scope 4. If the method of the first scope of patent application is applied, wherein the first dielectric layer It is composed of stone dioxide. 5. The method of claim 1, wherein the method further includes the following steps after the second chemical mechanical polishing process: forming a second dielectric layer on the surface of the semiconductor wafer; and the second dielectric A metal layer is formed in a predetermined area on the layer, so that the copper metal layer, the second dielectric layer and the metal layer form a metal capacitor. 6. —A method for making a metal capacitor on a semiconductor wafer, the semiconductor wafer includes a substrate, a first dielectric layer is disposed on the substrate, and a double damascene hole is disposed in the first dielectric layer and accessible. To the substrate surface, a barrier layer covers the surface of the first dielectric layer, the sidewall surface in the dual damascene hole and the bottom surface in the dual damascene hole, and a first metal layer is formed on the barrier layer and Filling the double damascene hole to form a double damascene structure, the method includes the following steps: performing a first chemical mechanical polishing (CMP) process to remove a portion of the first metal layer and allowing the first chemical mechanical polishing The process stops on the surface of the barrier layer; forms a photoresist layer on the top surface of the dual damascene structure; removes the barrier layer not covered by the photoresist layer; strips off the photoresist layer; performs a second chemical mechanical polishing Process, remove part of the first Page 13 1246156 / ________________________________________________ Case No. 90101308 Amended on July 7, ____________________—— VI. Patent application metal layer, so that the surface of the first metal layer on the top of the dual damascene structure and the surface of the first dielectric layer are cut Forming a second dielectric layer on the surface of the semiconductor wafer; and forming a second metal layer in a predetermined region on the second dielectric layer so that the first metal layer and the second dielectric layer Forming the metal capacitor with the second metal layer. 7. The method according to item 6 of the patent application, wherein the double mosaic hole is formed by stacking a plug hole and a wire groove. 8. The method according to item 6 of the patent application, wherein the material of the barrier layer includes tantalum (Ta), tantalum nitride (TaN), titanium nitride (TiN), and titanium (Ti). 9. The method according to item 6 of the patent application, wherein the first dielectric layer is composed of SiO2. 10. The method according to item 6 of the patent application, wherein the second dielectric layer is composed of an ONO structure or silicon nitride. 521246156 The Year of the Year Figure seven